From 27967a40de5df9ecfa36e9784da9ae4b5f6322b0 Mon Sep 17 00:00:00 2001 From: Roger Chang Date: Mon, 8 May 2023 16:18:48 +0800 Subject: [PATCH] arch-riscv: Fix the fflags issue for fcvt_d_w, fcvt_d_wu, fcvt_d_l fcvt_d_lu These instructions use type casting methods to convert integer to float, so the fflags couldn't trace the event of these. It should use the function xx_to_f64 to convert from integer to float Change-Id: Idd87306f0ca47b65d3faf17f249568330f374b72 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70377 Reviewed-by: Jason Lowe-Power Tested-by: kokoro Maintainer: Jason Lowe-Power --- src/arch/riscv/isa/decoder.isa | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa index 755be3db39..69b3055f1d 100644 --- a/src/arch/riscv/isa/decoder.isa +++ b/src/arch/riscv/isa/decoder.isa @@ -2069,22 +2069,30 @@ decode QUADRANT default Unknown::unknown() { 0x69: decode CONV_SGN { 0x0: fcvt_d_w({{ RM_REQUIRED; - Fd = (double)Rs1_sw; + freg_t fd; + fd = freg(i32_to_f64(Rs1_sw)); + Fd_bits = fd.v; }}, FloatCvtOp); 0x1: fcvt_d_wu({{ RM_REQUIRED; - Fd = (double)Rs1_uw; + freg_t fd; + fd = freg(ui32_to_f64(Rs1_uw)); + Fd_bits = fd.v; }}, FloatCvtOp); 0x2: decode RVTYPE { 0x1: fcvt_d_l({{ RM_REQUIRED; - Fd = (double)Rs1_sd; + freg_t fd; + fd = freg(i64_to_f64(Rs1_sd)); + Fd_bits = fd.v; }}, FloatCvtOp); } 0x3: decode RVTYPE { 0x1: fcvt_d_lu({{ RM_REQUIRED; - Fd = (double)Rs1; + freg_t fd; + fd = freg(ui64_to_f64(Rs1)); + Fd_bits = fd.v; }}, FloatCvtOp); } }