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arch-arm: Remove ISA::initID32

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Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I70cce0b9d99ed5fe146e64c6ee55fa8cedf98ac6
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70467
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Giacomo Travaglini
2023-02-03 19:38:24 +01:00
parent 7abece9d0f
commit b7c16f0dad
3 changed files with 46 additions and 54 deletions
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53
src/arch/arm/isa.cc
View File

@@ -142,8 +142,6 @@ ISA::clear()
miscRegs[idx] = lookUpMiscReg[idx].reset();
}
initID32(p);
// We always initialize AArch64 ID registers even
// if we are in AArch32. This is done since if we
// are in SE mode we don't know if our ArmProcess is
@@ -257,57 +255,6 @@ ISA::clear64(const ArmISAParams &p)
}
}
void
ISA::initID32(const ArmISAParams &p)
{
// Initialize configurable default values
uint32_t midr;
if (p.midr != 0x0)
midr = p.midr;
else if (highestELIs64)
// Cortex-A57 TRM r0p0 MIDR
midr = 0x410fd070;
else
// Cortex-A15 TRM r0p0 MIDR
midr = 0x410fc0f0;
miscRegs[MISCREG_MIDR] = midr;
miscRegs[MISCREG_VPIDR] = midr;
miscRegs[MISCREG_ID_ISAR0] = p.id_isar0;
miscRegs[MISCREG_ID_ISAR1] = p.id_isar1;
miscRegs[MISCREG_ID_ISAR2] = p.id_isar2;
miscRegs[MISCREG_ID_ISAR3] = p.id_isar3;
miscRegs[MISCREG_ID_ISAR4] = p.id_isar4;
miscRegs[MISCREG_ID_MMFR0] = p.id_mmfr0;
miscRegs[MISCREG_ID_MMFR1] = p.id_mmfr1;
miscRegs[MISCREG_ID_MMFR2] = p.id_mmfr2;
miscRegs[MISCREG_ID_MMFR3] = p.id_mmfr3;
miscRegs[MISCREG_ID_MMFR4] = p.id_mmfr4;
ISAR5 isar5 = p.id_isar5;
if (release->has(ArmExtension::CRYPTO)) {
isar5.crc32 = 1;
isar5.sha2 = 1;
isar5.sha1 = 1;
isar5.aes = 2;
} else {
isar5.crc32 = 0;
isar5.sha2 = 0;
isar5.sha1 = 0;
isar5.aes = 0;
}
isar5.rdm = release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0;
isar5.vcma = release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0;
miscRegs[MISCREG_ID_ISAR5] = isar5;
ISAR6 isar6 = p.id_isar6;
isar6.jscvt = release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0;
miscRegs[MISCREG_ID_ISAR6] = isar6;
}
void
ISA::initID64(const ArmISAParams &p)
{

1
src/arch/arm/isa.hh
View File

@@ -172,7 +172,6 @@ namespace ArmISA
protected:
void clear32(const ArmISAParams &p);
void clear64(const ArmISAParams &p);
void initID32(const ArmISAParams &p);
void initID64(const ArmISAParams &p);
void addressTranslation(MMU::ArmTranslationType tran_type,

46
src/arch/arm/regs/misc.cc
View File

@@ -45,6 +45,7 @@
#include "cpu/thread_context.hh"
#include "dev/arm/gic_v3_cpu_interface.hh"
#include "sim/full_system.hh"
#include "params/ArmISA.hh"
namespace gem5
{
@@ -2116,6 +2117,17 @@ ISA::initializeMiscRegMetadata()
const bool vhe_implemented = release->has(ArmExtension::FEAT_VHE);
const bool sel2_implemented = release->has(ArmExtension::FEAT_SEL2);
const Params &p(params());
uint32_t midr;
if (p.midr != 0x0)
midr = p.midr;
else if (highestELIs64)
// Cortex-A57 TRM r0p0 MIDR
midr = 0x410fd070;
else
// Cortex-A15 TRM r0p0 MIDR
midr = 0x410fc0f0;
/**
* Some registers alias with others, and therefore need to be translated.
@@ -2465,6 +2477,7 @@ ISA::initializeMiscRegMetadata()
// AArch32 CP15 registers
InitReg(MISCREG_MIDR)
.reset(midr)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_CTR)
.allPrivileges().exceptUserMode().writes(0);
@@ -2488,28 +2501,60 @@ ISA::initializeMiscRegMetadata()
InitReg(MISCREG_ID_AFR0)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_MMFR0)
.reset(p.id_mmfr0)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_MMFR1)
.reset(p.id_mmfr1)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_MMFR2)
.reset(p.id_mmfr2)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_MMFR3)
.reset(p.id_mmfr3)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_MMFR4)
.reset(p.id_mmfr4)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_ISAR0)
.reset(p.id_isar0)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_ISAR1)
.reset(p.id_isar1)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_ISAR2)
.reset(p.id_isar2)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_ISAR3)
.reset(p.id_isar3)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_ISAR4)
.reset(p.id_isar4)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_ISAR5)
.reset([p,release=release] () {
ISAR5 isar5 = p.id_isar5;
if (release->has(ArmExtension::CRYPTO)) {
isar5.crc32 = 1;
isar5.sha2 = 1;
isar5.sha1 = 1;
isar5.aes = 2;
} else {
isar5.crc32 = 0;
isar5.sha2 = 0;
isar5.sha1 = 0;
isar5.aes = 0;
}
isar5.rdm = release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0;
isar5.vcma = release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0;
return isar5;
}())
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_ISAR6)
.reset([p,release=release] () {
ISAR6 isar6 = p.id_isar6;
isar6.jscvt = release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0;
return isar6;
}())
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_CCSIDR)
.allPrivileges().exceptUserMode().writes(0);
@@ -2527,6 +2572,7 @@ ISA::initializeMiscRegMetadata()
.bankedChild()
.secure().exceptUserMode();
InitReg(MISCREG_VPIDR)
.reset(midr)
.hyp().monNonSecure();
InitReg(MISCREG_VMPIDR)
.hyp().monNonSecure();