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arch-riscv: Refactor RVC decode flow when funct4==0b1001 and op==C2

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the compressed instruction 0x901e (c.add zero, t2) should be decoded as
"c_add zero, t2" not c_ebreak

Change-Id: Ib2bd4b4d9739aa27ad290ead313e95b11b1727d1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70358
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Roger Chang
2023-05-08 14:30:04 +08:00
parent d2aed4f5c5
commit 8dac7f572b
1 changed files with 11 additions and 17 deletions
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28
src/arch/riscv/isa/decoder.isa
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@@ -365,27 +365,21 @@ decode QUADRANT default Unknown::unknown() {
Rc1 = rvSext(Rc2);
}});
}
0x1: decode RC1 {
0x0: SystemOp::c_ebreak({{
if (RC2 != 0) {
return std::make_shared<IllegalInstFault>(
"source reg x1", machInst);
}
return std::make_shared<BreakpointFault>(xc->pcState());
}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
default: decode RC2 {
0x0: Jump::c_jalr({{
if (RC1 == 0) {
return std::make_shared<IllegalInstFault>(
"source reg x0", machInst);
}
0x1: decode RC2 {
0x0: decode RC1 {
0x0: SystemOp::c_ebreak({{
return std::make_shared<BreakpointFault>(
xc->pcState());
}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
default: Jump::c_jalr({{
ra = rvSext(NPC);
NPC = rvZext(Rc1);
}}, IsIndirectControl, IsUncondControl, IsCall);
default: CompressedROp::c_add({{
Rc1_sd = rvSext(Rc1_sd + Rc2_sd);
}});
}
default: CompressedROp::c_add({{
// RC1 == 0 is HINT
Rc1_sd = rvSext(Rc1_sd + Rc2_sd);
}});
}
}
format CompressedStore {