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arch-arm: Simplify FPSCR writes

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The old logic was setting up a mask which was covering pretty much
the entire register, except for the FPSCR[14:13] and FPSCR[6:5]
register fields. Those RES0 fields were treated as WI.
We simplify this by explicitly marking them as RES0 at construction
time

Change-Id: I59942bd98c074349307d27e3a99351ee25f4db95
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70565
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2023-02-08 10:48:29 +00:00
parent 3e1b9dfc0f
commit 60dd3c7d05
2 changed files with 2 additions and 32 deletions
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33
src/arch/arm/isa.cc
View File

@@ -815,38 +815,7 @@ ISA::setMiscReg(RegIndex idx, RegVal val)
return;
case MISCREG_FPSCR:
{
const uint32_t ones = (uint32_t)(-1);
FPSCR fpscrMask = 0;
fpscrMask.ioc = ones;
fpscrMask.dzc = ones;
fpscrMask.ofc = ones;
fpscrMask.ufc = ones;
fpscrMask.ixc = ones;
fpscrMask.idc = ones;
fpscrMask.ioe = ones;
fpscrMask.dze = ones;
fpscrMask.ofe = ones;
fpscrMask.ufe = ones;
fpscrMask.ixe = ones;
fpscrMask.ide = ones;
fpscrMask.len = ones;
fpscrMask.fz16 = ones;
fpscrMask.stride = ones;
fpscrMask.rMode = ones;
fpscrMask.fz = ones;
fpscrMask.dn = ones;
fpscrMask.ahp = ones;
fpscrMask.qc = ones;
fpscrMask.v = ones;
fpscrMask.c = ones;
fpscrMask.z = ones;
fpscrMask.n = ones;
newVal = (newVal & (uint32_t)fpscrMask) |
(readMiscRegNoEffect(MISCREG_FPSCR) &
~(uint32_t)fpscrMask);
tc->getDecoderPtr()->as<Decoder>().setContext(newVal);
}
tc->getDecoderPtr()->as<Decoder>().setContext(newVal);
break;
case MISCREG_FPSR:
{

1
src/arch/arm/regs/misc.cc
View File

@@ -2199,6 +2199,7 @@ ISA::initializeMiscRegMetadata()
.reset(p.fpsid)
.allPrivileges();
InitReg(MISCREG_FPSCR)
.res0(mask(14, 13) | mask(6, 5))
.allPrivileges();
InitReg(MISCREG_MVFR1)
.reset([] () {