arch-arm: Implement RES0/RES1 with miscreg specifiers
Change-Id: Ic2caea121e02f63f069f1576760c849bcbdac894 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Richard Cooper <richard.cooper@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70563 Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
@@ -421,11 +421,6 @@ ISA::readMiscReg(RegIndex idx)
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idx = redirectRegVHE(idx);
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switch (unflattenMiscReg(idx)) {
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case MISCREG_HCR:
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case MISCREG_HCR2:
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if (!release->has(ArmExtension::VIRTUALIZATION))
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return 0;
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break;
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case MISCREG_CPACR:
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{
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const uint32_t ones = (uint32_t)(-1);
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@@ -456,10 +451,6 @@ ISA::readMiscReg(RegIndex idx)
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case MISCREG_MPIDR:
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case MISCREG_MPIDR_EL1:
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return readMPIDR(system, tc);
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case MISCREG_VMPIDR:
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case MISCREG_VMPIDR_EL2:
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// top bit defined as RES1
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return readMiscRegNoEffect(idx) | 0x80000000;
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case MISCREG_ID_AFR0: // not implemented, so alias MIDR
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case MISCREG_REVIDR: // not implemented, so alias MIDR
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case MISCREG_MIDR:
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@@ -568,10 +559,6 @@ ISA::readMiscReg(RegIndex idx)
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{
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return miscRegs[MISCREG_CPSR] & 0x800000;
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}
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case MISCREG_SVCR:
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{
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return miscRegs[MISCREG_SVCR];
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}
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case MISCREG_L2CTLR:
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{
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// mostly unimplemented, just set NumCPUs field from sim and return
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@@ -594,20 +581,17 @@ ISA::readMiscReg(RegIndex idx)
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}
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case MISCREG_HCPTR:
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{
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RegVal val = readMiscRegNoEffect(idx);
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// The trap bit associated with CP14 is defined as RAZ
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val &= ~(1 << 14);
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// If a CP bit in NSACR is 0 then the corresponding bit in
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// HCPTR is RAO/WI
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HCPTR val = readMiscRegNoEffect(idx);
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bool secure_lookup = release->has(ArmExtension::SECURITY) &&
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isSecure(tc);
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if (!secure_lookup) {
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RegVal mask = readMiscRegNoEffect(MISCREG_NSACR);
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val |= (mask ^ 0x7FFF) & 0xBFFF;
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NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
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if (!nsacr.cp10) {
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val.tcp10 = 1;
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val.tcp11 = 1;
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}
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}
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// Set the bits for unimplemented coprocessors to RAO/WI
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val |= 0x33FF;
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return (val);
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return val;
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}
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case MISCREG_HDFAR: // alias for secure DFAR
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return readMiscRegNoEffect(MISCREG_DFAR_S);
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@@ -934,16 +918,10 @@ ISA::setMiscReg(RegIndex idx, RegVal val)
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(readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
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}
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break;
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case MISCREG_HCR2:
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if (!release->has(ArmExtension::VIRTUALIZATION))
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return;
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break;
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case MISCREG_HCR:
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{
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const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
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selfDebug->setenableTDETGE((HCR)val, mdcr);
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if (!release->has(ArmExtension::VIRTUALIZATION))
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return;
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}
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break;
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@@ -1016,31 +994,6 @@ ISA::setMiscReg(RegIndex idx, RegVal val)
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case MISCREG_DBGWCR0_EL1 ... MISCREG_DBGWCR15_EL1:
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selfDebug->updateDBGWCR(idx - MISCREG_DBGWCR0_EL1, val);
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break;
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case MISCREG_IFSR:
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{
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// ARM ARM (ARM DDI 0406C.b) B4.1.96
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const uint32_t ifsrMask =
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mask(31, 13) | mask(11, 11) | mask(8, 6);
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newVal = newVal & ~ifsrMask;
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}
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break;
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case MISCREG_DFSR:
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{
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// ARM ARM (ARM DDI 0406C.b) B4.1.52
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const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
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newVal = newVal & ~dfsrMask;
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}
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break;
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case MISCREG_AMAIR0:
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case MISCREG_AMAIR1:
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{
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// ARM ARM (ARM DDI 0406C.b) B4.1.5
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// Valid only with LPAE
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if (!release->has(ArmExtension::LPAE))
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return;
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DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
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}
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break;
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case MISCREG_SCR:
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getMMUPtr(tc)->invalidateMiscReg();
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break;
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@@ -1327,21 +1280,6 @@ ISA::setMiscReg(RegIndex idx, RegVal val)
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idx = MISCREG_CPSR;
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}
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break;
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case MISCREG_SVCR:
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{
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SVCR svcr = miscRegs[MISCREG_SVCR];
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SVCR newSvcr = newVal;
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// Don't allow other bits to be set
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svcr.sm = newSvcr.sm;
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svcr.za = newSvcr.za;
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newVal = svcr;
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}
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break;
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case MISCREG_SMPRI_EL1:
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// Only the bottom 4 bits are settable
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newVal = newVal & 0xF;
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break;
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case MISCREG_AT_S1E1R_Xt:
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addressTranslation64(MMU::S1E1Tran, BaseMMU::Read, 0, val);
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return;
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@@ -2662,6 +2662,7 @@ ISA::initializeMiscRegMetadata()
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.reset(midr)
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.hyp().monNonSecure();
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InitReg(MISCREG_VMPIDR)
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.res1(mask(31, 31))
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.hyp().monNonSecure();
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InitReg(MISCREG_SCTLR)
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.banked()
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@@ -2739,13 +2740,17 @@ ISA::initializeMiscRegMetadata()
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.hyp().monNonSecure();
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InitReg(MISCREG_HCR)
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.hyp().monNonSecure()
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.res0(0x90000000);
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.res0(release->has(ArmExtension::VIRTUALIZATION) ?
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0x90000000 : mask(31, 0));
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InitReg(MISCREG_HCR2)
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.hyp().monNonSecure()
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.res0(0xffa9ff8c);
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.res0(release->has(ArmExtension::VIRTUALIZATION) ?
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0xffa9ff8c : mask(31, 0));
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InitReg(MISCREG_HDCR)
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.hyp().monNonSecure();
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InitReg(MISCREG_HCPTR)
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.res0(mask(29, 21) | mask(19, 16) | mask(14, 14))
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.res1(mask(13, 12) | mask(9, 0))
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.hyp().monNonSecure();
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InitReg(MISCREG_HSTR)
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.hyp().monNonSecure();
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@@ -2794,7 +2799,8 @@ ISA::initializeMiscRegMetadata()
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.bankedChild()
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.secure().exceptUserMode();
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InitReg(MISCREG_DFSR)
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.banked();
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.banked()
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.res0(mask(31, 14) | mask(8, 8));
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InitReg(MISCREG_DFSR_NS)
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.bankedChild()
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.privSecure(!aarch32EL3)
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@@ -2803,7 +2809,8 @@ ISA::initializeMiscRegMetadata()
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.bankedChild()
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.secure().exceptUserMode();
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InitReg(MISCREG_IFSR)
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.banked();
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.banked()
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.res0(mask(31, 13) | mask(11, 11) | mask(8, 6));
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InitReg(MISCREG_IFSR_NS)
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.bankedChild()
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.privSecure(!aarch32EL3)
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@@ -3118,6 +3125,7 @@ ISA::initializeMiscRegMetadata()
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.bankedChild()
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.secure().exceptUserMode();
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InitReg(MISCREG_AMAIR0)
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.res0(release->has(ArmExtension::LPAE) ? 0 : mask(31, 0))
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.banked();
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InitReg(MISCREG_AMAIR0_NS)
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.bankedChild()
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@@ -3127,6 +3135,7 @@ ISA::initializeMiscRegMetadata()
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.bankedChild()
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.secure().exceptUserMode();
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InitReg(MISCREG_AMAIR1)
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.res0(release->has(ArmExtension::LPAE) ? 0 : mask(31, 0))
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.banked();
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InitReg(MISCREG_AMAIR1_NS)
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.bankedChild()
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@@ -3976,6 +3985,8 @@ ISA::initializeMiscRegMetadata()
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.mapsTo(MISCREG_VPIDR);
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InitReg(MISCREG_VMPIDR_EL2)
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.hyp().mon()
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.res0(mask(63, 40) | mask(29, 25))
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.res1(mask(31, 31))
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.mapsTo(MISCREG_VMPIDR);
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InitReg(MISCREG_SCTLR_EL1)
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.allPrivileges().exceptUserMode()
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@@ -5263,6 +5274,12 @@ ISA::initializeMiscRegMetadata()
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}())
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.allPrivileges().exceptUserMode().writes(0);
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InitReg(MISCREG_SVCR)
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.res0([](){
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SVCR svcr_mask = 0;
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svcr_mask.sm = 1;
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svcr_mask.za = 1;
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return ~svcr_mask;
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}())
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.allPrivileges();
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InitReg(MISCREG_SMIDR_EL1)
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.reset([](){
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@@ -5274,6 +5291,7 @@ ISA::initializeMiscRegMetadata()
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}())
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.allPrivileges().exceptUserMode().writes(0);
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InitReg(MISCREG_SMPRI_EL1)
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.res0(mask(63, 4))
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.allPrivileges().exceptUserMode().reads(1);
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InitReg(MISCREG_SMPRIMAP_EL2)
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.hyp().mon();
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