arch-riscv: Simplify amd merge RV32/RV64 the RVM instructions
The change move the details implementation to utility.hh and merge the RV32 and RV64 versions into one. Change-Id: I438bfb0fc511f0f27e83f247d386c58493db65b4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70597 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Yu-hsin Wang <yuhsingw@google.com> Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
This commit is contained in:
Roger Chang
@@ -1084,34 +1084,13 @@ decode QUADRANT default Unknown::unknown() {
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0x0: sll({{
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Rd = rvSext(Rs1 << rvSelect(Rs2<4:0>, Rs2<5:0>));
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}});
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0x1: decode RVTYPE {
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0x0: rv32_mulh({{
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Rd_sw = ((int64_t)Rs1_sw * Rs2_sw) >> 32;
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}}, IntMultOp);
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0x1: mulh({{
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bool negate = (Rs1_sd < 0) != (Rs2_sd < 0);
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uint64_t Rs1_lo = (uint32_t)std::abs(Rs1_sd);
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uint64_t Rs1_hi = (uint64_t)std::abs(Rs1_sd) >> 32;
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uint64_t Rs2_lo = (uint32_t)std::abs(Rs2_sd);
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uint64_t Rs2_hi = (uint64_t)std::abs(Rs2_sd) >> 32;
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uint64_t hi = Rs1_hi*Rs2_hi;
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uint64_t mid1 = Rs1_hi*Rs2_lo;
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uint64_t mid2 = Rs1_lo*Rs2_hi;
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uint64_t lo = Rs2_lo*Rs1_lo;
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uint64_t carry = ((uint64_t)(uint32_t)mid1
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+ (uint64_t)(uint32_t)mid2
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+ (lo >> 32)) >> 32;
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uint64_t res = hi +
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(mid1 >> 32) +
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(mid2 >> 32) +
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carry;
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Rd = negate ? ~res + (Rs1_sd*Rs2_sd == 0 ? 1 : 0)
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: res;
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}}, IntMultOp);
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}
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0x1: mulh({{
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if (machInst.rv_type == RV32) {
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Rd_sd = mulh_32(Rs1_sd, Rs2_sd);
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} else {
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Rd_sd = mulh_64(Rs1_sd, Rs2_sd);
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}
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}}, IntMultOp);
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0x5: clmul({{
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uint64_t result = 0;
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for (int i = 0; i < rvSelect(32, 64); i++) {
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@@ -1144,32 +1123,13 @@ decode QUADRANT default Unknown::unknown() {
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0x0: slt({{
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Rd = (rvSext(Rs1_sd) < rvSext(Rs2_sd)) ? 1 : 0;
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}});
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0x1: decode RVTYPE {
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0x0: rv32_mulhsu({{
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Rd_sw = ((int64_t)Rs1_sw * Rs2_uw) >> 32;
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}}, IntMultOp);
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0x1: mulhsu({{
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bool negate = Rs1_sd < 0;
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uint64_t Rs1_lo = (uint32_t)std::abs(Rs1_sd);
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uint64_t Rs1_hi = (uint64_t)std::abs(Rs1_sd) >> 32;
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uint64_t Rs2_lo = (uint32_t)Rs2;
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uint64_t Rs2_hi = Rs2 >> 32;
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uint64_t hi = Rs1_hi*Rs2_hi;
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uint64_t mid1 = Rs1_hi*Rs2_lo;
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uint64_t mid2 = Rs1_lo*Rs2_hi;
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uint64_t lo = Rs1_lo*Rs2_lo;
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uint64_t carry = ((uint64_t)(uint32_t)mid1
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+ (uint64_t)(uint32_t)mid2
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+ (lo >> 32)) >> 32;
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uint64_t res = hi +
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(mid1 >> 32) +
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(mid2 >> 32) +
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carry;
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Rd = negate ? ~res + (Rs1_sd*Rs2 == 0 ? 1 : 0) : res;
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}}, IntMultOp);
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}
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0x1: mulhsu({{
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if (machInst.rv_type == RV32) {
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Rd_sd = mulhsu_32(Rs1_sd, Rs2);
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} else {
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Rd_sd = mulhsu_64(Rs1_sd, Rs2);
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}
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}}, IntMultOp);
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0x5: clmulr({{
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uint64_t result = 0;
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uint64_t xlen = rvSelect(32, 64);
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@@ -1197,27 +1157,13 @@ decode QUADRANT default Unknown::unknown() {
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0x0: sltu({{
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Rd = (rvZext(Rs1) < rvZext(Rs2)) ? 1 : 0;
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}});
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0x1: decode RVTYPE {
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0x0: rv32_mulhu({{
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Rd_sw = ((uint64_t)Rs1_uw * Rs2_uw) >> 32;
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}}, IntMultOp);
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0x1: mulhu({{
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uint64_t Rs1_lo = (uint32_t)Rs1;
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uint64_t Rs1_hi = Rs1 >> 32;
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uint64_t Rs2_lo = (uint32_t)Rs2;
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uint64_t Rs2_hi = Rs2 >> 32;
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uint64_t hi = Rs1_hi*Rs2_hi;
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uint64_t mid1 = Rs1_hi*Rs2_lo;
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uint64_t mid2 = Rs1_lo*Rs2_hi;
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uint64_t lo = Rs1_lo*Rs2_lo;
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uint64_t carry = ((uint64_t)(uint32_t)mid1
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+ (uint64_t)(uint32_t)mid2
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+ (lo >> 32)) >> 32;
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Rd = hi + (mid1 >> 32) + (mid2 >> 32) + carry;
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}}, IntMultOp);
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}
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0x1: mulhu({{
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if (machInst.rv_type == RV32) {
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Rd = (int32_t)mulhu_32(Rs1, Rs2);
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} else {
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Rd = mulhu_64(Rs1, Rs2);
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}
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}}, IntMultOp);
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0x5: clmulh({{
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uint64_t result = 0;
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uint64_t xlen = rvSelect(32, 64);
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@@ -1235,30 +1181,13 @@ decode QUADRANT default Unknown::unknown() {
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0x0: xor({{
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Rd = rvSext(Rs1 ^ Rs2);
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}});
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0x1: decode RVTYPE {
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0x0: rv32_div({{
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constexpr int32_t kRsMin = \
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std::numeric_limits<int32_t>::min();
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if (Rs2_sw == 0) {
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Rd_sw = -1;
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} else if (Rs1_sw == kRsMin && Rs2_sw == -1) {
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Rd_sw = kRsMin;
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} else {
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Rd_sw = Rs1_sw/Rs2_sw;
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}
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}}, IntDivOp);
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0x1: div({{
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constexpr int64_t kRsMin = \
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std::numeric_limits<int64_t>::min();
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if (Rs2_sd == 0) {
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Rd_sd = -1;
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} else if (Rs1_sd == kRsMin && Rs2_sd == -1) {
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Rd_sd = kRsMin;
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} else {
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Rd_sd = Rs1_sd/Rs2_sd;
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}
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}}, IntDivOp);
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}
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0x1: div({{
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if (machInst.rv_type == RV32) {
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Rd_sd = div<int32_t>(Rs1, Rs2);
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} else {
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Rd_sd = div<int64_t>(Rs1, Rs2);
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}
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}}, IntDivOp);
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0x4: pack({{
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int xlen = rvSelect(32, 64);
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Rd = rvSext(
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@@ -1289,22 +1218,13 @@ decode QUADRANT default Unknown::unknown() {
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Rd = rvSext(rvZext(Rs1) >>
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rvSelect(Rs2<4:0>, Rs2<5:0>));
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}});
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0x1: decode RVTYPE {
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0x0: rv32_divu({{
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if (Rs2_uw == 0) {
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Rd_sw = std::numeric_limits<uint32_t>::max();
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} else {
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Rd_sw = Rs1_uw/Rs2_uw;
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}
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}}, IntDivOp);
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0x1: divu({{
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if (Rs2 == 0) {
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Rd = std::numeric_limits<uint64_t>::max();
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} else {
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Rd = Rs1/Rs2;
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}
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}}, IntDivOp);
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}
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0x1: divu({{
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if (machInst.rv_type == RV32) {
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Rd = (int32_t)divu<uint32_t>(Rs1, Rs2);
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} else {
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Rd = divu<uint64_t>(Rs1, Rs2);
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}
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}}, IntDivOp);
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0x20: sra({{
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Rd = rvSext(Rs1_sd) >> rvSelect(Rs2<4:0>, Rs2<5:0>);
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}});
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@@ -1327,30 +1247,13 @@ decode QUADRANT default Unknown::unknown() {
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0x0: or({{
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Rd = rvSext(Rs1 | Rs2);
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}});
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0x1: decode RVTYPE {
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0x0: rv32_rem({{
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constexpr int32_t kRsMin = \
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std::numeric_limits<int32_t>::min();
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if (Rs2_sw == 0) {
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Rd_sw = Rs1_sw;
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} else if (Rs1_sw == kRsMin && Rs2_sw == -1) {
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Rd_sw = 0;
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} else {
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Rd_sw = Rs1_sw%Rs2_sw;
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}
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}}, IntDivOp);
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0x1: rem({{
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constexpr int64_t kRsMin = \
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std::numeric_limits<int64_t>::min();
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if (Rs2_sd == 0) {
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Rd = Rs1_sd;
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} else if (Rs1_sd == kRsMin && Rs2_sd == -1) {
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Rd = 0;
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} else {
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Rd = Rs1_sd%Rs2_sd;
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}
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}}, IntDivOp);
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}
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0x1: rem({{
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if (machInst.rv_type == RV32) {
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Rd_sd = rem<int32_t>(Rs1, Rs2);
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} else {
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Rd_sd = rem<int64_t>(Rs1, Rs2);
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}
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}}, IntDivOp);
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0x5: max({{
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Rd_sd = std::max(rvSext(Rs1_sd), rvSext(Rs2_sd));
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}});
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@@ -1365,22 +1268,13 @@ decode QUADRANT default Unknown::unknown() {
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0x0: and({{
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Rd = rvSext(Rs1 & Rs2);
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}});
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0x1: decode RVTYPE {
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0x0: rv32_remu({{
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if (Rs2_uw == 0) {
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Rd_sw = Rs1_uw;
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} else {
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Rd_sw = Rs1_uw%Rs2_uw;
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}
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}}, IntDivOp);
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0x1: remu({{
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if (Rs2 == 0) {
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Rd = Rs1;
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} else {
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Rd = Rs1%Rs2;
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}
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}}, IntDivOp);
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}
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0x1: remu({{
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if (machInst.rv_type == RV32) {
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Rd = (int32_t)remu<uint32_t>(Rs1, Rs2);
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} else {
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Rd = remu<uint64_t>(Rs1, Rs2);
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}
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}}, IntDivOp);
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0x4: packh({{
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// It doesn't need to sign ext as MSB is always 0
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Rd = (Rs2_ub << 8) | Rs1_ub;
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@@ -1432,15 +1326,7 @@ decode QUADRANT default Unknown::unknown() {
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}
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0x4: decode FUNCT7 {
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0x1: divw({{
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constexpr int32_t kRsMin = \
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std::numeric_limits<int32_t>::min();
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if (Rs2_sw == 0) {
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Rd_sd = -1;
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} else if (Rs1_sw == kRsMin && Rs2_sw == -1) {
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Rd_sd = kRsMin;
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} else {
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Rd_sd = Rs1_sw/Rs2_sw;
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}
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Rd_sd = div<int32_t>(Rs1, Rs2);
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}}, IntDivOp);
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0x4: packw({{
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Rd_sd = sext<32>((Rs2_uh << 16) | Rs1_uh);
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@@ -1454,11 +1340,7 @@ decode QUADRANT default Unknown::unknown() {
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Rd_sd = (int32_t)(Rs1_uw >> Rs2<4:0>);
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}});
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0x1: divuw({{
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if (Rs2_uw == 0) {
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Rd_sd = std::numeric_limits<uint64_t>::max();
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} else {
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Rd_sd = (int32_t)(Rs1_uw/Rs2_uw);
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}
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Rd = sext<32>(divu<uint32_t>(Rs1, Rs2));
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}}, IntDivOp);
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0x20: sraw({{
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Rd_sd = Rs1_sw >> Rs2<4:0>;
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@@ -1470,26 +1352,14 @@ decode QUADRANT default Unknown::unknown() {
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}
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0x6: decode FUNCT7 {
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0x1: remw({{
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constexpr int32_t kRsMin = \
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std::numeric_limits<int32_t>::min();
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if (Rs2_sw == 0) {
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Rd_sd = Rs1_sw;
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} else if (Rs1_sw == kRsMin && Rs2_sw == -1) {
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Rd_sd = 0;
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} else {
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Rd_sd = Rs1_sw%Rs2_sw;
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}
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Rd_sd = rem<int32_t>(Rs1, Rs2);
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}}, IntDivOp);
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0x10: sh3add_uw({{
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Rd = (((uint64_t)Rs1_uw) << 3) + Rs2;
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}});
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}
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0x7: remuw({{
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if (Rs2_uw == 0) {
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Rd_sd = (int32_t)Rs1_uw;
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} else {
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Rd_sd = (int32_t)(Rs1_uw%Rs2_uw);
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}
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Rd = sext<32>(remu<uint32_t>(Rs1, Rs2));
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}}, IntDivOp);
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}
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}
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@@ -55,6 +55,7 @@
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#include "cpu/reg_class.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/thread_context.hh"
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#include "enums/RiscvType.hh"
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#include "rvk.hh"
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namespace gem5
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@@ -137,6 +138,101 @@ registerName(RegId reg)
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}
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}
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inline uint32_t
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mulhu_32(uint32_t rs1, uint32_t rs2)
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{
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return ((uint64_t)rs1 * rs2) >> 32;
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}
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inline uint64_t
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mulhu_64(uint64_t rs1, uint64_t rs2)
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{
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uint64_t rs1_lo = (uint32_t)rs1;
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uint64_t rs1_hi = rs1 >> 32;
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uint64_t rs2_lo = (uint32_t)rs2;
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uint64_t rs2_hi = rs2 >> 32;
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uint64_t hi = rs1_hi * rs2_hi;
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uint64_t mid1 = rs1_hi * rs2_lo;
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uint64_t mid2 = rs1_lo * rs2_hi;
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uint64_t lo = rs1_lo * rs2_lo;
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uint64_t carry = ((uint64_t)(uint32_t)mid1
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+ (uint64_t)(uint32_t)mid2
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+ (lo >> 32)) >> 32;
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return hi + (mid1 >> 32) + (mid2 >> 32) + carry;
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}
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inline int32_t
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mulh_32(int32_t rs1, int32_t rs2)
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{
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return ((int64_t)rs1 * rs2) >> 32;
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}
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inline int64_t
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mulh_64(int64_t rs1, int64_t rs2)
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{
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bool negate = (rs1 < 0) != (rs2 < 0);
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uint64_t res = mulhu_64(std::abs(rs1), std::abs(rs2));
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return negate ? ~res + (rs1 * rs2 == 0 ? 1 : 0) : res;
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}
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inline int32_t
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mulhsu_32(int32_t rs1, uint32_t rs2)
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{
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return ((int64_t)rs1 * rs2) >> 32;
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}
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inline int64_t
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mulhsu_64(int64_t rs1, uint64_t rs2)
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{
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bool negate = rs1 < 0;
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uint64_t res = mulhu_64(std::abs(rs1), rs2);
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return negate ? ~res + (rs1 * rs2 == 0 ? 1 : 0) : res;
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}
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template<typename T> inline T
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div(T rs1, T rs2)
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{
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constexpr T kRsMin = std::numeric_limits<T>::min();
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if (rs2 == 0) {
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return -1;
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} else if (rs1 == kRsMin && rs2 == -1) {
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return kRsMin;
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} else {
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return rs1 / rs2;
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}
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}
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template<typename T> inline T
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divu(T rs1, T rs2)
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{
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if (rs2 == 0) {
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return std::numeric_limits<T>::max();
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} else {
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return rs1 / rs2;
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}
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}
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template<typename T> inline T
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rem(T rs1, T rs2)
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{
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constexpr T kRsMin = std::numeric_limits<T>::min();
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if (rs2 == 0) {
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return rs1;
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} else if (rs1 == kRsMin && rs2 == -1) {
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return 0;
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} else {
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return rs1 % rs2;
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}
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}
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template<typename T> inline T
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remu(T rs1, T rs2)
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{
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return (rs2 == 0) ? rs1 : rs1 % rs2;
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}
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} // namespace RiscvISA
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} // namespace gem5
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Block a user