Commit Graph

2206 Commits

Author SHA1 Message Date
Gabe Black
02ae343c66 misc: Replace M5_CLASS_VAR_USED with GEM5_CLASS_VAR_USED.
Change-Id: Ibd2230d684f41201b07fa9083881145e36176a68
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45241
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-05-11 20:16:31 +00:00
Gabe Black
97ef1472ad misc: Replace M5_LOCAL and M5_WEAK with GEM5_LOCAL and GEM5_WEAK.
Change-Id: Ieb8350e647480f9bf582479b7933f0462f18d14d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45236
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-05-11 20:16:31 +00:00
Gabe Black
ce6b5e7e33 misc: Replace M5_ATTR_PACKED with GEM5_PACKED.
Change-Id: Ie59071ca1fc81a76267a54ddd2d35dfc4477995d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45234
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-05-11 20:16:31 +00:00
Gabe Black
11fe13c311 misc: Replace M5_FALLTHROUGH with GEM5_FALLTHROUGH.
Change-Id: I058f311b6d9c284f745bcc915db72236d05db21b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45233
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-11 20:16:31 +00:00
Gabe Black
fb3befcc6d misc: Replace M5_VAR_USED with GEM5_VAR_USED.
Change-Id: I64a874ccd1a9ac0541dfa01971d7d620a98c9d32
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45231
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-05-11 20:16:31 +00:00
Gabe Black
f2d3011333 cpu: Get rid of the redundant PhysRegIndex type.
It was defined to be effectively the same type as RegIndex, which is a
uint16_t. Having two types for essentially the same thing (which the
compiler would treat as equivalent) adds unnecessary complexity.

Change-Id: Ibf6badc19e3b0a27c3bc3e68def1e686dbef3ea8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45228
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-05-10 20:04:00 +00:00
Gabe Black
8f0b33612e cpu: Get rid of the unused NumRegClasses constant.
Change-Id: Icb2918a97f58a79159307a5d7cba877899268caa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45227
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-05-10 20:03:49 +00:00
Gabe Black
16fa9f9812 arch,cpu: Get rid of is*Reg() methods in RegId.
These bake in the existing set of RegClass values and are not flexible
or scalable.

Change-Id: I107460cd82960d96916d1644403b7635820045a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45226
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-10 20:03:38 +00:00
Gabe Black
ed5832c273 cpu: Delete an unnecessary return in RegId::flatIndex.
panic() is marked [[noreturn]], so there's no need to put a dummy return
after it.

Change-Id: Icebba480ef583a149188d4d6f9481fe0bbd95082
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45225
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-05-10 20:03:26 +00:00
Gabe Black
41d934cf18 misc: Collapse all uses of DTRACE(x) to Debug::x.
Also mark the DTRACE macro as deprecated.

Change-Id: I99d9a9544b539117b375186e3e425d73d3c5cab7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45009
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-05-10 20:00:48 +00:00
Gabe Black
d33a693e43 arch,cpu: Rename arch/registers.hh to arch/vecregs.hh.
The only thing still in arch/registers.hh were related to vector
registers. To make it obvious that nothing else should be added, this
change renames the file so that it has the much less generic name
arch/vecregs.hh.

Change-Id: I729697dc576e1978047688d9700dc07ff9b17044
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42686
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-07 19:36:08 +00:00
Gabe Black
f1cd6341ea cpu,arch: Move the zero register index into RegClassInfo.
There is a design which has been put forward which eliminates the idea
of a zero register entirely, but in the mean time, to get rid of one
more ISA specific constant, this change moves the ZeroReg constant into
the RegClassInfo class, specifically the IntRegClass instance which is
published by each ISA.

When the idea of zero registers has been eliminated entirely from
non ISA specific code, this and the existing machinery can be
eliminated.

Change-Id: I4302a53220dd5ff6b9b47ecc765bddc6698310ca
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42685
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-29 12:48:47 +00:00
Gabe Black
7036e2174f cpu: Pull all remaining non-comm types out of SimpleCPUPolicy.
Change-Id: I79c56533cf6a9d1c982cea3ca9bedc83e6afda49
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42099
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-04-29 04:23:25 +00:00
Gabe Black
86059e7a0b cpu: Extract stage classes from O3's SimpleCPUPolicy.
Use the target types directly without that layer of indirection. This
also narrows the scope of some includes.

Change-Id: I152f2ce0684781a9b61bd9d5a38620c39a4c60e8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42098
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-29 04:23:01 +00:00
Gabe Black
729ab6d4d8 cpu: Move MaxWidth and MaxThreads from O3CPUImpl to cpu/o3/limits.hh.
Change-Id: I2534661bbdbd8537129403f97c8fb767a2eb85d6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42097
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-29 03:35:40 +00:00
Gabe Black
605399893c arch,base,cpu: Move some type aliases into base/types.hh.
The arch/generic/types.hh header includes some more complicated types
which in turn bring in more dependencies, adding baggage when other code
only needs the simple RegIndex or ElemIndex types. Also the RegVal type
alias is already in base/types.hh. It doesn't really make sense to have
RegVal in one header and RegIndex in another.

Change-Id: I1360652598b5fa59e0632b1ee0e0535ace2ba563
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42966
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-04-27 02:19:11 +00:00
Gabe Black
3c3c2c3076 cpu: Simplify the RegId class a little.
Having const and non const reference accessors for the RegId index are
basically the same thing as just making the index value public but with
more complexity. Stop allowing updates through the accessor, and
simplify/fix the one location that was using that.

Also, there is no good reason to return an integer value by const
reference instead of returning it by value, since the value being passed
around (a pointer) is the same size, and just makes the value harder to
access.

Change-Id: I377ffc5878ef9bffa2ac53626a87c019a585ab1a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42684
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-22 15:12:42 +00:00
Gabe Black
6f3c197742 cpu: Eliminate the isZeroReg() helper in RegId.
The isZeroReg() helper checked if the register was both an integer
register, and if it equaled TheISA::ZeroReg. This bakes in both the
assumption that any zero registers are integer (and that integer
registers are a thing), and also internalizes the plumbing which selects
what index is the zero register.

This change eliminates the isZeroReg helper and moves the logic inside
it into where it was called. In most cases, it was actually not
necessary to check if the register was integer since that was already
implied by context. This also brings the TheISA::ZeroReg constant out,
where it can be replaced by values plumbed in more generally than a
fixed, ISA specific constant.

Change-Id: I651762b6eb01fea83ec0b0076e8be9bf24b5b0da
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42683
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-22 12:50:48 +00:00
Gabe Black
8467e183c9 cpu,sim: Set ThreadContext's ContextID right away.
The code which registers thread contexts originally returned the ID that
it had chosen, and let the CPU actually set the ID in the object itself.
That opened a window where calling contextId() on the ThreadContext
would return the wrong answer.

Instead, we can just set the ID immediately after it's decided. This
also localizes that logic and removes plumbing for the ID between that
decision and where it's actually applied.

Change-Id: I31ad84c3f9bf6f5b6f72457ca640ea929b24f6a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44615
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-04-20 06:27:07 +00:00
Gabe Black
86301ce456 cpu: Use the built in << for VecReg and VecPredReg in ExeTrace.
There's no reason to reimplement printing code when VecReg and
VecPredReg types already know how to print themselves.

Change-Id: I092c28143de286d765312122b81ce865a5184091
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42001
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-04-20 00:14:09 +00:00
Gabe Black
2d95f59ece arch,cpu: Separate printing and serialization of VecPredReg.
This is equivalent to what was done with VecReg recently.

Change-Id: I8e28c9796bf5cabd35a6bf5b89e55efcf9324d92
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41999
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-20 00:14:09 +00:00
Gabe Black
14f14f9a62 arch,cpu,sim: Move the null and nop StaticInstPtrs to their own files.
The nullStaticInstPtr was low overhead, but the nopStaticInstPtr needed
an actual StaticInst implementation it could point to, and that brought
with it some (minor) additional dependencies. Specifically, the
implementation of advancePC needs the definition of TheISA::PCState,
while all other signatures/impementations in StaticInst are already
passing around that type by reference or could be made to, reducing
dependencies further.

Change-Id: I9ac6a6e5a3106858ea1fc727648f61dc39738a59
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42968
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-17 22:39:37 +00:00
Gabe Black
3bd72b42d0 cpu: De-templatize the BaseO3DynInst.
Change-Id: If77561b811e10adf54a8b9e28f61e143ed3ead33
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42096
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-17 08:39:49 +00:00
Gabe Black
f484341215 cpu: Get rid of the unused eaSrcsReady method.
This method wasn't used by anything, and also made very unsafe
assumptions about what different source registers were used for.

Change-Id: I8f58aa70e139d3895499e04c86d8de2530e17d5a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42095
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-17 01:33:41 +00:00
Gabe Black
1daf4bf39d cpu: Merge the BaseDynInst and the BaseO3DynInst classes.
Despite the generic sounding name and sort of generic contents, the
BaseDynInst was actually tied to the O3 CPU. Having the two independent
moving pieces created complexity but provided no real benefit. This was
evidenced by the fact that no CPU other than O3 actually used that
class.

Change-Id: I4ea1d053e2e172ececdc3113b8d76d5ad7490fc7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42094
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-17 01:33:13 +00:00
handsomeliu
490b41eaac cpu: Increased the upper bound of cpu issue width
The upper bound was 8, but issue width increased to 12 since Cortex A77.
(https://en.wikichip.org/wiki/arm_holdings/microarchitectures/cortex-a77)
This CL increased the upper bound to 12.

Bug: 175759373
Test: gem5/main/config/example/se.py
Change-Id: I9d084b940628a2bcfa676d386d3d1a82ba9b03f2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44225
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-15 07:55:54 +00:00
Daniel R. Carvalho
e7e03df9a9 cpu-o3: Fix missing overrides
Fix missing overrides in SimpleTrace.

Change-Id: I82ed2a10c98ea67dde7b99db13c0ad5d9ed96f0f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44405
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-14 00:09:06 +00:00
Gabe Black
960b9246c5 scons: Convert gem5_scons.Configure to a context manager.
This has two purposes. First, SCons assumes that once you call
Configure, you won't set up the environment the Configure is based on
until after you get the environment back from it again with
conf.Finish(). We get away with this when the cache mode for config
tests is not "force", since Configure just reuses the environment we
pass in, and any changes we make are immediately communicated between
the two.

If the cache mode *is* "force" though, SCons modifies the decider so
that everything the conf environment goes to build looks like it's out
of date. It does that by cloning the original environment, and then
using that clone to do its tests. That causes a problem because we have
a long lived "conf" object and make further changes to main, and since
the two environments are now separate the one in conf doesn't see those
updates.

Second, and more subtly, we export our "main" and "env" environments so
that other SConsopts and SConscript files can use them and define things
in them. The way Configure is designed, if the config caching mode is
"force", then it will create a new environment, and then that
environment will replace what the, for instance, "main" variable points
to when "main = conf.Finish()" is executed.

Unfortunately, if we've already Export()-ed main, we've exported what
the "main" variable pointed to at that time. Our view of "main" will
track with the value that conf.Finish() returned, but since that
construction environment is mearly derived from the main we Exported and
not actually the same thing, they have diverged at that point and will
behave independently.

To solve both of these problems, this change modifies the
gem5_scons.Configure() method so that it's a context manager instead of
a regular function. As before, it will call Configure for us and create
a configuration context, which it will yield as the "with" value. When
the context exits, all the variables in the context Finish() returns
will be shoved back into the original context with Replace(). This isn't
perfect since variables which were deleted in the environment (probably
very rare in practice) will not exist and so will not overwrite the
still existent variable in the original dict.

This has several advantages. The environment never splits into two
copies which continue on independently. It makes the lifetime of a
configuration context short, which is good because behavior during that
time is tricky and unintuitive. It also makes the scope of the context
very clear, so that you won't miss the fact that you're in a special
setting and need to pay attention to what environment you're modifying.

Also, this keeps the conceptual overhead of configuration localized to
where the configuration is happening. In parts of the SConscripts which
are not doing anything with conf, etc, they don't have to modify their
behavior since no configuration context is active.

This change is based on this change from Hanhwi Jang who identified this
problem and proposed an initial solution:

https://gem5-review.googlesource.com/c/public/gem5/+/44265

Change-Id: Iae0a292d6b375c5da98619f31392ca1de6216fcd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44389
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Hanhwi Jang <jang.hanhwi@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-13 01:04:54 +00:00
Gabe Black
0dade68dae arch,cpu,gpu-compute: Further simplify VecRegContainer.
Get rid of VecRegT, and a few redundant or unused methods.

Change-Id: I6c88c40653e1939fe74b8ffb847ef50ab8064670
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41995
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-10 07:31:23 +00:00
Daniel R. Carvalho
5c8983fc18 misc: Fix remaining opening braces
These were not caught by the previous patches because
the grep used ignored:
- anonymous structures
  (e.g., "struct {")
- opening braces without leading spaces
  (e.g., "struct Name{"),
- weird chars in auto-generation files
  (e.g., "struct $name {").
- extra characters after the opening brace.
  (e.g., "struct Name { // Comment")
- typedefs (note that this is not caught by the verifier)
  (e.g., "typedef struct Name {")

Most of this has been fixed be grepping structures
with the following regex:
  grep -nrE --exclude-dir=systemc \
    "^ *(typedef)* *(struct|class|enum|union) [^{]*{$" src/

The following makes sure that "struct{" is captured:
  grep -nrE --exclude-dir=systemc \
    "^ *(struct|class|enum|union){" src/

To find cases that contain a comment after the
opening brace:
  grep -nrE --exclude-dir=systemc \
    "^ *(struct|class|enum|union)[^{]*{\s*//" src/

Change-Id: I9f822bed628d13b1a09ccd6059373aff63a8d7bd
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43505
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-07 01:29:31 +00:00
Gabe Black
1791b8732c scons: Pull domain specific build setup out of SConstruct.
Use SConsopts files local to individual domains to pull
non-foundational build code out of SConstruct. This greatly simplifies
SConstruct, and also makes it easier to find build configuration having
to do with particular pieces of gem5.

This change also converts some python level variables, all_protocols,
protocol_dirs, and slicc_includes, into the environment where the timing
of their initialization is more flexible.

Change-Id: Ie61ceb75ae9e5557cc400603c972a9582e99c1ea
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40872
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
2021-04-03 01:18:17 +00:00
Alexander Klimov
34c82f7266 cpu: Improve MemTest
To make it easy to select memory sizes, make the base addresses
explicit parameters.

Change-Id: I337a10b539bf734c6f99f99eaa2daa252be5a9d2
Signed-off-by: Alexander Klimov <Alexander.Klimov@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43727
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-31 15:33:08 +00:00
Gabe Black
5f95d7a89a dev,cpu,configs: Get rid of the IntrControl device.
This vestigial device provides a thin layer of indirection between
devices and the CPUs in a system. It's basically a collection of helper
functions, but since it's a SimObject it needs to be instantiated in
python and added to configurations.

Change-Id: I029d2314ae0bb890678e1e68dafcdab4bfe49beb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43347
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-29 20:54:16 +00:00
Daniel R. Carvalho
b2c0b191e1 misc: Fix coding style for union's opening braces
The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, 2 and 3 levels of indentation, using:

    grep -nrE --exclude-dir=systemc \
        "^ *union [A-Za-z].* {$" src/

Then the following commands were run to replace:

    <indent level>union X ... {

by:

    <indent level>union X ...
    <indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc \
        "^union [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^union ([A-Za-z].*) \{$/union \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    union [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    union ([A-Za-z].*) \{$/    union \1\n    \{/g'

and so on.

Change-Id: I066854eb27a8acd2cc2dfa41596bb1b1f66c71b1
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43328
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
2021-03-23 16:26:04 +00:00
Daniel R. Carvalho
7f1de4e686 misc: Fix coding style for enum's opening braces
The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, and 2 levels of indentation (and 2 of 2 spaces,
1 of 3 spaces and 2 of 12 spaces), using:

    grep -nrE --exclude-dir=systemc \
        "^ *enum [A-Za-z].* {$" src/

Then the following commands were run to replace:

    <indent level>enum X ... {

by:

    <indent level>enum X ...
    <indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc \
        "^enum [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^enum ([A-Za-z].*) \{$/enum \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    enum [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    enum ([A-Za-z].*) \{$/    enum \1\n    \{/g'

and so on.

Change-Id: Ib186cf379049098ceaec20dfe4d1edcedd5f940d
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43326
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-23 16:26:04 +00:00
Gabe Black
08913caec2 arch,cpu,kern,sim: Eliminate the utility.hh switching header.
This header is no longer used. Remove the places where it's included,
and stop generating it. Also eliminate the now empty SPARC and Power
versions of the header.

Change-Id: I6ee66d39bc0218d1d9b9b7db3b350134ef03251d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39337
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-03-22 21:01:58 +00:00
Gabe Black
5ffd619d38 arch,cpu: Move TheISA::copyRegs to TheISA::ISA::copyRegsFrom.
This eliminates the last externally used function in arch/utility.hh.

Change-Id: I7f402b0303e2758762e19d69f3bed37262cc9289
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39336
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-03-22 21:01:33 +00:00
Gabe Black
2cb09e4042 arch,cpu: Collapse away TheISA::advancePC.
In most ISAs except MIPS and Power, this was implemented as
inst->advancePC(). It works just fine to call this function all the
time, but the idea had originally been that for ISAs which could simply
advance the PC using the PC itself, they could save the virtual function
call. Since the only ISAs which could skip the call were MIPS and Power,
and neither is at the point where that level of performance tuning
matters, this function can be collapsed with little downside.

If this turns out to be a performance bottleneck in the future, the way
the PC is managed could be revisited to see if we can factor out this
trip to the instruction object in the first place.

Change-Id: I533d1ad316e5c936466c529b7f1238a9ab87bd1c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39335
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Alex Dutu <alexandru.dutu@amd.com>
2021-03-22 21:01:07 +00:00
Bobby R. Bruce
af81ec9041 Merge "misc: Merge branch 'release-staging-v21-0' into develop" into develop 2021-03-19 21:13:58 +00:00
Daniel R. Carvalho
2922f763e1 misc: Fix coding style for struct's opening braces
The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, 2 and 3 levels of indentation (and a single
occurrence of 2 and 3 spaces), using:

    grep -nrE --exclude-dir=systemc \
        "^ *struct [A-Za-z].* {$" src/

Then the following commands were run to replace:

<indent level>struct X ... {

by:

<indent level>struct X ...
<indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc
        "^struct [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^struct ([A-Za-z].*) \{$/struct \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    struct [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    struct ([A-Za-z].*) \{$/    struct \1\n    \{/g'

and so on.

Change-Id: I362ef58c86912dabdd272c7debb8d25d587cd455
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39017
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-19 20:57:24 +00:00
Daniel R. Carvalho
469f0671d1 misc: Fix coding style for class-opening braces
The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, and 2 levels of indentation, using:

    grep -nrE --exclude-dir=systemc \
        "^ *class [A-Za-z].* {$" src/

Then the following commands were run to replace:

<indent level>class X ... {

by:

<indent level>class X ...
<indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc
        "^class [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^class ([A-Za-z].*) \{$/class \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    class [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    class ([A-Za-z].*) \{$/    class \1\n    \{/g'

and so on.

Change-Id: I17615ce16a333d69867b27c7bae0f4fdafd8b2eb
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39015
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-19 20:57:24 +00:00
Gabe Black
1c35c00c4f arch,cpu: Get rid of the RenameMode template class.
There is no way to make this sort of template work with more than one
ISA at a time, and it's also more complex than it needs to be,
particularly since the methods within it are never used in performance
critical code. Using virtual functions is also simpler and uses less
code.

Change-Id: I0baa1a651fa656420f6f90776572f8700a6d7cab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40106
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-19 00:56:21 +00:00
Bobby R. Bruce
68064d8043 misc: Merge branch 'release-staging-v21-0' into develop
Change-Id: I0ad043ded56fb848e045057a1e7a56ea39797906
2021-03-18 11:13:14 -07:00
Gabe Black
d79d8498a4 cpu: Use a unique_ptr to manage cached disassembly.
This is a fairly minor improvement, but avoids having to manually keep
track of that string pointer.

Change-Id: Ic3d4ddd9445920a110b36ab0cd64ff2289cf0139
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42967
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-03-16 11:04:39 +00:00
Gabe Black
10b0aceeff cpu: Narrow the dependencies of the StaticInst class.
Include only the minimal number of headers to make StaticInst subclasses
easier to test with unit tests.

Change-Id: Ie2e1c01b77d1776b366d29982e481d62b6a2b8cf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42965
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-03-16 03:51:15 +00:00
Gabe Black
e1f2608141 cpu: Fix transitive includes in the O3 rename map and debug faults.
Change-Id: I22f80c24c3128e91fd039b8e3b689d7065440ad0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42964
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-03-16 03:51:07 +00:00
Gabe Black
122ff006c3 cpu: Fix some minor style issues in cpu/static_inst.hh.
Also use default values for some members rather than setting them in the
constructor explicitly.

Change-Id: I0f75cca54f952542d1f37576bd752a8d6acb5561
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42963
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-16 03:50:34 +00:00
Daniel R. Carvalho
eb9e11ad96 base: Move Named class to its own file
Named can be useful in instances where trace is not required.
Because of that it has been moved to its own file.

Named is intended for public inheritance; thus it should have
a virtual destructor.

Added a unit test for the Named class.

Change-Id: I314e850b4fafd7804d919fd3fe6dec44822e1f48
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38743
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-16 03:28:52 +00:00
Gabe Black
b22b7f2d66 arch,cpu: Move buildRetPC into the StaticInst class.
This was an inline function defined for each ISA, but really it makes
more sense for it to be defined by the instruction classes. The actual
return address for any given instruction can best be calculated when you
know what that instruction actually does, and also the instructions will
know about ISA level PC management.

Change-Id: I2c5203aefa90f2f26ecd94e82b925c6b552e33d3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39324
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-13 05:53:27 +00:00
Yu-hsin Wang
bf91a33e2d cpu-kvm: refactor x86 fixup before kvm_run
Since kvmRun still does lots of thing before really going to KVM, to
make the fixup more precise, I change ioctlRun to a virtual function and
make the derived class overrides it if needed.

Change-Id: Ifd75decf0a5445a5266398caebd8aac1a5e80c50
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42301
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2021-03-12 02:46:11 +00:00