derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

cpu: Improve MemTest

Browse Source 
To make it easy to select memory sizes, make the base addresses
explicit parameters.

Change-Id: I337a10b539bf734c6f99f99eaa2daa252be5a9d2
Signed-off-by: Alexander Klimov <Alexander.Klimov@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43727
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Alexander Klimov
2021-03-25 11:56:10 +00:00
committed by Giacomo Travaglini
parent e0b4c2ee04
commit 34c82f7266
3 changed files with 16 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/cpu/testers/memtest/MemTest.py
View File

@@ -1,4 +1,4 @@
# Copyright (c) 2015 ARM Limited
# Copyright (c) 2015, 2021 Arm Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -49,6 +49,10 @@ class MemTest(ClockedObject):
# touched, and an optional stop condition
interval = Param.Cycles(1, "Interval between request packets")
size = Param.Unsigned(65536, "Size of memory region to use (bytes)")
base_addr_1 = Param.Addr(0x100000, "Start of the first testing region")
base_addr_2 = Param.Addr(0x400000, "Start of the second testing region")
uncacheable_base_addr = Param.Addr(
0x800000, "Start of the uncacheable testing region")
max_loads = Param.Counter(0, "Number of loads to execute before exiting")
# Control the mix of packets and if functional accesses are part of

11
src/cpu/testers/memtest/memtest.cc
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2015, 2019 ARM Limited
* Copyright (c) 2015, 2019, 2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -48,7 +48,7 @@
#include "sim/stats.hh"
#include "sim/system.hh"
unsigned int TESTER_ALLOCATOR = 0;
static unsigned int TESTER_ALLOCATOR = 0;
bool
MemTest::CpuPort::recvTimingResp(PacketPtr pkt)
@@ -92,6 +92,9 @@ MemTest::MemTest(const Params &p)
requestorId(p.system->getRequestorId(this)),
blockSize(p.system->cacheLineSize()),
blockAddrMask(blockSize - 1),
baseAddr1(p.base_addr_1),
baseAddr2(p.base_addr_2),
uncacheAddr(p.uncacheable_base_addr),
progressInterval(p.progress_interval),
progressCheck(p.progress_check),
nextProgressMessage(p.progress_interval),
@@ -103,10 +106,6 @@ MemTest::MemTest(const Params &p)
fatal_if(id >= blockSize, "Too many testers, only %d allowed\n",
blockSize - 1);
baseAddr1 = 0x100000;
baseAddr2 = 0x400000;
uncacheAddr = 0x800000;
// set up counters
numReads = 0;
numWrites = 0;

12
src/cpu/testers/memtest/memtest.hh
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2015 ARM Limited
* Copyright (c) 2015, 2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -41,8 +41,8 @@
#ifndef __CPU_MEMTEST_MEMTEST_HH__
#define __CPU_MEMTEST_MEMTEST_HH__
#include <set>
#include <unordered_map>
#include <unordered_set>
#include "base/statistics.hh"
#include "mem/port.hh"
@@ -130,7 +130,7 @@ class MemTest : public ClockedObject
unsigned int id;
std::set<Addr> outstandingAddrs;
std::unordered_set<Addr> outstandingAddrs;
// store the expected value for the addresses we have touched
std::unordered_map<Addr, uint8_t> referenceData;
@@ -150,9 +150,9 @@ class MemTest : public ClockedObject
return (addr & ~blockAddrMask);
}
Addr baseAddr1;
Addr baseAddr2;
Addr uncacheAddr;
const Addr baseAddr1;
const Addr baseAddr2;
const Addr uncacheAddr;
const unsigned progressInterval; // frequency of progress reports
const Cycles progressCheck;