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dev,cpu,configs: Get rid of the IntrControl device.

Browse Source 
This vestigial device provides a thin layer of indirection between
devices and the CPUs in a system. It's basically a collection of helper
functions, but since it's a SimObject it needs to be instantiated in
python and added to configurations.

Change-Id: I029d2314ae0bb890678e1e68dafcdab4bfe49beb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43347
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-03-22 04:06:48 -07:00
parent fc9b1b5089
commit 5f95d7a89a
42 changed files with 88 additions and 370 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
configs/common/FSConfig.py
View File

@@ -122,7 +122,6 @@ def makeSparcSystem(mem_mode, mdesc=None, cmdline=None):
AddrRange(Addr('2GB'), size ='256MB')]
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
self.intrctrl = IntrControl()
self.disk0 = CowMmDisk()
self.disk0.childImage(mdesc.disks()[0])
self.disk0.pio = self.iobus.master
@@ -332,7 +331,6 @@ def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
dev, self.iobus,
dma_ports=self._dma_ports if ruby else None)
self.intrctrl = IntrControl()
self.terminal = Terminal()
self.vncserver = VncServer()
@@ -379,7 +377,6 @@ def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None):
self.malta.ethernet.dma = self.iobus.slave
self.simple_disk = SimpleDisk(disk=RawDiskImage(
image_file = mdesc.disks()[0], read_only = True))
self.intrctrl = IntrControl()
self.mem_mode = mem_mode
self.terminal = Terminal()
self.console = binary('mips/console')
@@ -488,8 +485,6 @@ def makeX86System(mem_mode, numCPUs=1, mdesc=None, workload=None, Ruby=False):
else:
connectX86ClassicSystem(self, numCPUs)
self.intrctrl = IntrControl()
# Disks
disks = makeCowDisks(mdesc.disks())
self.pc.south_bridge.ide.disks = disks

1
configs/example/arm/devices.py
View File

@@ -296,7 +296,6 @@ class BaseSimpleSystem(ArmSystem):
if hasattr(self.realview.gic, 'cpu_addr'):
self.gic_cpu_addr = self.realview.gic.cpu_addr
self.intrctrl = IntrControl()
self.terminal = Terminal()
self.vncserver = VncServer()

2
configs/example/riscv/fs_linux.py
View File

@@ -137,8 +137,6 @@ system.membus = MemBus()
system.system_port = system.membus.cpu_side_ports
system.intrctrl = IntrControl()
# HiFive platform
system.platform = HiFive()

33
src/cpu/IntrControl.py
View File

@@ -1,33 +0,0 @@
# Copyright (c) 2005-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
class IntrControl(SimObject):
type = 'IntrControl'
cxx_header = "cpu/intr_control.hh"
sys = Param.System(Parent.any, "the system we are part of")

5
src/cpu/SConscript
View File

@@ -64,7 +64,6 @@ DebugFlag('ExecAsid', 'Format: Include ASID in trace')
DebugFlag('ExecFlags', 'Format: Include instruction flags in trace')
DebugFlag('Fetch')
DebugFlag('HtmCpu', 'Hardware Transactional Memory (CPU side)')
DebugFlag('IntrControl')
DebugFlag('O3PipeView')
DebugFlag('PCEvent')
DebugFlag('Quiesce')
@@ -83,8 +82,6 @@ CompoundFlag('ExecNoTicks', [ 'Exec', 'FmtTicksOff' ])
Source('pc_event.cc')
if env['TARGET_ISA'] == 'null':
SimObject('IntrControl.py')
Source('intr_control_noisa.cc')
Return()
# Only build the protocol buffer instructions tracer if we have protobuf support
@@ -97,7 +94,6 @@ SimObject('CheckerCPU.py')
SimObject('BaseCPU.py')
SimObject('CPUTracers.py')
SimObject('FuncUnit.py')
SimObject('IntrControl.py')
SimObject('TimingExpr.py')
Source('activity.cc')
@@ -105,7 +101,6 @@ Source('base.cc')
Source('exetrace.cc')
Source('func_unit.cc')
Source('inteltrace.cc')
Source('intr_control.cc')
Source('nativetrace.cc')
Source('profile.cc')
Source('reg_class.cc')

74
src/cpu/intr_control.cc
View File

@@ -1,74 +0,0 @@
/*
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "cpu/intr_control.hh"
#include <string>
#include <vector>
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/IntrControl.hh"
#include "sim/sim_object.hh"
IntrControl::IntrControl(const Params &p)
: SimObject(p), sys(p.sys)
{}
void
IntrControl::post(int cpu_id, int int_num, int index)
{
DPRINTF(IntrControl, "post %d:%d (cpu %d)\n", int_num, index, cpu_id);
auto *tc = sys->threads[cpu_id];
tc->getCpuPtr()->postInterrupt(tc->threadId(), int_num, index);
}
void
IntrControl::clear(int cpu_id, int int_num, int index)
{
DPRINTF(IntrControl, "clear %d:%d (cpu %d)\n", int_num, index, cpu_id);
auto *tc = sys->threads[cpu_id];
tc->getCpuPtr()->clearInterrupt(tc->threadId(), int_num, index);
}
void
IntrControl::clearAll(int cpu_id)
{
DPRINTF(IntrControl, "Clear all pending interrupts for CPU %d\n", cpu_id);
auto *tc = sys->threads[cpu_id];
tc->getCpuPtr()->clearInterrupts(tc->threadId());
}
bool
IntrControl::havePosted(int cpu_id) const
{
DPRINTF(IntrControl, "Check pending interrupts for CPU %d\n", cpu_id);
auto *tc = sys->threads[cpu_id];
return tc->getCpuPtr()->checkInterrupts(tc->threadId());
}

71
src/cpu/intr_control.hh
View File

@@ -1,71 +0,0 @@
/*
* Copyright (c) 2001-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __INTR_CONTROL_HH__
#define __INTR_CONTROL_HH__
#include <vector>
#include "base/logging.hh"
#include "params/IntrControl.hh"
#include "sim/sim_object.hh"
#include "sim/system.hh"
class IntrControl : public SimObject
{
public:
System *sys;
typedef IntrControlParams Params;
IntrControl(const Params &p);
void clear(int cpu_id, int int_num, int index);
void post(int cpu_id, int int_num, int index);
void clearAll(int cpu_id);
bool havePosted(int cpu_id) const;
void
clear(int int_num, int index = 0)
{
clear(0, int_num, index);
}
void
post(int int_num, int index = 0)
{
post(0, int_num, index);
}
};
#endif // __INTR_CONTROL_HH__

43
src/cpu/intr_control_noisa.cc
View File

@@ -1,43 +0,0 @@
/*
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "cpu/intr_control.hh"
IntrControl::IntrControl(const Params &p)
: SimObject(p), sys(p.sys)
{}
void
IntrControl::post(int cpu_id, int int_num, int index)
{
}
void
IntrControl::clear(int cpu_id, int int_num, int index)
{
}

2
src/dev/Platform.py
View File

@@ -32,7 +32,7 @@ class Platform(SimObject):
type = 'Platform'
abstract = True
cxx_header = "dev/platform.hh"
intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
system = Param.System(Parent.any, "system")
# for platforms using device trees to set properties of CPU nodes
def annotateCpuDeviceNode(self, cpu, state):

1
src/dev/arm/RealView.py
View File

@@ -649,7 +649,6 @@ class GenericMHU(MHU):
class RealView(Platform):
type = 'RealView'
cxx_header = "dev/arm/realview.hh"
system = Param.System(Parent.any, "system")
_mem_regions = [ AddrRange(0, size='256MiB') ]
_num_pci_dev = 0

12
src/dev/arm/gic_v2.cc
View File

@@ -41,6 +41,7 @@
#include "dev/arm/gic_v2.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
#include "debug/Checkpoint.hh"
#include "debug/GIC.hh"
#include "debug/IPI.hh"
@@ -917,10 +918,11 @@ GicV2::clearPPInt(uint32_t num, uint32_t cpu)
void
GicV2::clearInt(ContextID ctx, uint32_t int_num)
{
auto tc = sys->threads[ctx];
if (isFiq(ctx, int_num)) {
platform->intrctrl->clear(ctx, ArmISA::INT_FIQ, 0);
tc->getCpuPtr()->clearInterrupt(tc->threadId(), ArmISA::INT_FIQ, 0);
} else {
platform->intrctrl->clear(ctx, ArmISA::INT_IRQ, 0);
tc->getCpuPtr()->clearInterrupt(tc->threadId(), ArmISA::INT_IRQ, 0);
}
}
@@ -936,7 +938,8 @@ GicV2::postInt(uint32_t cpu, Tick when)
void
GicV2::postDelayedInt(uint32_t cpu)
{
platform->intrctrl->post(cpu, ArmISA::INT_IRQ, 0);
auto tc = sys->threads[cpu];
tc->getCpuPtr()->postInterrupt(tc->threadId(), ArmISA::INT_IRQ, 0);
--pendingDelayedInterrupts;
assert(pendingDelayedInterrupts >= 0);
if (pendingDelayedInterrupts == 0)
@@ -961,7 +964,8 @@ GicV2::supportsVersion(GicVersion version)
void
GicV2::postDelayedFiq(uint32_t cpu)
{
platform->intrctrl->post(cpu, ArmISA::INT_FIQ, 0);
auto tc = sys->threads[cpu];
tc->getCpuPtr()->postInterrupt(tc->threadId(), ArmISA::INT_FIQ, 0);
--pendingDelayedInterrupts;
assert(pendingDelayedInterrupts >= 0);
if (pendingDelayedInterrupts == 0)

1
src/dev/arm/gic_v2.hh
View File

@@ -51,7 +51,6 @@
#include "arch/arm/interrupts.hh"
#include "base/addr_range.hh"
#include "base/bitunion.hh"
#include "cpu/intr_control.hh"
#include "dev/arm/base_gic.hh"
#include "dev/io_device.hh"
#include "dev/platform.hh"

1
src/dev/arm/gic_v2m.hh
View File

@@ -45,7 +45,6 @@
#define __DEV_ARM_GIC_V2M_H__
#include "base/bitunion.hh"
#include "cpu/intr_control.hh"
#include "dev/arm/base_gic.hh"
#include "dev/io_device.hh"
#include "dev/platform.hh"

16
src/dev/arm/gic_v3.cc
View File

@@ -40,7 +40,7 @@
#include "dev/arm/gic_v3.hh"
#include "cpu/intr_control.hh"
#include "cpu/base.hh"
#include "debug/GIC.hh"
#include "debug/Interrupt.hh"
#include "dev/arm/gic_v3_cpu_interface.hh"
@@ -204,8 +204,9 @@ Gicv3::clearPPInt(uint32_t int_id, uint32_t cpu)
void
Gicv3::postInt(uint32_t cpu, ArmISA::InterruptTypes int_type)
{
platform->intrctrl->post(cpu, int_type, 0);
ArmSystem::callClearStandByWfi(sys->threads[cpu]);
auto tc = sys->threads[cpu];
tc->getCpuPtr()->postInterrupt(tc->threadId(), int_type, 0);
ArmSystem::callClearStandByWfi(tc);
}
bool
@@ -218,19 +219,22 @@ Gicv3::supportsVersion(GicVersion version)
void
Gicv3::deassertInt(uint32_t cpu, ArmISA::InterruptTypes int_type)
{
platform->intrctrl->clear(cpu, int_type, 0);
auto tc = sys->threads[cpu];
tc->getCpuPtr()->clearInterrupt(tc->threadId(), int_type, 0);
}
void
Gicv3::deassertAll(uint32_t cpu)
{
platform->intrctrl->clearAll(cpu);
auto tc = sys->threads[cpu];
tc->getCpuPtr()->clearInterrupts(tc->threadId());
}
bool
Gicv3::haveAsserted(uint32_t cpu) const
{
return platform->intrctrl->havePosted(cpu);
auto tc = sys->threads[cpu];
return tc->getCpuPtr()->checkInterrupts(tc->threadId());
}
Gicv3Redistributor *

4
src/dev/arm/realview.cc
View File

@@ -48,13 +48,11 @@
#include <string>
#include <vector>
#include "cpu/intr_control.hh"
#include "dev/arm/base_gic.hh"
#include "sim/system.hh"
RealView::RealView(const Params &p)
: Platform(p), system(p.system), gic(nullptr)
: Platform(p), gic(nullptr)
{}
void

10
src/dev/arm/realview.hh
View File

@@ -52,25 +52,15 @@
class BaseGic;
class IdeController;
class System;
class RealView : public Platform
{
public:
/** Pointer to the system */
System *system;
BaseGic *gic;
public:
using Params = RealViewParams;
/**
* Constructor for the Tsunami Class.
* @param name name of the object
* @param s system the object belongs to
* @param intctrl pointer to the interrupt controller
*/
RealView(const Params &p);
/** Give platform a pointer to interrupt controller */

7
src/dev/arm/vgic.cc
View File

@@ -39,6 +39,7 @@
#include "arch/arm/interrupts.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
#include "debug/Checkpoint.hh"
#include "debug/VGIC.hh"
#include "dev/arm/base_gic.hh"
@@ -371,13 +372,15 @@ void
VGic::unPostVInt(uint32_t cpu)
{
DPRINTF(VGIC, "Unposting VIRQ to %d\n", cpu);
platform->intrctrl->clear(cpu, ArmISA::INT_VIRT_IRQ, 0);
auto tc = platform->system->threads[cpu];
tc->getCpuPtr()->clearInterrupt(tc->threadId(), ArmISA::INT_VIRT_IRQ, 0);
}
void
VGic::processPostVIntEvent(uint32_t cpu)
{
platform->intrctrl->post(cpu, ArmISA::INT_VIRT_IRQ, 0);
auto tc = platform->system->threads[cpu];
tc->getCpuPtr()->postInterrupt(tc->threadId(), ArmISA::INT_VIRT_IRQ, 0);
}

1
src/dev/arm/vgic.hh
View File

@@ -55,7 +55,6 @@
#include "base/addr_range.hh"
#include "base/bitunion.hh"
#include "cpu/intr_control.hh"
#include "dev/io_device.hh"
#include "dev/platform.hh"
#include "params/VGic.hh"

1
src/dev/mips/Malta.py
View File

@@ -50,7 +50,6 @@ class MaltaIO(BasicPioDevice):
class Malta(Platform):
type = 'Malta'
cxx_header = "dev/mips/malta.hh"
system = Param.System(Parent.any, "system")
cchip = MaltaCChip(pio_addr=0x801a0000000)
io = MaltaIO(pio_addr=0x801fc000000)
uart = Uart8250(pio_addr=0xBFD003F8)

3
src/dev/mips/malta.cc
View File

@@ -36,7 +36,6 @@
#include <string>
#include <vector>
#include "cpu/intr_control.hh"
#include "debug/Malta.hh"
#include "dev/mips/malta_cchip.hh"
#include "dev/mips/malta_io.hh"
@@ -44,7 +43,7 @@
#include "sim/system.hh"
Malta::Malta(const Params &p)
: Platform(p), system(p.system)
: Platform(p)
{
for (int i = 0; i < Malta::Max_CPUs; i++)
intr_sum_type[i] = 0;

9
src/dev/mips/malta.hh
View File

@@ -56,9 +56,6 @@ class Malta : public Platform
/** Max number of CPUs in a Malta */
static const int Max_CPUs = 64;
/** Pointer to the system */
System *system;
/** Pointer to the MaltaIO device which has the RTC */
MaltaIO *io;
@@ -72,12 +69,6 @@ class Malta : public Platform
int ipi_pending[Malta::Max_CPUs];
public:
/**
* Constructor for the Malta Class.
* @param name name of the object
* @param s system the object belongs to
* @param intctrl pointer to the interrupt controller
*/
typedef MaltaParams Params;
Malta(const Params &p);

8
src/dev/mips/malta_cchip.cc
View File

@@ -37,7 +37,7 @@
#include <vector>
#include "base/trace.hh"
#include "cpu/intr_control.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/Malta.hh"
#include "dev/mips/malta.hh"
@@ -106,7 +106,8 @@ MaltaCChip::postIntr(uint32_t interrupt)
for (int i=0; i < size; i++) {
//Note: Malta does not use index, but this was added to use the
//pre-existing implementation
malta->intrctrl->post(i, interrupt, 0);
auto tc = sys->threads[i];
tc->getCpuPtr()->postInterrupt(tc->threadId(), interrupt, 0);
DPRINTF(Malta, "posting interrupt to cpu %d, interrupt %d\n",
i, interrupt);
}
@@ -121,7 +122,8 @@ MaltaCChip::clearIntr(uint32_t interrupt)
for (int i=0; i < size; i++) {
//Note: Malta does not use index, but this was added to use the
//pre-existing implementation
malta->intrctrl->clear(i, interrupt, 0);
auto tc = sys->threads[i];
tc->getCpuPtr()->clearInterrupt(tc->threadId(), interrupt, 0);
DPRINTF(Malta, "clearing interrupt to cpu %d, interrupt %d\n",
i, interrupt);
}

10
src/dev/platform.cc
View File

@@ -29,16 +29,8 @@
#include "dev/platform.hh"
#include "base/logging.hh"
#include "sim/sim_exit.hh"
Platform::Platform(const Params &p)
: SimObject(p), intrctrl(p.intrctrl)
{
}
Platform::~Platform()
{
}
Platform::Platform(const Params &p) : SimObject(p), system(p.system) {}
void
Platform::postPciInt(int line)

8
src/dev/platform.hh
View File

@@ -40,22 +40,18 @@
#include "params/Platform.hh"
#include "sim/sim_object.hh"
class IntrControl;
class Terminal;
class Uart;
class System;
class Platform : public SimObject
{
public:
/** Pointer to the interrupt controller */
IntrControl *intrctrl;
System *system;
public:
typedef PlatformParams Params;
Platform(const Params &p);
virtual ~Platform();
virtual ~Platform() = default;
/**
* Cause the cpu to post a serial interrupt to the CPU.

1
src/dev/riscv/Clint.py
View File

@@ -49,7 +49,6 @@ class Clint(BasicPioDevice):
"""
type = 'Clint'
cxx_header = 'dev/riscv/clint.hh'
intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
int_pin = IntSinkPin('Pin to receive RTC signal')
pio_size = Param.Addr(0xC000, "PIO Size")

1
src/dev/riscv/HiFive.py
View File

@@ -97,7 +97,6 @@ class HiFive(Platform):
"""
type = 'HiFive'
cxx_header = "dev/riscv/hifive.hh"
system = Param.System(Parent.any, "system")
# CLINT
clint = Param.Clint(Clint(pio_addr=0x2000000), "CLINT")

1
src/dev/riscv/Plic.py
View File

@@ -48,7 +48,6 @@ class Plic(BasicPioDevice):
"""
type = 'Plic'
cxx_header = 'dev/riscv/plic.hh'
intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
pio_size = Param.Addr(0x4000000, "PIO Size")
n_src = Param.Int("Number of interrupt sources")

34
src/dev/riscv/clint.cc
View File

@@ -37,6 +37,7 @@
#include "dev/riscv/clint.hh"
#include "cpu/base.hh"
#include "debug/Clint.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
@@ -48,7 +49,6 @@ using namespace RiscvISA;
Clint::Clint(const Params &params) :
BasicPioDevice(params, params.pio_size),
system(params.system),
intrctrl(params.intrctrl),
signal(params.name + ".signal", 0, this),
registers(params.name + ".registers", params.pio_addr, this)
{
@@ -63,22 +63,25 @@ Clint::raiseInterruptPin(int id)
for (int context_id = 0; context_id < nThread; context_id++) {
auto tc = system->threads[context_id];
// Update misc reg file
ISA* isa = dynamic_cast<ISA*>(
system->threads[context_id]->getIsaPtr());
ISA* isa = dynamic_cast<ISA*>(tc->getIsaPtr());
isa->setMiscRegNoEffect(MISCREG_TIME, mtime);
// Post timer interrupt
uint64_t mtimecmp = registers.mtimecmp[context_id].get();
if (mtime >= mtimecmp) {
if (mtime == mtimecmp) {
DPRINTF(Clint,
"MTIP posted - thread: %d, mtime: %d, mtimecmp: %d\n",
context_id, mtime, mtimecmp);
}
intrctrl->post(context_id, ExceptionCode::INT_TIMER_MACHINE, 0);
if (mtime == mtimecmp) {
DPRINTF(Clint,
"MTIP posted - thread: %d, mtime: %d, mtimecmp: %d\n",
context_id, mtime, mtimecmp);
}
tc->getCpuPtr()->postInterrupt(tc->threadId(),
ExceptionCode::INT_TIMER_MACHINE, 0);
} else {
intrctrl->clear(context_id, ExceptionCode::INT_TIMER_MACHINE, 0);
tc->getCpuPtr()->clearInterrupt(tc->threadId(),
ExceptionCode::INT_TIMER_MACHINE, 0);
}
}
}
@@ -137,15 +140,14 @@ Clint::writeMSIP(Register32& reg, const uint32_t& data, const int thread_id)
{
reg.update(data);
assert(data <= 1);
auto tc = system->threads[thread_id];
if (data > 0) {
DPRINTF(Clint,
"MSIP posted - thread: %d\n", thread_id);
intrctrl->post(thread_id,
DPRINTF(Clint, "MSIP posted - thread: %d\n", thread_id);
tc->getCpuPtr()->postInterrupt(tc->threadId(),
ExceptionCode::INT_SOFTWARE_MACHINE, 0);
} else {
DPRINTF(Clint,
"MSIP cleared - thread: %d\n", thread_id);
intrctrl->clear(thread_id,
DPRINTF(Clint, "MSIP cleared - thread: %d\n", thread_id);
tc->getCpuPtr()->clearInterrupt(tc->threadId(),
ExceptionCode::INT_SOFTWARE_MACHINE, 0);
}
};

2
src/dev/riscv/clint.hh
View File

@@ -40,7 +40,6 @@
#include "arch/riscv/interrupts.hh"
#include "arch/riscv/registers.hh"
#include "cpu/intr_control.hh"
#include "dev/intpin.hh"
#include "dev/io_device.hh"
#include "dev/mc146818.hh"
@@ -71,7 +70,6 @@ class Clint : public BasicPioDevice
// Params
protected:
System *system;
IntrControl *intrctrl;
int nThread;
IntSinkPin<Clint> signal;

2
src/dev/riscv/hifive.cc
View File

@@ -45,7 +45,7 @@
using namespace RiscvISA;
HiFive::HiFive(const Params &params) :
Platform(params), system(params.system),
Platform(params),
clint(params.clint), plic(params.plic),
uartIntID(params.uart_int_id)
{

1
src/dev/riscv/hifive.hh
View File

@@ -48,7 +48,6 @@ using namespace RiscvISA;
class HiFive : public Platform
{
public:
System *system;
Clint *clint;
Plic *plic;
int uartIntID;

23
src/dev/riscv/plic.cc
View File

@@ -41,6 +41,7 @@
#include <algorithm>
#include "arch/riscv/registers.hh"
#include "cpu/base.hh"
#include "debug/Plic.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
@@ -52,7 +53,6 @@ using namespace RiscvISA;
Plic::Plic(const Params &params) :
BasicPioDevice(params, params.pio_size),
system(params.system),
intrctrl(params.intrctrl),
nSrc(params.n_src),
registers(params.name, pioAddr, this),
update([this]{updateOutput();}, name() + ".update")
@@ -444,25 +444,22 @@ Plic::updateInt()
int int_id = (i & 1) ?
ExceptionCode::INT_EXT_SUPER : ExceptionCode::INT_EXT_MACHINE;
auto tc = system->threads[thread_id];
uint32_t max_id = output.maxID[i];
uint32_t priority = output.maxPriority[i];
uint32_t threshold = registers.threshold[i].get();
if (priority > threshold && max_id > 0 && lastID[i] == 0) {
DPRINTF(Plic,
"Int posted - thread: %d, int id: %d, ",
thread_id, int_id);
DPRINTFR(Plic,
"pri: %d, thres: %d\n", priority, threshold);
intrctrl->post(thread_id, int_id, 0);
DPRINTF(Plic, "Int posted - thread: %d, int id: %d, ",
thread_id, int_id);
DPRINTFR(Plic, "pri: %d, thres: %d\n", priority, threshold);
tc->getCpuPtr()->postInterrupt(tc->threadId(), int_id, 0);
} else {
if (priority > 0) {
DPRINTF(Plic,
"Int filtered - thread: %d, int id: %d, ",
thread_id, int_id);
DPRINTFR(Plic,
"pri: %d, thres: %d\n", priority, threshold);
DPRINTF(Plic, "Int filtered - thread: %d, int id: %d, ",
thread_id, int_id);
DPRINTFR(Plic, "pri: %d, thres: %d\n", priority, threshold);
}
intrctrl->clear(thread_id, int_id, 0);
tc->getCpuPtr()->clearInterrupt(tc->threadId(), int_id, 0);
}
}
}

2
src/dev/riscv/plic.hh
View File

@@ -42,7 +42,6 @@
#include <map>
#include "arch/riscv/interrupts.hh"
#include "cpu/intr_control.hh"
#include "dev/io_device.hh"
#include "dev/reg_bank.hh"
#include "mem/packet.hh"
@@ -97,7 +96,6 @@ class Plic : public BasicPioDevice
// Params
protected:
System *system;
IntrControl *intrctrl;
// Number of interrupt sources
int nSrc;

1
src/dev/sparc/T1000.py
View File

@@ -55,7 +55,6 @@ class Iob(PioDevice):
class T1000(Platform):
type = 'T1000'
cxx_header = "dev/sparc/t1000.hh"
system = Param.System(Parent.any, "system")
fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000)
#warn_access="Accessing Clock Unit -- Unimplemented!")

32
src/dev/sparc/iob.cc
View File

@@ -42,7 +42,7 @@
#include "arch/sparc/isa_traits.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
#include "cpu/intr_control.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/Iob.hh"
#include "dev/platform.hh"
@@ -51,8 +51,7 @@
#include "sim/faults.hh"
#include "sim/system.hh"
Iob::Iob(const Params &p)
: PioDevice(p), ic(p.platform->intrctrl)
Iob::Iob(const Params &p) : PioDevice(p)
{
iobManAddr = 0x9800000000ULL;
iobManSize = 0x0100000000ULL;
@@ -268,37 +267,44 @@ Iob::receiveDeviceInterrupt(DeviceId devid)
intCtl[devid].pend = true;
DPRINTF(Iob, "Receiving Device interrupt: %d for cpu %d vec %d\n",
devid, intMan[devid].cpu, intMan[devid].vector);
ic->post(intMan[devid].cpu, SparcISA::IT_INT_VEC, intMan[devid].vector);
auto tc = sys->threads[intMan[devid].cpu];
tc->getCpuPtr()->postInterrupt(tc->threadId(), SparcISA::IT_INT_VEC,
intMan[devid].vector);
}
void
Iob::generateIpi(Type type, int cpu_id, int vector)
{
SparcISA::SparcFault<SparcISA::PowerOnReset> *por = new SparcISA::PowerOnReset();
SparcISA::SparcFault<SparcISA::PowerOnReset> *por =
new SparcISA::PowerOnReset();
if (cpu_id >= sys->threads.size())
return;
auto tc = sys->threads[cpu_id];
switch (type) {
case 0: // interrupt
DPRINTF(Iob, "Generating interrupt because of I/O write to cpu: %d vec %d\n",
DPRINTF(Iob,
"Generating interrupt because of I/O write to cpu: "
"%d vec %d\n",
cpu_id, vector);
ic->post(cpu_id, SparcISA::IT_INT_VEC, vector);
tc->getCpuPtr()->postInterrupt(
tc->threadId(), SparcISA::IT_INT_VEC, vector);
break;
case 1: // reset
warn("Sending reset to CPU: %d\n", cpu_id);
if (vector != por->trapType())
panic("Don't know how to set non-POR reset to cpu\n");
por->invoke(sys->threads[cpu_id]);
sys->threads[cpu_id]->activate();
por->invoke(tc);
tc->activate();
break;
case 2: // idle -- this means stop executing and don't wake on interrupts
DPRINTF(Iob, "Idling CPU because of I/O write cpu: %d\n", cpu_id);
sys->threads[cpu_id]->halt();
tc->halt();
break;
case 3: // resume
DPRINTF(Iob, "Resuming CPU because of I/O write cpu: %d\n", cpu_id);
sys->threads[cpu_id]->activate();
tc->activate();
break;
default:
panic("Invalid type to generate ipi\n");
@@ -321,7 +327,9 @@ Iob::receiveJBusInterrupt(int cpu_id, int source, uint64_t d0, uint64_t d1)
jBusData0[cpu_id] = d0;
jBusData1[cpu_id] = d1;
ic->post(cpu_id, SparcISA::IT_INT_VEC, jIntVec);
auto tc = sys->threads[cpu_id];
tc->getCpuPtr()->postInterrupt(
tc->threadId(), SparcISA::IT_INT_VEC, jIntVec);
return true;
}

3
src/dev/sparc/iob.hh
View File

@@ -37,8 +37,6 @@
#include "dev/io_device.hh"
#include "params/Iob.hh"
class IntrControl;
const int MaxNiagaraProcs = 32;
// IOB Managment Addresses
const Addr IntManAddr = 0x0000;
@@ -71,7 +69,6 @@ const uint64_t JIntBusyMask = 0x0003F;
class Iob : public PioDevice
{
private:
IntrControl *ic;
Addr iobManAddr;
Addr iobManSize;
Addr iobJBusAddr;

7
src/dev/sparc/t1000.cc
View File

@@ -36,12 +36,9 @@
#include <string>
#include <vector>
#include "cpu/intr_control.hh"
#include "sim/system.hh"
#include "base/logging.hh"
T1000::T1000(const Params &p)
: Platform(p), system(p.system)
{}
T1000::T1000(const Params &p) : Platform(p) {}
void
T1000::postConsoleInt()

5
src/dev/sparc/t1000.hh
View File

@@ -39,14 +39,9 @@
#include "params/T1000.hh"
class IdeController;
class System;
class T1000 : public Platform
{
public:
/** Pointer to the system */
System *system;
public:
typedef T1000Params Params;
/**

1
src/dev/storage/ide_ctrl.cc
View File

@@ -43,7 +43,6 @@
#include <string>
#include "base/cprintf.hh"
#include "cpu/intr_control.hh"
#include "debug/IdeCtrl.hh"
#include "dev/storage/ide_disk.hh"
#include "mem/packet.hh"

8
src/dev/x86/pc.cc
View File

@@ -38,18 +38,14 @@
#include "arch/x86/intmessage.hh"
#include "arch/x86/x86_traits.hh"
#include "cpu/intr_control.hh"
#include "dev/x86/i82094aa.hh"
#include "dev/x86/i8254.hh"
#include "dev/x86/i8259.hh"
#include "dev/x86/south_bridge.hh"
#include "sim/system.hh"
Pc::Pc(const Params &p)
: Platform(p), system(p.system)
{
southBridge = NULL;
}
Pc::Pc(const Params &p) : Platform(p)
{}
void
Pc::init()

4
src/dev/x86/pc.hh
View File

@@ -45,9 +45,7 @@ class SouthBridge;
class Pc : public Platform
{
public:
/** Pointer to the system */
System *system;
SouthBridge *southBridge;
SouthBridge *southBridge = nullptr;
public:
typedef PcParams Params;

2
tests/gem5/x86-boot-tests/system/system.py
View File

@@ -232,8 +232,6 @@ class MySystem(System):
self.iocache.cpu_side = self.iobus.master
self.iocache.mem_side = self.membus.slave
self.intrctrl = IntrControl()
###############################################
# Add in a Bios information structure.