5f95d7a89a
This vestigial device provides a thin layer of indirection between devices and the CPUs in a system. It's basically a collection of helper functions, but since it's a SimObject it needs to be instantiated in python and added to configurations. Change-Id: I029d2314ae0bb890678e1e68dafcdab4bfe49beb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43347 Reviewed-by: Gabe Black <gabe.black@gmail.com> Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
95 lines
2.7 KiB
C++
95 lines
2.7 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/** @file
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* Implementation of Malta platform.
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*/
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#include "dev/mips/malta.hh"
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#include <deque>
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#include <string>
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#include <vector>
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#include "debug/Malta.hh"
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#include "dev/mips/malta_cchip.hh"
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#include "dev/mips/malta_io.hh"
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#include "params/Malta.hh"
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#include "sim/system.hh"
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Malta::Malta(const Params &p)
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: Platform(p)
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{
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for (int i = 0; i < Malta::Max_CPUs; i++)
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intr_sum_type[i] = 0;
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}
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void
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Malta::postConsoleInt()
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{
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//see {Linux-src}/arch/mips/mips-boards/sim/sim_setup.c
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io->postIntr(0x10/*HW4*/);
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}
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void
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Malta::clearConsoleInt()
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{
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//FIXME: implement clearConsoleInt()
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io->clearIntr(0x10/*HW4*/);
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}
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void
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Malta::postPciInt(int line)
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{
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panic("Malta::postPciInt() has not been implemented.");
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}
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void
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Malta::clearPciInt(int line)
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{
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panic("Malta::clearPciInt() has not been implemented.");
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}
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Addr
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Malta::pciToDma(Addr pciAddr) const
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{
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panic("Malta::pciToDma() has not been implemented.");
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}
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void
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Malta::serialize(CheckpointOut &cp) const
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{
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SERIALIZE_ARRAY(intr_sum_type, Malta::Max_CPUs);
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}
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void
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Malta::unserialize(CheckpointIn &cp)
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{
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UNSERIALIZE_ARRAY(intr_sum_type, Malta::Max_CPUs);
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}
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