arch,base,cpu: Move some type aliases into base/types.hh.

The arch/generic/types.hh header includes some more complicated types
which in turn bring in more dependencies, adding baggage when other code
only needs the simple RegIndex or ElemIndex types. Also the RegVal type
alias is already in base/types.hh. It doesn't really make sense to have
RegVal in one header and RegIndex in another.

Change-Id: I1360652598b5fa59e0632b1ee0e0535ace2ba563
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42966
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

src/arch/generic/types.hh

@@ -42,21 +42,11 @@
 #define __ARCH_GENERIC_TYPES_HH__
 
 #include <iostream>
-#include <limits>
 
 #include "base/trace.hh"
 #include "base/types.hh"
 #include "sim/serialize.hh"
 
-// Logical register index type.
-typedef uint16_t RegIndex;
-
-/** Logical vector register elem index type. */
-using ElemIndex = uint16_t;
-
-/** ElemIndex value that indicates that the register is not a vector. */
-#define ILLEGAL_ELEM_INDEX std::numeric_limits<ElemIndex>::max()
-
 namespace GenericISA
 {
 

src/base/types.hh

@@ -38,6 +38,7 @@
 #include <inttypes.h>
 
 #include <cassert>
+#include <limits>
 #include <memory>
 #include <ostream>
 #include <stdexcept>
@@ -166,7 +167,17 @@ isRomMicroPC(MicroPC upc)
 
 const Addr MaxAddr = (Addr)-1;
 
-typedef uint64_t RegVal;
+using RegVal = uint64_t;
+
+// Logical register index type.
+using RegIndex = uint16_t;
+
+/** Logical vector register elem index type. */
+using ElemIndex = uint16_t;
+
+/** ElemIndex value that indicates that the register is not a vector. */
+static const ElemIndex IllegalElemIndex =
+    std::numeric_limits<ElemIndex>::max();
 
 static inline uint32_t
 floatToBits32(float val)

src/cpu/reg_class.hh

@@ -44,8 +44,8 @@
 #include <cassert>
 #include <cstddef>
 
-#include "arch/generic/types.hh"
 #include "arch/registers.hh"
+#include "base/types.hh"
 #include "config/the_isa.hh"
 
 /** Enumerate the classes of registers. */
@@ -100,13 +100,13 @@ class RegId
     RegId() : RegId(IntRegClass, 0) {}
 
     RegId(RegClass reg_class, RegIndex reg_idx)
-        : RegId(reg_class, reg_idx, ILLEGAL_ELEM_INDEX) {}
+        : RegId(reg_class, reg_idx, IllegalElemIndex) {}
 
     explicit RegId(RegClass reg_class, RegIndex reg_idx, ElemIndex elem_idx)
         : regClass(reg_class), regIdx(reg_idx), elemIdx(elem_idx),
           numPinnedWrites(0)
     {
-        if (elemIdx == ILLEGAL_ELEM_INDEX) {
+        if (elemIdx == IllegalElemIndex) {
             panic_if(regClass == VecElemClass,
                     "Creating vector physical index w/o element index");
         } else {