diff --git a/src/arch/generic/types.hh b/src/arch/generic/types.hh
index 76df835c7c..0f1e83737c 100644
--- a/src/arch/generic/types.hh
+++ b/src/arch/generic/types.hh
@@ -42,21 +42,11 @@
 #define __ARCH_GENERIC_TYPES_HH__
 
 #include <iostream>
-#include <limits>
 
 #include "base/trace.hh"
 #include "base/types.hh"
 #include "sim/serialize.hh"
 
-// Logical register index type.
-typedef uint16_t RegIndex;
-
-/** Logical vector register elem index type. */
-using ElemIndex = uint16_t;
-
-/** ElemIndex value that indicates that the register is not a vector. */
-#define ILLEGAL_ELEM_INDEX std::numeric_limits<ElemIndex>::max()
-
 namespace GenericISA
 {
 
diff --git a/src/base/types.hh b/src/base/types.hh
index 5e9a207924..5f4c741c8a 100644
--- a/src/base/types.hh
+++ b/src/base/types.hh
@@ -38,6 +38,7 @@
 #include <inttypes.h>
 
 #include <cassert>
+#include <limits>
 #include <memory>
 #include <ostream>
 #include <stdexcept>
@@ -166,7 +167,17 @@ isRomMicroPC(MicroPC upc)
 
 const Addr MaxAddr = (Addr)-1;
 
-typedef uint64_t RegVal;
+using RegVal = uint64_t;
+
+// Logical register index type.
+using RegIndex = uint16_t;
+
+/** Logical vector register elem index type. */
+using ElemIndex = uint16_t;
+
+/** ElemIndex value that indicates that the register is not a vector. */
+static const ElemIndex IllegalElemIndex =
+    std::numeric_limits<ElemIndex>::max();
 
 static inline uint32_t
 floatToBits32(float val)
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index 37207a2a28..d11dc2e19a 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -44,8 +44,8 @@
 #include <cassert>
 #include <cstddef>
 
-#include "arch/generic/types.hh"
 #include "arch/registers.hh"
+#include "base/types.hh"
 #include "config/the_isa.hh"
 
 /** Enumerate the classes of registers. */
@@ -100,13 +100,13 @@ class RegId
     RegId() : RegId(IntRegClass, 0) {}
 
     RegId(RegClass reg_class, RegIndex reg_idx)
-        : RegId(reg_class, reg_idx, ILLEGAL_ELEM_INDEX) {}
+        : RegId(reg_class, reg_idx, IllegalElemIndex) {}
 
     explicit RegId(RegClass reg_class, RegIndex reg_idx, ElemIndex elem_idx)
         : regClass(reg_class), regIdx(reg_idx), elemIdx(elem_idx),
           numPinnedWrites(0)
     {
-        if (elemIdx == ILLEGAL_ELEM_INDEX) {
+        if (elemIdx == IllegalElemIndex) {
             panic_if(regClass == VecElemClass,
                     "Creating vector physical index w/o element index");
         } else {