arch,cpu: Separate printing and serialization of VecPredReg.

This is equivalent to what was done with VecReg recently.

Change-Id: I8e28c9796bf5cabd35a6bf5b89e55efcf9324d92
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41999
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/generic/vec_pred_reg.hh

@@ -42,6 +42,7 @@
 
 #include "arch/generic/vec_reg.hh"
 #include "base/cprintf.hh"
+#include "sim/serialize_handlers.hh"
 
 template <size_t NumBits, bool Packed>
 class VecPredRegContainer;
@@ -152,18 +153,13 @@ class VecPredRegT
     friend std::ostream&
     operator<<(std::ostream& os, const MyClass& p)
     {
-        // 0-sized is not allowed
-        os << '[' << p.container[0];
-        for (int i = 0; i < p.NUM_BITS; ++i) {
-            os << " " << (p.container[i] ? 1 : 0);
-        }
-        os << ']';
+        // Size must be greater than 0.
+        for (int i = 0; i < NUM_BITS; i++)
+            ccprintf(os, "%s%d", i ? " " : "[", (int)p.container[i]);
+        ccprintf(os, "]");
         return os;
     }
 
-    /// Returns a string representation of the register content.
-    const std::string print() const { return csprintf("%s", *this); }
-
     /// Returns true if the first active element of the register is true.
     /// @param mask Input mask used to filter the predicates to be tested.
     /// @param actual_num_elems Actual number of vector elements considered for
@@ -326,18 +322,18 @@ class VecPredRegContainer
         }
     }
 
-    /// Returns a string representation of the register content.
-    const std::string print() const { return csprintf("%s", *this); }
-
     friend std::ostream&
-    operator<<(std::ostream& os, const MyClass& v)
+    operator<<(std::ostream& os, const MyClass& p)
     {
-        for (auto b: v.container) {
-            os << csprintf("%d", b);
-        }
+        // Size must be greater than 0.
+        for (int i = 0; i < NumBits; i++)
+            ccprintf(os, "%s%d", i ? " " : "[", (int)p.container[i]);
+        ccprintf(os, "]");
         return os;
     }
 
+    friend ShowParam<VecPredRegContainer<NumBits, Packed>>;
+
     /// Create a view of this container.
     ///
     /// If NumElems is provided, the size of the container is bounds-checked,
@@ -371,17 +367,29 @@ class VecPredRegContainer
     /// @}
 };
 
-/// Helper functions used for serialization/de-serialization
 template <size_t NumBits, bool Packed>
-inline bool
-to_number(const std::string& value, VecPredRegContainer<NumBits, Packed>& p)
+struct ParseParam<VecPredRegContainer<NumBits, Packed>>
 {
-    int i = 0;
-    for (const auto& c: value) {
-        p[i] = (c == '1');
+    static bool
+    parse(const std::string &s, VecPredRegContainer<NumBits, Packed> &value)
+    {
+        int i = 0;
+        for (const auto& c: s)
+            value[i++] = (c == '1');
+        return true;
     }
-    return true;
-}
+};
+
+template <size_t NumBits, bool Packed>
+struct ShowParam<VecPredRegContainer<NumBits, Packed>>
+{
+    static void
+    show(std::ostream &os, const VecPredRegContainer<NumBits, Packed> &value)
+    {
+        for (auto b: value.container)
+            ccprintf(os, "%d", b);
+    }
+};
 
 /// Dummy type aliases and constants for architectures that do not implement
 /// vector predicate registers.

src/cpu/o3/regfile.hh

@@ -239,7 +239,7 @@ class PhysRegFile
 
         DPRINTF(IEW, "RegFile: Access to predicate register %i, has "
                 "data %s\n", int(phys_reg->index()),
-                vecPredRegFile[phys_reg->index()].print());
+                vecPredRegFile[phys_reg->index()]);
 
         return vecPredRegFile[phys_reg->index()];
     }
@@ -323,7 +323,7 @@ class PhysRegFile
         assert(phys_reg->isVecPredPhysReg());
 
         DPRINTF(IEW, "RegFile: Setting predicate register %i to %s\n",
-                int(phys_reg->index()), val.print());
+                int(phys_reg->index()), val);
 
         vecPredRegFile[phys_reg->index()] = val;
     }

src/cpu/simple_thread.hh

@@ -330,7 +330,7 @@ class SimpleThread : public ThreadState, public ThreadContext
         const TheISA::VecPredRegContainer& regVal =
             readVecPredRegFlat(flatIndex);
         DPRINTF(VecPredRegs, "Reading predicate reg %d (%d) as %s.\n",
-                reg.index(), flatIndex, regVal.print());
+                reg.index(), flatIndex, regVal);
         return regVal;
     }
 
@@ -343,7 +343,7 @@ class SimpleThread : public ThreadState, public ThreadContext
             getWritableVecPredRegFlat(flatIndex);
         DPRINTF(VecPredRegs,
                 "Reading predicate reg %d (%d) as %s for modify.\n",
-                reg.index(), flatIndex, regVal.print());
+                reg.index(), flatIndex, regVal);
         return regVal;
     }
 
@@ -410,7 +410,7 @@ class SimpleThread : public ThreadState, public ThreadContext
         assert(flatIndex < vecPredRegs.size());
         setVecPredRegFlat(flatIndex, val);
         DPRINTF(VecPredRegs, "Setting predicate reg %d (%d) to %s.\n",
-                reg.index(), flatIndex, val.print());
+                reg.index(), flatIndex, val);
     }
 
     void