arch,cpu: Rename arch/registers.hh to arch/vecregs.hh.

The only thing still in arch/registers.hh were related to vector
registers. To make it obvious that nothing else should be added, this
change renames the file so that it has the much less generic name
arch/vecregs.hh.

Change-Id: I729697dc576e1978047688d9700dc07ff9b17044
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42686
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/SConscript

@@ -61,9 +61,9 @@ env.SwitchingHeaders(
         isa.hh
         locked_mem.hh
         page_size.hh
-        registers.hh
         remote_gdb.hh
         types.hh
+        vecregs.hh
         '''),
     env.subst('${TARGET_ISA}'))
 

src/arch/arm/htm.hh

@@ -44,8 +44,8 @@
  * ISA-specific types for hardware transactional memory.
  */
 
-#include "arch/arm/registers.hh"
 #include "arch/arm/regs/int.hh"
+#include "arch/arm/regs/vec.hh"
 #include "arch/generic/htm.hh"
 #include "base/types.hh"
 

src/arch/arm/insts/tme64ruby.cc

@@ -39,7 +39,6 @@
 #include "arch/arm/htm.hh"
 #include "arch/arm/insts/tme64.hh"
 #include "arch/arm/locked_mem.hh"
-#include "arch/arm/registers.hh"
 #include "arch/generic/memhelpers.hh"
 #include "debug/ArmTme.hh"
 #include "mem/packet_access.hh"

src/arch/arm/interrupts.hh

@@ -42,7 +42,6 @@
 #define __ARCH_ARM_INTERRUPT_HH__
 
 #include "arch/arm/faults.hh"
-#include "arch/arm/registers.hh"
 #include "arch/arm/regs/misc.hh"
 #include "arch/arm/utility.hh"
 #include "arch/generic/interrupts.hh"

src/arch/arm/isa.hh

@@ -42,7 +42,7 @@
 #define __ARCH_ARM_ISA_HH__
 
 #include "arch/arm/isa_device.hh"
-#include "arch/arm/registers.hh"
+#include "arch/arm/regs/int.hh"
 #include "arch/arm/regs/misc.hh"
 #include "arch/arm/self_debug.hh"
 #include "arch/arm/system.hh"

src/arch/arm/isa_device.hh

@@ -38,8 +38,8 @@
 #ifndef __ARCH_ARM_ISA_DEVICE_HH__
 #define __ARCH_ARM_ISA_DEVICE_HH__
 
-#include "arch/arm/registers.hh"
 #include "base/compiler.hh"
+#include "base/types.hh"
 
 class ThreadContext;
 

src/arch/arm/kvm/arm_cpu.cc

@@ -44,7 +44,8 @@
 #include <memory>
 
 #include "arch/arm/interrupts.hh"
-#include "arch/arm/registers.hh"
+#include "arch/arm/regs/int.hh"
+#include "arch/arm/regs/misc.hh"
 #include "cpu/kvm/base.hh"
 #include "debug/Kvm.hh"
 #include "debug/KvmContext.hh"

src/arch/arm/linux/se_workload.hh

@@ -29,7 +29,7 @@
 #define __ARCH_ARM_LINUX_SE_WORKLOAD_HH__
 
 #include "arch/arm/linux/linux.hh"
-#include "arch/arm/registers.hh"
+#include "arch/arm/regs/int.hh"
 #include "arch/arm/se_workload.hh"
 #include "params/ArmEmuLinux.hh"
 #include "sim/syscall_desc.hh"

src/arch/arm/pmu.hh

@@ -43,7 +43,6 @@
 #include <vector>
 
 #include "arch/arm/isa_device.hh"
-#include "arch/arm/registers.hh"
 #include "arch/arm/system.hh"
 #include "base/cprintf.hh"
 #include "cpu/base.hh"

src/arch/arm/remote_gdb.cc

@@ -137,7 +137,7 @@
 
 #include "arch/arm/decoder.hh"
 #include "arch/arm/pagetable.hh"
-#include "arch/arm/registers.hh"
+#include "arch/arm/regs/vec.hh"
 #include "arch/arm/system.hh"
 #include "arch/arm/utility.hh"
 #include "arch/generic/mmu.hh"

src/arch/arm/remote_gdb.hh

@@ -46,7 +46,7 @@
 
 #include <algorithm>
 
-#include "arch/arm/registers.hh"
+#include "arch/arm/regs/vec.hh"
 #include "arch/arm/utility.hh"
 #include "base/compiler.hh"
 #include "base/remote_gdb.hh"

src/arch/arm/tracers/tarmac_base.hh

@@ -49,7 +49,6 @@
 #ifndef __ARCH_ARM_TRACERS_TARMAC_BASE_HH__
 #define __ARCH_ARM_TRACERS_TARMAC_BASE_HH__
 
-#include "arch/arm/registers.hh"
 #include "base/trace.hh"
 #include "base/types.hh"
 #include "cpu/static_inst.hh"

src/arch/arm/tracers/tarmac_parser.hh

@@ -49,7 +49,6 @@
 #include <fstream>
 #include <unordered_map>
 
-#include "arch/arm/registers.hh"
 #include "base/trace.hh"
 #include "base/types.hh"
 #include "cpu/static_inst.hh"

src/arch/arm/vecregs.hh

@@ -38,8 +38,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __ARCH_ARM_REGISTERS_HH__
-#define __ARCH_ARM_REGISTERS_HH__
+#ifndef __ARCH_ARM_VECREGS_HH__
+#define __ARCH_ARM_VECREGS_HH__
 
 #include "arch/arm/regs/vec.hh"
 

src/arch/mips/vecregs.hh

@@ -27,8 +27,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __ARCH_MIPS_REGISTERS_HH__
-#define __ARCH_MIPS_REGISTERS_HH__
+#ifndef __ARCH_MIPS_VECREGS_HH__
+#define __ARCH_MIPS_VECREGS_HH__
 
 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"

src/arch/null/vecregs.hh

@@ -35,8 +35,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __ARCH_NULL_REGISTERS_HH__
-#define __ARCH_NULL_REGISTERS_HH__
+#ifndef __ARCH_NULL_VECREGS_HH__
+#define __ARCH_NULL_VECREGS_HH__
 
 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"
@@ -59,4 +59,4 @@ constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
 
 }
 
-#endif // __ARCH_NULL_REGISTERS_HH__
+#endif // __ARCH_NULL_VECREGS_HH__

src/arch/power/vecregs.hh

@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __ARCH_POWER_REGISTERS_HH__
-#define __ARCH_POWER_REGISTERS_HH__
+#ifndef __ARCH_POWER_VECREGS_HH__
+#define __ARCH_POWER_VECREGS_HH__
 
 #include <cstdint>
 
@@ -52,4 +52,4 @@ constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
 
 } // namespace PowerISA
 
-#endif // __ARCH_POWER_REGISTERS_HH__
+#endif // __ARCH_POWER_VECREGS_HH__

src/arch/riscv/vecregs.hh

@@ -43,8 +43,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __ARCH_RISCV_REGISTERS_HH__
-#define __ARCH_RISCV_REGISTERS_HH__
+#ifndef __ARCH_RISCV_VECREGS_HH__
+#define __ARCH_RISCV_VECREGS_HH__
 
 #include <cstdint>
 
@@ -69,4 +69,4 @@ constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
 
 }
 
-#endif // __ARCH_RISCV_REGISTERS_HH__
+#endif // __ARCH_RISCV_VECREGS_HH__

src/arch/sparc/vecregs.hh

@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __ARCH_SPARC_REGISTERS_HH__
-#define __ARCH_SPARC_REGISTERS_HH__
+#ifndef __ARCH_SPARC_VECREGS_HH__
+#define __ARCH_SPARC_VECREGS_HH__
 
 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"

src/arch/x86/emulenv.hh

@@ -40,7 +40,6 @@
 
 #include "arch/x86/regs/int.hh"
 #include "arch/x86/regs/segment.hh"
-#include "arch/x86/registers.hh"
 #include "arch/x86/types.hh"
 
 namespace X86ISA

src/arch/x86/isa.cc

@@ -30,7 +30,6 @@
 
 #include "arch/x86/decoder.hh"
 #include "arch/x86/mmu.hh"
-#include "arch/x86/registers.hh"
 #include "arch/x86/regs/ccr.hh"
 #include "arch/x86/regs/int.hh"
 #include "arch/x86/regs/misc.hh"

src/arch/x86/isa.hh

@@ -33,7 +33,6 @@
 #include <string>
 
 #include "arch/generic/isa.hh"
-#include "arch/x86/registers.hh"
 #include "arch/x86/regs/float.hh"
 #include "arch/x86/regs/misc.hh"
 #include "base/types.hh"

src/arch/x86/isa/includes.isa

@@ -60,7 +60,6 @@ output header {{
 #include "arch/x86/insts/micromediaop.hh"
 #include "arch/x86/insts/microregop.hh"
 #include "arch/x86/insts/static_inst.hh"
-#include "arch/x86/registers.hh"
 #include "arch/x86/types.hh"
 #include "arch/x86/utility.hh"
 #include "base/logging.hh"

src/arch/x86/linux/se_workload.cc

@@ -43,7 +43,6 @@
 #include "arch/x86/linux/linux.hh"
 #include "arch/x86/page_size.hh"
 #include "arch/x86/process.hh"
-#include "arch/x86/registers.hh"
 #include "arch/x86/se_workload.hh"
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"

src/arch/x86/linux/syscalls.cc

@@ -29,7 +29,6 @@
 
 #include "arch/x86/linux/linux.hh"
 #include "arch/x86/process.hh"
-#include "arch/x86/registers.hh"
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
 #include "kern/linux/linux.hh"

src/arch/x86/pseudo_inst_abi.hh

@@ -35,7 +35,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "arch/x86/registers.hh"
+#include "arch/x86/regs/int.hh"
 #include "sim/guest_abi.hh"
 
 struct X86PseudoInstABI

src/arch/x86/vecregs.hh

@@ -36,8 +36,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __ARCH_X86_REGISTERS_HH__
-#define __ARCH_X86_REGISTERS_HH__
+#ifndef __ARCH_X86_VECREGS_HH__
+#define __ARCH_X86_VECREGS_HH__
 
 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"
@@ -76,4 +76,4 @@ constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
 
 } // namespace X86ISA
 
-#endif // __ARCH_X86_REGFILE_HH__
+#endif // __ARCH_X86_VECREGS_HH__

src/cpu/exec_context.hh

@@ -42,7 +42,7 @@
 #ifndef __CPU_EXEC_CONTEXT_HH__
 #define __CPU_EXEC_CONTEXT_HH__
 
-#include "arch/registers.hh"
+#include "arch/vecregs.hh"
 #include "base/types.hh"
 #include "config/the_isa.hh"
 #include "cpu/base.hh"

src/cpu/kvm/x86_cpu.cc

@@ -34,7 +34,6 @@
 #include <cerrno>
 #include <memory>
 
-#include "arch/registers.hh"
 #include "arch/x86/cpuid.hh"
 #include "arch/x86/faults.hh"
 #include "arch/x86/interrupts.hh"

src/cpu/minor/dyn_inst.cc

@@ -41,7 +41,6 @@
 #include <sstream>
 
 #include "arch/isa.hh"
-#include "arch/registers.hh"
 #include "cpu/base.hh"
 #include "cpu/minor/trace.hh"
 #include "cpu/null_static_inst.hh"

src/cpu/minor/execute.cc

@@ -38,7 +38,6 @@
 #include "cpu/minor/execute.hh"
 
 #include "arch/locked_mem.hh"
-#include "arch/registers.hh"
 #include "cpu/minor/cpu.hh"
 #include "cpu/minor/exec_context.hh"
 #include "cpu/minor/fetch1.hh"

src/cpu/minor/scoreboard.cc

@@ -37,7 +37,6 @@
 
 #include "cpu/minor/scoreboard.hh"
 
-#include "arch/registers.hh"
 #include "cpu/reg_class.hh"
 #include "debug/MinorScoreboard.hh"
 #include "debug/MinorTiming.hh"

src/cpu/o3/regfile.hh

@@ -45,7 +45,7 @@
 #include <vector>
 
 #include "arch/generic/isa.hh"
-#include "arch/registers.hh"
+#include "arch/vecregs.hh"
 #include "base/trace.hh"
 #include "config/the_isa.hh"
 #include "cpu/o3/comm.hh"

src/cpu/o3/rename_map.cc

@@ -43,7 +43,7 @@
 
 #include <vector>
 
-#include "arch/registers.hh"
+#include "arch/vecregs.hh"
 #include "cpu/reg_class.hh"
 #include "debug/Rename.hh"
 

src/cpu/o3/rob.hh

@@ -45,9 +45,7 @@
 #include <utility>
 #include <vector>
 
-#include "arch/registers.hh"
 #include "base/types.hh"
-#include "config/the_isa.hh"
 #include "cpu/o3/limits.hh"
 #include "enums/SMTQueuePolicy.hh"
 

src/cpu/o3/thread_context_impl.hh

@@ -42,7 +42,7 @@
 #ifndef __CPU_O3_THREAD_CONTEXT_IMPL_HH__
 #define __CPU_O3_THREAD_CONTEXT_IMPL_HH__
 
-#include "arch/registers.hh"
+#include "arch/vecregs.hh"
 #include "config/the_isa.hh"
 #include "cpu/o3/thread_context.hh"
 #include "debug/O3CPU.hh"

src/cpu/reg_class.hh

@@ -44,7 +44,7 @@
 #include <cassert>
 #include <cstddef>
 
-#include "arch/registers.hh"
+#include "arch/vecregs.hh"
 #include "base/types.hh"
 #include "config/the_isa.hh"
 

src/cpu/simple/exec_context.hh

@@ -41,7 +41,7 @@
 #ifndef __CPU_SIMPLE_EXEC_CONTEXT_HH__
 #define __CPU_SIMPLE_EXEC_CONTEXT_HH__
 
-#include "arch/registers.hh"
+#include "arch/vecregs.hh"
 #include "base/types.hh"
 #include "config/the_isa.hh"
 #include "cpu/base.hh"

src/cpu/simple_thread.hh

@@ -50,8 +50,8 @@
 #include "arch/generic/mmu.hh"
 #include "arch/generic/tlb.hh"
 #include "arch/isa.hh"
-#include "arch/registers.hh"
 #include "arch/types.hh"
+#include "arch/vecregs.hh"
 #include "base/types.hh"
 #include "config/the_isa.hh"
 #include "cpu/thread_context.hh"

src/cpu/thread_context.hh

@@ -47,8 +47,8 @@
 
 #include "arch/generic/htm.hh"
 #include "arch/generic/isa.hh"
-#include "arch/registers.hh"
 #include "arch/types.hh"
+#include "arch/vecregs.hh"
 #include "base/types.hh"
 #include "config/the_isa.hh"
 #include "cpu/pc_event.hh"

src/cpu/trace/trace_cpu.hh

@@ -44,7 +44,6 @@
 #include <set>
 #include <unordered_map>
 
-#include "arch/registers.hh"
 #include "base/statistics.hh"
 #include "cpu/base.hh"
 #include "debug/TraceCPUData.hh"

src/dev/riscv/clint.hh

@@ -39,7 +39,6 @@
 #define __DEV_RISCV_CLINT_HH__
 
 #include "arch/riscv/interrupts.hh"
-#include "arch/riscv/registers.hh"
 #include "dev/intpin.hh"
 #include "dev/io_device.hh"
 #include "dev/mc146818.hh"

src/dev/riscv/plic.cc

@@ -40,7 +40,6 @@
 
 #include <algorithm>
 
-#include "arch/riscv/registers.hh"
 #include "cpu/base.hh"
 #include "debug/Plic.hh"
 #include "mem/packet.hh"

src/sim/process.hh

@@ -37,11 +37,9 @@
 #include <string>
 #include <vector>
 
-#include "arch/registers.hh"
 #include "base/loader/memory_image.hh"
 #include "base/statistics.hh"
 #include "base/types.hh"
-#include "config/the_isa.hh"
 #include "mem/se_translating_port_proxy.hh"
 #include "sim/fd_array.hh"
 #include "sim/fd_entry.hh"