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misc: Replace M5_FALLTHROUGH with GEM5_FALLTHROUGH.

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Change-Id: I058f311b6d9c284f745bcc915db72236d05db21b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45233
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-05-08 20:29:26 -07:00
parent e1fea279e2
commit 11fe13c311
21 changed files with 38 additions and 38 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/arm/insts/pred_inst.hh
View File

@@ -150,7 +150,7 @@ simd_modified_imm(bool op, uint8_t cmode, uint8_t data, bool &immValid,
break;
}
}
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
default:
immValid = false;
break;

2
src/arch/arm/isa/formats/aarch64.isa
View File

@@ -595,7 +595,7 @@ namespace Aarch64
return new Unknown64(machInst);
}
}
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
default:
return new Unknown64(machInst);
}

4
src/arch/arm/isa/formats/data.isa
View File

@@ -1440,7 +1440,7 @@ def format Thumb32DataProcPlainBin() {{
const uint32_t satImm = bits(machInst, 4, 0);
return new Ssat16(machInst, rd, satImm + 1, rn);
}
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case 0x10:
{
const uint32_t satImm = bits(machInst, 4, 0);
@@ -1473,7 +1473,7 @@ def format Thumb32DataProcPlainBin() {{
const uint32_t satImm = bits(machInst, 4, 0);
return new Usat16(machInst, rd, satImm, rn);
}
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case 0x18:
{
const uint32_t satImm = bits(machInst, 4, 0);

4
src/arch/arm/isa/formats/fp.isa
View File

@@ -131,7 +131,7 @@ let {{
width = 1;
break;
}
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
default:
return new Unknown(machInst);
}
@@ -2113,7 +2113,7 @@ let {{
false, true, true, offset);
}
}
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case 0x3:
const bool up = (bits(machInst, 23) == 1);
const uint32_t imm = bits(machInst, 7, 0) << 2;

2
src/arch/arm/isa/formats/sve_top_level.isa
View File

@@ -248,7 +248,7 @@ namespace Aarch64
case 4:
if (!bits(machInst, 10))
return decodeSveFpMulIndexed(machInst);
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
default:
return new Unknown64(machInst);
}

2
src/arch/arm/regs/misc.cc
View File

@@ -2865,7 +2865,7 @@ decodeAArch64SysReg(unsigned op0, unsigned op1,
}
break;
}
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
default:
// S3_<op1>_11_<Cm>_<op2>
return MISCREG_IMPDEF_UNIMPL;

2
src/arch/arm/table_walker.cc
View File

@@ -1562,7 +1562,7 @@ TableWalker::memAttrsAArch64(ThreadContext *tc, TlbEntry &te,
case 0x1 ... 0x3: // Normal Memory, Inner Write-through transient
case 0x9 ... 0xb: // Normal Memory, Inner Write-through non-transient
warn_if(!attr_hi, "Unpredictable behavior");
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case 0x4: // Device-nGnRE memory or
// Normal memory, Inner Non-cacheable
case 0x8: // Device-nGRE memory or

2
src/arch/arm/tlb.cc
View File

@@ -978,7 +978,7 @@ TLB::checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode,
grant_read = false;
break;
}
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case EL3:
{
uint8_t perm = (ap & 0x2) | xn;

2
src/arch/arm/utility.cc
View File

@@ -140,7 +140,7 @@ readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
// be part of the table even if MPIDR is not accessible in user
// mode.
warn_once("Trying to read MPIDR at EL0\n");
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case EL1:
if (ArmSystem::haveEL(tc, EL2) && !is_secure)
return tc->readMiscReg(MISCREG_VMPIDR_EL2);

4
src/arch/sparc/tlb.cc
View File

@@ -1246,7 +1246,7 @@ TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
break;
case ASI_ITLB_DATA_ACCESS_REG:
entry_insert = bits(va, 8,3);
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case ASI_ITLB_DATA_IN_REG:
assert(entry_insert != -1 || mbits(va,10,9) == va);
ta_insert = itb->tag_access;
@@ -1261,7 +1261,7 @@ TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
break;
case ASI_DTLB_DATA_ACCESS_REG:
entry_insert = bits(va, 8,3);
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case ASI_DTLB_DATA_IN_REG:
assert(entry_insert != -1 || mbits(va,10,9) == va);
ta_insert = tag_access;

4
src/arch/x86/isa.cc
View File

@@ -377,7 +377,7 @@ ISA::setMiscReg(int miscReg, RegVal val)
break;
case MISCREG_DR4:
miscReg = MISCREG_DR6;
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case MISCREG_DR6:
{
DR6 dr6 = regVal[MISCREG_DR6];
@@ -394,7 +394,7 @@ ISA::setMiscReg(int miscReg, RegVal val)
break;
case MISCREG_DR5:
miscReg = MISCREG_DR7;
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case MISCREG_DR7:
{
DR7 dr7 = regVal[MISCREG_DR7];

2
src/arch/x86/isa/microops/regop.isa
View File

@@ -1504,7 +1504,7 @@ let {{
fault = std::make_shared<GeneralProtection>(selector);
break;
}
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case SegIntGateCheck:
// Make sure the gate's the right type.
if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) ||

8
src/base/cprintf.cc
View File

@@ -139,7 +139,7 @@ Print::processFlag()
case 'X':
fmt.uppercase = true;
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case 'x':
fmt.base = Format::Hex;
fmt.format = Format::Integer;
@@ -161,7 +161,7 @@ Print::processFlag()
case 'G':
fmt.uppercase = true;
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case 'g':
fmt.format = Format::Floating;
fmt.floatFormat = Format::Best;
@@ -170,7 +170,7 @@ Print::processFlag()
case 'E':
fmt.uppercase = true;
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case 'e':
fmt.format = Format::Floating;
fmt.floatFormat = Format::Scientific;
@@ -217,7 +217,7 @@ Print::processFlag()
fmt.fillZero = true;
break;
}
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case '1':
case '2':
case '3':

2
src/base/imgwriter.cc
View File

@@ -57,7 +57,7 @@ createImgWriter(Enums::ImageFormat type, const FrameBuffer *fb)
// gem5 will try PNG first, and it will fallback to BMP if not
// available.
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
#if HAVE_PNG
case Enums::Png:
return std::unique_ptr<PngWriter>(new PngWriter(fb));

2
src/cpu/kvm/base.cc
View File

@@ -332,7 +332,7 @@ BaseKvmCPU::drain()
deschedule(tickEvent);
_status = Idle;
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case Idle:
// Idle, no need to drain
assert(!tickEvent.scheduled());

10
src/cpu/kvm/x86_cpu.cc
View File

@@ -398,7 +398,7 @@ checkSeg(const char *name, const int idx, const struct kvm_segment &seg,
case MISCREG_ES:
if (seg.unusable)
break;
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case MISCREG_CS:
if (seg.base & 0xffffffff00000000ULL)
warn("Illegal %s base: 0x%x\n", name, seg.base);
@@ -436,7 +436,7 @@ checkSeg(const char *name, const int idx, const struct kvm_segment &seg,
case 3:
if (sregs.cs.type == 3 && seg.dpl != 0)
warn("CS type is 3, but SS DPL is != 0.\n");
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case 7:
if (!(sregs.cr0 & 1) && seg.dpl != 0)
warn("SS DPL is %i, but CR0 PE is 0\n", seg.dpl);
@@ -480,7 +480,7 @@ checkSeg(const char *name, const int idx, const struct kvm_segment &seg,
case MISCREG_GS:
if (seg.unusable)
break;
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case MISCREG_CS:
if (!seg.s)
warn("%s: S flag not set\n", name);
@@ -489,7 +489,7 @@ checkSeg(const char *name, const int idx, const struct kvm_segment &seg,
case MISCREG_TSL:
if (seg.unusable)
break;
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case MISCREG_TR:
if (seg.s)
warn("%s: S flag is set\n", name);
@@ -505,7 +505,7 @@ checkSeg(const char *name, const int idx, const struct kvm_segment &seg,
case MISCREG_TSL:
if (seg.unusable)
break;
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case MISCREG_TR:
case MISCREG_CS:
if (!seg.present)

4
src/dev/arm/smmu_v3.cc
View File

@@ -249,7 +249,7 @@ SMMUv3::runProcessAtomic(SMMUProcess *proc, PacketPtr pkt)
pkt = action.pkt;
break;
}
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case ACTION_SEND_REQ_FINAL:
delay += requestPort.sendAtomic(action.pkt);
pkt = action.pkt;
@@ -305,7 +305,7 @@ SMMUv3::runProcessTiming(SMMUProcess *proc, PacketPtr pkt)
break;
}
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case ACTION_SEND_REQ_FINAL:
action.pkt->pushSenderState(proc);

2
src/dev/storage/ide_disk.cc
View File

@@ -682,7 +682,7 @@ IdeDisk::startCommand()
// Supported DMA commands
case WDCC_WRITEDMA:
dmaRead = true; // a write to the disk is a DMA read from memory
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case WDCC_READDMA:
if (!(cmdReg.drive & DRIVE_LBA_BIT))
panic("Attempt to perform CHS access, only supports LBA\n");

2
src/kern/linux/printk.cc
View File

@@ -104,7 +104,7 @@ printk(std::string &str, ThreadContext *tc, Addr format_ptr,
break;
case 'P':
format = true;
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case 'p':
hexnum = true;
break;

2
src/mem/slicc/symbols/Type.py
View File

@@ -736,7 +736,7 @@ ${{self.c_ident}}_base_number(const ${{self.c_ident}}& obj)
code(' base += ${{enum.ident}}_Controller::getNumControllers();')
else:
code(' base += 0;')
code(' M5_FALLTHROUGH;')
code(' GEM5_FALLTHROUGH;')
code(' case ${{self.c_ident}}_${{enum.ident}}:')
code(' break;')
code.dedent()

12
src/systemc/dt/fx/scfx_rep.cc
View File

@@ -549,10 +549,10 @@ scfx_rep::from_string(const char *s, int cte_wl)
switch (*s) {
case '1':
set_bin(j);
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case '0':
j--;
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case '.':
break;
default:
@@ -587,10 +587,10 @@ scfx_rep::from_string(const char *s, int cte_wl)
case '7': case '6': case '5': case '4':
case '3': case '2': case '1':
set_oct(j, *s - '0');
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case '0':
j -= 3;
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case '.':
break;
default:
@@ -677,10 +677,10 @@ scfx_rep::from_string(const char *s, int cte_wl)
case '9': case '8': case '7': case '6': case '5':
case '4': case '3': case '2': case '1':
set_hex(j, *s - '0');
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case '0':
j -= 4;
M5_FALLTHROUGH;
GEM5_FALLTHROUGH;
case '.':
break;
default: