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arch,cpu: Get rid of is*Reg() methods in RegId.

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These bake in the existing set of RegClass values and are not flexible
or scalable.

Change-Id: I107460cd82960d96916d1644403b7635820045a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45226
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-05-02 05:43:41 -07:00
parent ed5832c273
commit 16fa9f9812
16 changed files with 162 additions and 194 deletions
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4
src/arch/arm/insts/misc.cc
View File

@@ -52,7 +52,7 @@ MrsOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
bool foundPsr = false;
for (unsigned i = 0; i < numSrcRegs(); i++) {
const RegId& reg = srcRegIdx(i);
if (!reg.isMiscReg()) {
if (!reg.is(MiscRegClass)) {
continue;
}
if (reg.index() == MISCREG_CPSR) {
@@ -80,7 +80,7 @@ MsrBase::printMsrBase(std::ostream &os) const
bool foundPsr = false;
for (unsigned i = 0; i < numDestRegs(); i++) {
const RegId& reg = destRegIdx(i);
if (!reg.isMiscReg()) {
if (!reg.is(MiscRegClass)) {
continue;
}
if (reg.index() == MISCREG_CPSR) {

2
src/arch/mips/isa/base.isa
View File

@@ -88,7 +88,7 @@ output decoder {{
void
MipsStaticInst::printReg(std::ostream &os, RegId reg) const
{
if (reg.isIntReg()) {
if (reg.is(IntRegClass)) {
ccprintf(os, "r%d", reg.index());
} else {
ccprintf(os, "f%d", reg.index());

15
src/arch/power/insts/static_inst.cc
View File

@@ -36,11 +36,14 @@ using namespace PowerISA;
void
PowerStaticInst::printReg(std::ostream &os, RegId reg) const
{
if (reg.isIntReg())
switch (reg.classValue()) {
case IntRegClass:
ccprintf(os, "r%d", reg.index());
else if (reg.isFloatReg())
break;
case FloatRegClass:
ccprintf(os, "f%d", reg.index());
else if (reg.isMiscReg())
break;
case MiscRegClass:
switch (reg.index()) {
case 0: ccprintf(os, "cr"); break;
case 1: ccprintf(os, "xer"); break;
@@ -49,8 +52,10 @@ PowerStaticInst::printReg(std::ostream &os, RegId reg) const
default: ccprintf(os, "unknown_reg");
break;
}
else if (reg.isCCReg())
panic("printReg: POWER does not implement CCRegClass\n");
break;
default:
panic("printReg: Unrecognized register class.");
}
}
std::string

2
src/arch/riscv/utility.hh
View File

@@ -102,7 +102,7 @@ issignalingnan<double>(double val)
inline std::string
registerName(RegId reg)
{
if (reg.isIntReg()) {
if (reg.is(IntRegClass)) {
if (reg.index() >= NumIntArchRegs) {
/*
* This should only happen if a instruction is being speculatively

4
src/arch/sparc/insts/static_inst.cc
View File

@@ -104,7 +104,7 @@ SparcStaticInst::printReg(std::ostream &os, RegId reg)
const int MaxInput = 32;
const int MaxMicroReg = 40;
RegIndex reg_idx = reg.index();
if (reg.isIntReg()) {
if (reg.is(IntRegClass)) {
// If we used a register from the next or previous window,
// take out the offset.
while (reg_idx >= MaxMicroReg)
@@ -149,7 +149,7 @@ SparcStaticInst::printReg(std::ostream &os, RegId reg)
break;
}
}
} else if (reg.isFloatReg()) {
} else if (reg.is(FloatRegClass)) {
ccprintf(os, "%%f%d", reg_idx);
} else {
switch (reg_idx) {

138
src/arch/x86/insts/static_inst.cc
View File

@@ -150,71 +150,74 @@ X86StaticInst::printReg(std::ostream &os, RegId reg, int size)
RegIndex reg_idx = reg.index();
if (reg.isIntReg()) {
const char * suffix = "";
bool fold = reg_idx & IntFoldBit;
reg_idx &= ~IntFoldBit;
switch (reg.classValue()) {
case IntRegClass:
{
const char * suffix = "";
bool fold = reg_idx & IntFoldBit;
reg_idx &= ~IntFoldBit;
if (fold)
suffix = "h";
else if (reg_idx < 8 && size == 1)
suffix = "l";
if (fold)
suffix = "h";
else if (reg_idx < 8 && size == 1)
suffix = "l";
switch (reg_idx) {
case INTREG_RAX:
ccprintf(os, abcdFormats[size], "a");
break;
case INTREG_RBX:
ccprintf(os, abcdFormats[size], "b");
break;
case INTREG_RCX:
ccprintf(os, abcdFormats[size], "c");
break;
case INTREG_RDX:
ccprintf(os, abcdFormats[size], "d");
break;
case INTREG_RSP:
ccprintf(os, piFormats[size], "sp");
break;
case INTREG_RBP:
ccprintf(os, piFormats[size], "bp");
break;
case INTREG_RSI:
ccprintf(os, piFormats[size], "si");
break;
case INTREG_RDI:
ccprintf(os, piFormats[size], "di");
break;
case INTREG_R8W:
ccprintf(os, longFormats[size], "8");
break;
case INTREG_R9W:
ccprintf(os, longFormats[size], "9");
break;
case INTREG_R10W:
ccprintf(os, longFormats[size], "10");
break;
case INTREG_R11W:
ccprintf(os, longFormats[size], "11");
break;
case INTREG_R12W:
ccprintf(os, longFormats[size], "12");
break;
case INTREG_R13W:
ccprintf(os, longFormats[size], "13");
break;
case INTREG_R14W:
ccprintf(os, longFormats[size], "14");
break;
case INTREG_R15W:
ccprintf(os, longFormats[size], "15");
break;
default:
ccprintf(os, microFormats[size], reg_idx - NUM_INTREGS);
switch (reg_idx) {
case INTREG_RAX:
ccprintf(os, abcdFormats[size], "a");
break;
case INTREG_RBX:
ccprintf(os, abcdFormats[size], "b");
break;
case INTREG_RCX:
ccprintf(os, abcdFormats[size], "c");
break;
case INTREG_RDX:
ccprintf(os, abcdFormats[size], "d");
break;
case INTREG_RSP:
ccprintf(os, piFormats[size], "sp");
break;
case INTREG_RBP:
ccprintf(os, piFormats[size], "bp");
break;
case INTREG_RSI:
ccprintf(os, piFormats[size], "si");
break;
case INTREG_RDI:
ccprintf(os, piFormats[size], "di");
break;
case INTREG_R8W:
ccprintf(os, longFormats[size], "8");
break;
case INTREG_R9W:
ccprintf(os, longFormats[size], "9");
break;
case INTREG_R10W:
ccprintf(os, longFormats[size], "10");
break;
case INTREG_R11W:
ccprintf(os, longFormats[size], "11");
break;
case INTREG_R12W:
ccprintf(os, longFormats[size], "12");
break;
case INTREG_R13W:
ccprintf(os, longFormats[size], "13");
break;
case INTREG_R14W:
ccprintf(os, longFormats[size], "14");
break;
case INTREG_R15W:
ccprintf(os, longFormats[size], "15");
break;
default:
ccprintf(os, microFormats[size], reg_idx - NUM_INTREGS);
}
ccprintf(os, suffix);
}
ccprintf(os, suffix);
} else if (reg.isFloatReg()) {
break;
case FloatRegClass:
if (reg_idx < NumMMXRegs) {
ccprintf(os, "%%mmx%d", reg_idx);
return;
@@ -232,15 +235,18 @@ X86StaticInst::printReg(std::ostream &os, RegId reg, int size)
}
reg_idx -= NumMicroFpRegs;
ccprintf(os, "%%st(%d)", reg_idx);
} else if (reg.isCCReg()) {
break;
case CCRegClass:
ccprintf(os, "%%cc%d", reg_idx);
} else if (reg.isMiscReg()) {
break;
case MiscRegClass:
switch (reg_idx) {
default:
ccprintf(os, "%%ctrl%d", reg_idx);
}
break;
default:
panic("Unrecognized register class.");
}
}

30
src/cpu/checker/cpu.hh
View File

@@ -182,7 +182,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
readIntRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isIntReg());
assert(reg.is(IntRegClass));
return thread->readIntReg(reg.index());
}
@@ -190,7 +190,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
readFloatRegOperandBits(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isFloatReg());
assert(reg.is(FloatRegClass));
return thread->readFloatReg(reg.index());
}
@@ -201,7 +201,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
readVecRegOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isVecReg());
assert(reg.is(VecRegClass));
return thread->readVecReg(reg);
}
@@ -212,7 +212,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
getWritableVecRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
assert(reg.is(VecRegClass));
return thread->getWritableVecReg(reg);
}
@@ -227,7 +227,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
readVecPredRegOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isVecPredReg());
assert(reg.is(VecPredRegClass));
return thread->readVecPredReg(reg);
}
@@ -235,7 +235,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
getWritableVecPredRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecPredReg());
assert(reg.is(VecPredRegClass));
return thread->getWritableVecPredReg(reg);
}
@@ -243,7 +243,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
readCCRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isCCReg());
assert(reg.is(CCRegClass));
return thread->readCCReg(reg.index());
}
@@ -283,7 +283,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isIntReg());
assert(reg.is(IntRegClass));
thread->setIntReg(reg.index(), val);
setScalarResult(val);
}
@@ -292,7 +292,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isFloatReg());
assert(reg.is(FloatRegClass));
thread->setFloatReg(reg.index(), val);
setScalarResult(val);
}
@@ -301,7 +301,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isCCReg());
assert(reg.is(CCRegClass));
thread->setCCReg(reg.index(), val);
setScalarResult((uint64_t)val);
}
@@ -311,7 +311,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
const TheISA::VecRegContainer& val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
assert(reg.is(VecRegClass));
thread->setVecReg(reg, val);
setVecResult(val);
}
@@ -321,7 +321,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
const TheISA::VecElem val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecElem());
assert(reg.is(VecElemClass));
thread->setVecElem(reg, val);
setVecElemResult(val);
}
@@ -330,7 +330,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
const TheISA::VecPredRegContainer& val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecPredReg());
assert(reg.is(VecPredRegClass));
thread->setVecPredReg(reg, val);
setVecPredResult(val);
}
@@ -437,7 +437,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
readMiscRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isMiscReg());
assert(reg.is(MiscRegClass));
return thread->readMiscReg(reg.index());
}
@@ -445,7 +445,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isMiscReg());
assert(reg.is(MiscRegClass));
return this->setMiscReg(reg.index(), val);
}

32
src/cpu/minor/exec_context.hh
View File

@@ -144,7 +144,7 @@ class ExecContext : public ::ExecContext
readIntRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isIntReg());
assert(reg.is(IntRegClass));
return thread.readIntReg(reg.index());
}
@@ -152,7 +152,7 @@ class ExecContext : public ::ExecContext
readFloatRegOperandBits(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isFloatReg());
assert(reg.is(FloatRegClass));
return thread.readFloatReg(reg.index());
}
@@ -160,7 +160,7 @@ class ExecContext : public ::ExecContext
readVecRegOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isVecReg());
assert(reg.is(VecRegClass));
return thread.readVecReg(reg);
}
@@ -168,7 +168,7 @@ class ExecContext : public ::ExecContext
getWritableVecRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
assert(reg.is(VecRegClass));
return thread.getWritableVecReg(reg);
}
@@ -176,7 +176,7 @@ class ExecContext : public ::ExecContext
readVecElemOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isVecElem());
assert(reg.is(VecElemClass));
return thread.readVecElem(reg);
}
@@ -184,7 +184,7 @@ class ExecContext : public ::ExecContext
readVecPredRegOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isVecPredReg());
assert(reg.is(VecPredRegClass));
return thread.readVecPredReg(reg);
}
@@ -192,7 +192,7 @@ class ExecContext : public ::ExecContext
getWritableVecPredRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecPredReg());
assert(reg.is(VecPredRegClass));
return thread.getWritableVecPredReg(reg);
}
@@ -200,7 +200,7 @@ class ExecContext : public ::ExecContext
setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isIntReg());
assert(reg.is(IntRegClass));
thread.setIntReg(reg.index(), val);
}
@@ -208,7 +208,7 @@ class ExecContext : public ::ExecContext
setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isFloatReg());
assert(reg.is(FloatRegClass));
thread.setFloatReg(reg.index(), val);
}
@@ -217,7 +217,7 @@ class ExecContext : public ::ExecContext
const TheISA::VecRegContainer& val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
assert(reg.is(VecRegClass));
thread.setVecReg(reg, val);
}
@@ -226,7 +226,7 @@ class ExecContext : public ::ExecContext
const TheISA::VecPredRegContainer& val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecPredReg());
assert(reg.is(VecPredRegClass));
thread.setVecPredReg(reg, val);
}
@@ -235,7 +235,7 @@ class ExecContext : public ::ExecContext
const TheISA::VecElem val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecElem());
assert(reg.is(VecElemClass));
thread.setVecElem(reg, val);
}
@@ -330,7 +330,7 @@ class ExecContext : public ::ExecContext
readMiscRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isMiscReg());
assert(reg.is(MiscRegClass));
return thread.readMiscReg(reg.index());
}
@@ -338,7 +338,7 @@ class ExecContext : public ::ExecContext
setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isMiscReg());
assert(reg.is(MiscRegClass));
return thread.setMiscReg(reg.index(), val);
}
@@ -362,7 +362,7 @@ class ExecContext : public ::ExecContext
readCCRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isCCReg());
assert(reg.is(CCRegClass));
return thread.readCCReg(reg.index());
}
@@ -370,7 +370,7 @@ class ExecContext : public ::ExecContext
setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isCCReg());
assert(reg.is(CCRegClass));
thread.setCCReg(reg.index(), val);
}

4
src/cpu/o3/dyn_inst.hh
View File

@@ -1137,7 +1137,7 @@ class BaseO3DynInst : public ExecContext, public RefCounted
readMiscRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isMiscReg());
assert(reg.is(MiscRegClass));
return this->cpu->readMiscReg(reg.index(), this->threadNumber);
}
@@ -1148,7 +1148,7 @@ class BaseO3DynInst : public ExecContext, public RefCounted
setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isMiscReg());
assert(reg.is(MiscRegClass));
setMiscReg(reg.index(), val);
}

8
src/cpu/o3/probe/elastic_trace.cc
View File

@@ -244,8 +244,8 @@ ElasticTrace::updateRegDep(const DynInstConstPtr& dyn_inst)
for (int src_idx = 0; src_idx < max_regs; src_idx++) {
const RegId& src_reg = dyn_inst->srcRegIdx(src_idx);
if (!src_reg.isMiscReg() &&
!(src_reg.isIntReg() && src_reg.index() == zeroReg)) {
if (!src_reg.is(MiscRegClass) &&
!(src_reg.is(IntRegClass) && src_reg.index() == zeroReg)) {
// Get the physical register index of the i'th source register.
PhysRegIdPtr phys_src_reg = dyn_inst->regs.renamedSrcIdx(src_idx);
DPRINTFR(ElasticTrace, "[sn:%lli] Check map for src reg"
@@ -276,8 +276,8 @@ ElasticTrace::updateRegDep(const DynInstConstPtr& dyn_inst)
// For data dependency tracking the register must be an int, float or
// CC register and not a Misc register.
const RegId& dest_reg = dyn_inst->destRegIdx(dest_idx);
if (!dest_reg.isMiscReg() &&
!(dest_reg.isIntReg() && dest_reg.index() == zeroReg)) {
if (!dest_reg.is(MiscRegClass) &&
!(dest_reg.is(IntRegClass) && dest_reg.index() == zeroReg)) {
// Get the physical register index of the i'th destination
// register.
PhysRegIdPtr phys_dest_reg =

4
src/cpu/o3/regfile.cc
View File

@@ -182,7 +182,7 @@ PhysRegFile::initFreeList(UnifiedFreeList *freeList)
PhysRegFile::IdRange
PhysRegFile::getRegElemIds(PhysRegIdPtr reg)
{
panic_if(!reg->isVectorPhysReg(),
panic_if(!reg->is(VecRegClass),
"Trying to get elems of a %s register", reg->className());
auto idx = reg->index();
return std::make_pair(
@@ -225,7 +225,7 @@ PhysRegFile::getTrueId(PhysRegIdPtr reg)
return &vecElemIds[reg->index() * TheISA::NumVecElemPerVecReg +
reg->elemIndex()];
default:
panic_if(!reg->isVectorPhysElem(),
panic_if(!reg->is(VecElemClass),
"Trying to get the register of a %s register", reg->className());
}
return nullptr;

24
src/cpu/o3/regfile.hh
View File

@@ -178,7 +178,7 @@ class PhysRegFile
RegVal
readIntReg(PhysRegIdPtr phys_reg) const
{
assert(phys_reg->isIntPhysReg());
assert(phys_reg->is(IntRegClass));
DPRINTF(IEW, "RegFile: Access to int register %i, has data "
"%#x\n", phys_reg->index(), intRegFile[phys_reg->index()]);
@@ -188,7 +188,7 @@ class PhysRegFile
RegVal
readFloatReg(PhysRegIdPtr phys_reg) const
{
assert(phys_reg->isFloatPhysReg());
assert(phys_reg->is(FloatRegClass));
RegVal floatRegBits = floatRegFile[phys_reg->index()];
@@ -202,7 +202,7 @@ class PhysRegFile
const TheISA::VecRegContainer &
readVecReg(PhysRegIdPtr phys_reg) const
{
assert(phys_reg->isVectorPhysReg());
assert(phys_reg->is(VecRegClass));
DPRINTF(IEW, "RegFile: Access to vector register %i, has "
"data %s\n", int(phys_reg->index()),
@@ -223,7 +223,7 @@ class PhysRegFile
const TheISA::VecElem &
readVecElem(PhysRegIdPtr phys_reg) const
{
assert(phys_reg->isVectorPhysElem());
assert(phys_reg->is(VecElemClass));
auto ret = vectorRegFile[phys_reg->index()].as<TheISA::VecElem>();
const TheISA::VecElem& val = ret[phys_reg->elemIndex()];
DPRINTF(IEW, "RegFile: Access to element %d of vector register %i,"
@@ -237,7 +237,7 @@ class PhysRegFile
const TheISA::VecPredRegContainer&
readVecPredReg(PhysRegIdPtr phys_reg) const
{
assert(phys_reg->isVecPredPhysReg());
assert(phys_reg->is(VecPredRegClass));
DPRINTF(IEW, "RegFile: Access to predicate register %i, has "
"data %s\n", int(phys_reg->index()),
@@ -258,7 +258,7 @@ class PhysRegFile
RegVal
readCCReg(PhysRegIdPtr phys_reg)
{
assert(phys_reg->isCCPhysReg());
assert(phys_reg->is(CCRegClass));
DPRINTF(IEW, "RegFile: Access to cc register %i, has "
"data %#x\n", phys_reg->index(),
@@ -271,7 +271,7 @@ class PhysRegFile
void
setIntReg(PhysRegIdPtr phys_reg, RegVal val)
{
assert(phys_reg->isIntPhysReg());
assert(phys_reg->is(IntRegClass));
DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
phys_reg->index(), val);
@@ -283,7 +283,7 @@ class PhysRegFile
void
setFloatReg(PhysRegIdPtr phys_reg, RegVal val)
{
assert(phys_reg->isFloatPhysReg());
assert(phys_reg->is(FloatRegClass));
DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
phys_reg->index(), (uint64_t)val);
@@ -295,7 +295,7 @@ class PhysRegFile
void
setVecReg(PhysRegIdPtr phys_reg, const TheISA::VecRegContainer& val)
{
assert(phys_reg->isVectorPhysReg());
assert(phys_reg->is(VecRegClass));
DPRINTF(IEW, "RegFile: Setting vector register %i to %s\n",
int(phys_reg->index()), val);
@@ -307,7 +307,7 @@ class PhysRegFile
void
setVecElem(PhysRegIdPtr phys_reg, const TheISA::VecElem val)
{
assert(phys_reg->isVectorPhysElem());
assert(phys_reg->is(VecElemClass));
DPRINTF(IEW, "RegFile: Setting element %d of vector register %i to"
" %#x\n", phys_reg->elemIndex(), int(phys_reg->index()), val);
@@ -321,7 +321,7 @@ class PhysRegFile
setVecPredReg(PhysRegIdPtr phys_reg,
const TheISA::VecPredRegContainer& val)
{
assert(phys_reg->isVecPredPhysReg());
assert(phys_reg->is(VecPredRegClass));
DPRINTF(IEW, "RegFile: Setting predicate register %i to %s\n",
int(phys_reg->index()), val);
@@ -333,7 +333,7 @@ class PhysRegFile
void
setCCReg(PhysRegIdPtr phys_reg, RegVal val)
{
assert(phys_reg->isCCPhysReg());
assert(phys_reg->is(CCRegClass));
DPRINTF(IEW, "RegFile: Setting cc register %i to %#x\n",
phys_reg->index(), (uint64_t)val);

7
src/cpu/o3/rename_map.hh
View File

@@ -304,31 +304,26 @@ class UnifiedRenameMap
void
setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg)
{
assert(phys_reg->is(arch_reg.classValue()));
switch (arch_reg.classValue()) {
case IntRegClass:
assert(phys_reg->isIntPhysReg());
return intMap.setEntry(arch_reg, phys_reg);
case FloatRegClass:
assert(phys_reg->isFloatPhysReg());
return floatMap.setEntry(arch_reg, phys_reg);
case VecRegClass:
assert(phys_reg->isVectorPhysReg());
assert(vecMode == Enums::Full);
return vecMap.setEntry(arch_reg, phys_reg);
case VecElemClass:
assert(phys_reg->isVectorPhysElem());
assert(vecMode == Enums::Elem);
return vecElemMap.setEntry(arch_reg, phys_reg);
case VecPredRegClass:
assert(phys_reg->isVecPredPhysReg());
return predMap.setEntry(arch_reg, phys_reg);
case CCRegClass:
assert(phys_reg->isCCPhysReg());
return ccMap.setEntry(arch_reg, phys_reg);
case MiscRegClass:

4
src/cpu/o3/scoreboard.hh
View File

@@ -87,7 +87,7 @@ class Scoreboard
bool ready = regScoreBoard[phys_reg->flatIndex()];
if (phys_reg->isIntPhysReg() && phys_reg->index() == zeroReg)
if (phys_reg->is(IntRegClass) && phys_reg->index() == zeroReg)
assert(ready);
return ready;
@@ -124,7 +124,7 @@ class Scoreboard
}
// zero reg should never be marked unready
if (phys_reg->isIntPhysReg() && phys_reg->index() == zeroReg)
if (phys_reg->is(IntRegClass) && phys_reg->index() == zeroReg)
return;
regScoreBoard[phys_reg->flatIndex()] = false;

46
src/cpu/reg_class.hh
View File

@@ -149,26 +149,8 @@ class RegId
return regClass != MiscRegClass;
}
/** @return true if it is an integer physical register. */
bool isIntReg() const { return regClass == IntRegClass; }
/** @return true if it is a floating-point physical register. */
bool isFloatReg() const { return regClass == FloatRegClass; }
/** @Return true if it is a condition-code physical register. */
bool isVecReg() const { return regClass == VecRegClass; }
/** @Return true if it is a condition-code physical register. */
bool isVecElem() const { return regClass == VecElemClass; }
/** @Return true if it is a predicate physical register. */
bool isVecPredReg() const { return regClass == VecPredRegClass; }
/** @Return true if it is a condition-code physical register. */
bool isCCReg() const { return regClass == CCRegClass; }
/** @Return true if it is a condition-code physical register. */
bool isMiscReg() const { return regClass == MiscRegClass; }
/** @return true if it is of the specified class. */
bool is(RegClass reg_class) const { return regClass == reg_class; }
/** Index accessors */
/** @{ */
@@ -254,6 +236,7 @@ class PhysRegId : private RegId
using RegId::classValue;
using RegId::className;
using RegId::elemIndex;
using RegId::is;
/** @} */
/**
* Explicit forward methods, to prevent comparisons of PhysRegId with
@@ -279,27 +262,6 @@ class PhysRegId : private RegId
}
/** @} */
/** @return true if it is an integer physical register. */
bool isIntPhysReg() const { return isIntReg(); }
/** @return true if it is a floating-point physical register. */
bool isFloatPhysReg() const { return isFloatReg(); }
/** @Return true if it is a condition-code physical register. */
bool isCCPhysReg() const { return isCCReg(); }
/** @Return true if it is a vector physical register. */
bool isVectorPhysReg() const { return isVecReg(); }
/** @Return true if it is a vector element physical register. */
bool isVectorPhysElem() const { return isVecElem(); }
/** @return true if it is a vector predicate physical register. */
bool isVecPredPhysReg() const { return isVecPredReg(); }
/** @Return true if it is a condition-code physical register. */
bool isMiscPhysReg() const { return isMiscReg(); }
/**
* Returns true if this register is always associated to the same
* architectural register.
@@ -312,7 +274,7 @@ class PhysRegId : private RegId
static PhysRegId
elemId(PhysRegId* vid, ElemIndex elem)
{
assert(vid->isVectorPhysReg());
assert(vid->is(VecRegClass));
return PhysRegId(VecElemClass, vid->index(), elem);
}

32
src/cpu/simple/exec_context.hh
View File

@@ -277,7 +277,7 @@ class SimpleExecContext : public ExecContext
{
execContextStats.numIntRegReads++;
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isIntReg());
assert(reg.is(IntRegClass));
return thread->readIntReg(reg.index());
}
@@ -287,7 +287,7 @@ class SimpleExecContext : public ExecContext
{
execContextStats.numIntRegWrites++;
const RegId& reg = si->destRegIdx(idx);
assert(reg.isIntReg());
assert(reg.is(IntRegClass));
thread->setIntReg(reg.index(), val);
}
@@ -298,7 +298,7 @@ class SimpleExecContext : public ExecContext
{
execContextStats.numFpRegReads++;
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isFloatReg());
assert(reg.is(FloatRegClass));
return thread->readFloatReg(reg.index());
}
@@ -309,7 +309,7 @@ class SimpleExecContext : public ExecContext
{
execContextStats.numFpRegWrites++;
const RegId& reg = si->destRegIdx(idx);
assert(reg.isFloatReg());
assert(reg.is(FloatRegClass));
thread->setFloatReg(reg.index(), val);
}
@@ -319,7 +319,7 @@ class SimpleExecContext : public ExecContext
{
execContextStats.numVecRegReads++;
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isVecReg());
assert(reg.is(VecRegClass));
return thread->readVecReg(reg);
}
@@ -329,7 +329,7 @@ class SimpleExecContext : public ExecContext
{
execContextStats.numVecRegWrites++;
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
assert(reg.is(VecRegClass));
return thread->getWritableVecReg(reg);
}
@@ -340,7 +340,7 @@ class SimpleExecContext : public ExecContext
{
execContextStats.numVecRegWrites++;
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
assert(reg.is(VecRegClass));
thread->setVecReg(reg, val);
}
@@ -350,7 +350,7 @@ class SimpleExecContext : public ExecContext
{
execContextStats.numVecRegReads++;
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isVecElem());
assert(reg.is(VecElemClass));
return thread->readVecElem(reg);
}
@@ -361,7 +361,7 @@ class SimpleExecContext : public ExecContext
{
execContextStats.numVecRegWrites++;
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecElem());
assert(reg.is(VecElemClass));
thread->setVecElem(reg, val);
}
@@ -370,7 +370,7 @@ class SimpleExecContext : public ExecContext
{
execContextStats.numVecPredRegReads++;
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isVecPredReg());
assert(reg.is(VecPredRegClass));
return thread->readVecPredReg(reg);
}
@@ -379,7 +379,7 @@ class SimpleExecContext : public ExecContext
{
execContextStats.numVecPredRegWrites++;
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecPredReg());
assert(reg.is(VecPredRegClass));
return thread->getWritableVecPredReg(reg);
}
@@ -389,7 +389,7 @@ class SimpleExecContext : public ExecContext
{
execContextStats.numVecPredRegWrites++;
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecPredReg());
assert(reg.is(VecPredRegClass));
thread->setVecPredReg(reg, val);
}
@@ -398,7 +398,7 @@ class SimpleExecContext : public ExecContext
{
execContextStats.numCCRegReads++;
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isCCReg());
assert(reg.is(CCRegClass));
return thread->readCCReg(reg.index());
}
@@ -407,7 +407,7 @@ class SimpleExecContext : public ExecContext
{
execContextStats.numCCRegWrites++;
const RegId& reg = si->destRegIdx(idx);
assert(reg.isCCReg());
assert(reg.is(CCRegClass));
thread->setCCReg(reg.index(), val);
}
@@ -416,7 +416,7 @@ class SimpleExecContext : public ExecContext
{
execContextStats.numIntRegReads++;
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isMiscReg());
assert(reg.is(MiscRegClass));
return thread->readMiscReg(reg.index());
}
@@ -425,7 +425,7 @@ class SimpleExecContext : public ExecContext
{
execContextStats.numIntRegWrites++;
const RegId& reg = si->destRegIdx(idx);
assert(reg.isMiscReg());
assert(reg.is(MiscRegClass));
thread->setMiscReg(reg.index(), val);
}