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cpu: Use the built in << for VecReg and VecPredReg in ExeTrace.

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There's no reason to reimplement printing code when VecReg and
VecPredReg types already know how to print themselves.

Change-Id: I092c28143de286d765312122b81ce865a5184091
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42001
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Gabe Black
2021-02-26 21:24:47 -08:00
parent fa505b3e12
commit 86301ce456
1 changed files with 2 additions and 23 deletions
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25
src/cpu/exetrace.cc
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@@ -115,31 +115,10 @@ Trace::ExeTracerRecord::traceInst(const StaticInstPtr &inst, bool ran)
if (Debug::ExecResult && data_status != DataInvalid) {
switch (data_status) {
case DataVec:
{
ccprintf(outs, " D=0x[");
auto dv = data.as_vec->as<uint32_t>();
for (int i = TheISA::VecRegSizeBytes / 4 - 1; i >= 0;
i--) {
ccprintf(outs, "%08x", dv[i]);
if (i != 0) {
ccprintf(outs, "_");
}
}
ccprintf(outs, "]");
}
ccprintf(outs, " D=%s", *data.as_vec);
break;
case DataVecPred:
{
ccprintf(outs, " D=0b[");
auto pv = data.as_pred->as<uint8_t>();
for (int i = TheISA::VecPredRegSizeBits - 1; i >= 0; i--) {
ccprintf(outs, pv[i] ? "1" : "0");
if (i != 0 && i % 4 == 0) {
ccprintf(outs, "_");
}
}
ccprintf(outs, "]");
}
ccprintf(outs, " D=%s", *data.as_pred);
break;
default:
ccprintf(outs, " D=%#018x", data.as_int);