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misc: Fix remaining opening braces

Browse Source 
These were not caught by the previous patches because
the grep used ignored:
- anonymous structures
  (e.g., "struct {")
- opening braces without leading spaces
  (e.g., "struct Name{"),
- weird chars in auto-generation files
  (e.g., "struct $name {").
- extra characters after the opening brace.
  (e.g., "struct Name { // Comment")
- typedefs (note that this is not caught by the verifier)
  (e.g., "typedef struct Name {")

Most of this has been fixed be grepping structures
with the following regex:
  grep -nrE --exclude-dir=systemc \
    "^ *(typedef)* *(struct|class|enum|union) [^{]*{$" src/

The following makes sure that "struct{" is captured:
  grep -nrE --exclude-dir=systemc \
    "^ *(struct|class|enum|union){" src/

To find cases that contain a comment after the
opening brace:
  grep -nrE --exclude-dir=systemc \
    "^ *(struct|class|enum|union)[^{]*{\s*//" src/

Change-Id: I9f822bed628d13b1a09ccd6059373aff63a8d7bd
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43505
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Daniel R. Carvalho
2021-03-23 13:29:40 -03:00
committed by Daniel Carvalho
parent 5e24869079
commit 5c8983fc18
76 changed files with 584 additions and 277 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
src/arch/arm/freebsd/freebsd.hh
View File

@@ -124,7 +124,8 @@ class ArmFreebsd32 : public ArmFreebsd
* sizeof st_lspare 4
*/
typedef struct {
typedef struct
{
uint32_t st_dev;
uint32_t st_ino;
uint16_t st_mode;
@@ -148,7 +149,8 @@ class ArmFreebsd32 : public ArmFreebsd
uint64_t st_birthtim;
} tgt_stat;
typedef struct {
typedef struct
{
uint32_t st_dev;
uint32_t st_ino;
uint16_t st_mode;
@@ -295,7 +297,8 @@ class ArmFreebsd64 : public ArmFreebsd
uint64_t iov_len;
};
typedef struct {
typedef struct
{
uint32_t st_dev;
uint32_t st_ino;
uint16_t st_mode;
@@ -319,7 +322,8 @@ class ArmFreebsd64 : public ArmFreebsd
uint64_t st_birthtim;
} tgt_stat;
typedef struct {
typedef struct
{
uint32_t st_dev;
uint32_t st_ino;
uint16_t st_mode;

3
src/arch/arm/insts/static_inst.hh
View File

@@ -347,7 +347,8 @@ class ArmStaticInst : public StaticInst
cSwap(T val, bool big)
{
const unsigned count = sizeof(T) / sizeof(E);
union {
union
{
T tVal;
E eVals[count];
} conv;

5
src/arch/arm/isa/insts/neon64.isa
View File

@@ -3568,8 +3568,9 @@ let {{
for decoderFlavor, type_dict in decoders.items():
header_output += '''
class %(decoder_flavor)sDecoder {
public:
class %(decoder_flavor)sDecoder
{
public:
''' % { "decoder_flavor" : decoderFlavor }
for type,name in type_dict.items():
header_output += '''

6
src/arch/arm/kvm/armv8_cpu.cc
View File

@@ -83,12 +83,14 @@ kvmFPReg(const int num)
union KvmFPReg
{
union {
union
{
uint32_t i;
float f;
} s[4];
union {
union
{
uint64_t i;
double f;
} d[2];

6
src/arch/arm/linux/atag.hh
View File

@@ -43,7 +43,8 @@
#include "base/types.hh"
enum {
enum
{
CoreTag = 0x54410001,
MemTag = 0x54410002,
RevTag = 0x54410007,
@@ -277,7 +278,8 @@ struct atag_cmdline
struct atag
{
struct atag_header hdr;
union {
union
{
struct atag_core core;
struct atag_mem mem;
struct atag_videotext videotext;

18
src/arch/arm/linux/linux.hh
View File

@@ -193,7 +193,8 @@ class ArmLinux32 : public ArmLinux
};
typedef struct {
typedef struct
{
uint32_t st_dev;
uint32_t st_ino;
uint16_t st_mode;
@@ -214,7 +215,8 @@ class ArmLinux32 : public ArmLinux
uint32_t st_ctime_nsec;
} tgt_stat;
typedef struct {
typedef struct
{
uint64_t st_dev;
uint8_t __pad0[4];
uint32_t __st_ino;
@@ -236,7 +238,8 @@ class ArmLinux32 : public ArmLinux
uint64_t st_ino;
} tgt_stat64;
typedef struct {
typedef struct
{
int32_t uptime; /* Seconds since boot */
uint32_t loads[3]; /* 1, 5, and 15 minute load averages */
uint32_t totalram; /* Total usable main memory size */
@@ -459,7 +462,8 @@ class ArmLinux64 : public ArmLinux
uint64_t iov_len;
};
typedef struct {
typedef struct
{
uint64_t st_dev;
uint64_t st_ino;
uint64_t st_nlink;
@@ -479,7 +483,8 @@ class ArmLinux64 : public ArmLinux
uint64_t st_ctime_nsec;
} tgt_stat;
typedef struct {
typedef struct
{
uint64_t st_dev;
uint64_t st_ino;
uint32_t st_mode;
@@ -499,7 +504,8 @@ class ArmLinux64 : public ArmLinux
uint64_t st_ctime_nsec;
} tgt_stat64;
typedef struct {
typedef struct
{
int64_t uptime; /* Seconds since boot */
uint64_t loads[3]; /* 1, 5, and 15 minute load averages */
uint64_t totalram; /* Total usable main memory size */

4
src/arch/arm/semihosting.hh
View File

@@ -72,8 +72,8 @@ class SerialDevice;
class ArmSemihosting : public SimObject
{
public:
enum {
enum
{
// Standard ARM immediate values which trigger semihosting.
T32Imm = 0xAB,
A32Imm = 0x123456,

3
src/arch/arm/table_walker.hh
View File

@@ -769,7 +769,8 @@ class TableWalker : public ClockedObject
CPSR cpsr;
/** Cached copy of ttbcr/tcr as it existed when translation began */
union {
union
{
TTBCR ttbcr; // AArch32 translations
TCR tcr; // AArch64 translations
};

6
src/arch/arm/types.hh
View File

@@ -590,7 +590,8 @@ namespace ArmISA
typedef int RegContextVal;
//used in FP convert & round function
enum ConvertType{
enum ConvertType
{
SINGLE_TO_DOUBLE,
SINGLE_TO_WORD,
SINGLE_TO_LONG,
@@ -614,7 +615,8 @@ namespace ArmISA
};
//used in FP convert & round function
enum RoundMode{
enum RoundMode
{
RND_ZERO,
RND_DOWN,
RND_UP,

12
src/arch/mips/dsp.hh
View File

@@ -38,7 +38,8 @@ class ThreadContext;
namespace MipsISA {
// SIMD formats
enum {
enum
{
SIMD_FMT_L, // long word
SIMD_FMT_W, // word
SIMD_FMT_PH, // paired halfword
@@ -47,7 +48,8 @@ enum {
};
// DSPControl Fields
enum {
enum
{
DSP_POS, // insertion bitfield position
DSP_SCOUNT, // insertion bitfield size
DSP_C, // carry bit
@@ -58,14 +60,16 @@ enum {
};
// compare instruction operations
enum {
enum
{
CMP_EQ, // equal
CMP_LT, // less than
CMP_LE // less than or equal
};
// SIMD operation order modes
enum {
enum
{
MODE_L, // left
MODE_R, // right
MODE_LA, // left-alternate

3
src/arch/mips/linux/linux.hh
View File

@@ -179,7 +179,8 @@ class MipsLinux : public Linux
/// the root users.
static const int NUM_ROOT_PROCS = 2;
typedef struct {
typedef struct
{
int32_t uptime; /* Seconds since boot */
uint32_t loads[3]; /* 1, 5, and 15 minute load averages */
uint32_t totalram; /* Total usable main memory size */

3
src/arch/mips/remote_gdb.hh
View File

@@ -49,7 +49,8 @@ class RemoteGDB : public BaseRemoteGDB
{
using BaseGdbRegCache::BaseGdbRegCache;
private:
struct {
struct
{
uint32_t gpr[32];
uint32_t sr;
uint32_t lo;

6
src/arch/mips/types.hh
View File

@@ -41,7 +41,8 @@ typedef uint64_t ExtMachInst;
typedef GenericISA::DelaySlotPCState<MachInst> PCState;
//used in FP convert & round function
enum ConvertType{
enum ConvertType
{
SINGLE_TO_DOUBLE,
SINGLE_TO_WORD,
SINGLE_TO_LONG,
@@ -65,7 +66,8 @@ enum ConvertType{
};
//used in FP convert & round function
enum RoundMode{
enum RoundMode
{
RND_ZERO,
RND_DOWN,
RND_UP,

6
src/arch/power/linux/linux.hh
View File

@@ -44,7 +44,8 @@ class PowerLinux : public Linux
typedef int32_t time_t;
typedef struct {
typedef struct
{
uint64_t st_dev;
uint32_t __pad1;
uint32_t st_ino;
@@ -67,7 +68,8 @@ class PowerLinux : public Linux
uint32_t __unused5;
} tgt_stat;
typedef struct {
typedef struct
{
uint64_t st_dev;
uint64_t st_ino;
uint32_t st_mode;

3
src/arch/power/remote_gdb.hh
View File

@@ -49,7 +49,8 @@ class RemoteGDB : public BaseRemoteGDB
{
using BaseGdbRegCache::BaseGdbRegCache;
private:
struct {
struct
{
uint32_t gpr[NumIntArchRegs];
uint64_t fpr[NumFloatArchRegs];
uint32_t pc;

24
src/arch/riscv/linux/linux.hh
View File

@@ -138,7 +138,8 @@ class RiscvLinux64 : public RiscvLinux
int64_t tv_nsec;
};
typedef struct {
typedef struct
{
dev_t st_dev;
ino_t st_ino;
mode_t st_mode;
@@ -159,11 +160,13 @@ class RiscvLinux64 : public RiscvLinux
int32_t ___glibc_reserved[2];
} tgt_stat64;
typedef struct {
typedef struct
{
int32_t val[2];
} tgt_fsid_t;
typedef struct {
typedef struct
{
uint64_t f_type;
uint64_t f_bsize;
uint64_t f_blocks;
@@ -178,7 +181,8 @@ class RiscvLinux64 : public RiscvLinux
uint64_t f_spare[4];
} tgt_statfs;
typedef struct {
typedef struct
{
int64_t uptime;
uint64_t loads[3];
uint64_t totalram;
@@ -310,11 +314,13 @@ class RiscvLinux32 : public RiscvLinux
int32_t tv_nsec;
};
typedef struct {
typedef struct
{
int32_t val[2];
} tgt_fsid_t;
typedef struct {
typedef struct
{
uint64_t st_dev;
uint64_t st_ino;
uint32_t st_mode;
@@ -337,7 +343,8 @@ class RiscvLinux32 : public RiscvLinux
int32_t __unused5;
} tgt_stat;
typedef struct {
typedef struct
{
uint32_t f_type;
uint32_t f_bsize;
uint32_t f_blocks;
@@ -352,7 +359,8 @@ class RiscvLinux32 : public RiscvLinux
uint32_t f_spare[4];
} tgt_statfs;
typedef struct {
typedef struct
{
int32_t uptime;
uint32_t loads[3];
uint32_t totalram;

3
src/arch/riscv/remote_gdb.hh
View File

@@ -66,7 +66,8 @@ class RemoteGDB : public BaseRemoteGDB
* 2. Add register to struct below
* 3. Modify RiscvGdbRegCache::getRegs and setRegs
*/
struct {
struct
{
uint64_t gpr[NumIntArchRegs];
uint64_t pc;
uint64_t fpu[NumFloatRegs];

5
src/arch/riscv/tlb.hh
View File

@@ -53,7 +53,7 @@ namespace RiscvISA {
class Walker;
class TLB : public BaseTLB
{
{
typedef std::list<TlbEntry *> EntryList;
protected:
@@ -65,7 +65,8 @@ class TLB : public BaseTLB
Walker *walker;
struct TlbStats : public Stats::Group{
struct TlbStats : public Stats::Group
{
TlbStats(Stats::Group *parent);
Stats::Scalar readHits;

9
src/arch/sparc/linux/linux.hh
View File

@@ -168,7 +168,8 @@ class SparcLinux : public Linux
static const unsigned NUM_MMAP_FLAGS;
typedef struct {
typedef struct
{
int64_t uptime; /* Seconds since boot */
uint64_t loads[3]; /* 1, 5, and 15 minute load averages */
uint64_t totalram; /* Total usable main memory size */
@@ -245,7 +246,8 @@ class Sparc32Linux : public SparcLinux
{
public:
typedef struct {
typedef struct
{
uint64_t st_dev;
uint64_t st_ino;
uint32_t st_mode;
@@ -268,7 +270,8 @@ class Sparc32Linux : public SparcLinux
uint32_t __unused5;
} tgt_stat64;
typedef struct {
typedef struct
{
int32_t uptime; /* Seconds since boot */
uint32_t loads[3]; /* 1, 5, and 15 minute load averages */
uint32_t totalram; /* Total usable main memory size */

6
src/arch/sparc/remote_gdb.hh
View File

@@ -49,7 +49,8 @@ class RemoteGDB : public BaseRemoteGDB
{
using BaseGdbRegCache::BaseGdbRegCache;
private:
struct {
struct
{
uint32_t gpr[32];
uint32_t hole[32];
uint32_t y;
@@ -77,7 +78,8 @@ class RemoteGDB : public BaseRemoteGDB
{
using BaseGdbRegCache::BaseGdbRegCache;
private:
struct {
struct
{
uint64_t gpr[32];
uint64_t fpr[32];
uint64_t pc;

22
src/arch/x86/linux/linux.hh
View File

@@ -92,7 +92,8 @@ class X86Linux64 : public X86Linux
{
public:
typedef struct {
typedef struct
{
uint64_t st_dev;
uint64_t st_ino;
uint64_t st_nlink;
@@ -113,11 +114,13 @@ class X86Linux64 : public X86Linux
int64_t unused0[3];
} tgt_stat64;
typedef struct {
typedef struct
{
long val[2];
} tgt_fsid;
typedef struct {
typedef struct
{
long f_type;
long f_bsize;
long f_blocks;
@@ -217,12 +220,14 @@ class X86Linux64 : public X86Linux
static const unsigned NUM_MMAP_FLAGS;
typedef struct {
typedef struct
{
uint64_t iov_base; // void *
uint64_t iov_len; // size_t
} tgt_iovec;
typedef struct {
typedef struct
{
int64_t uptime; /* Seconds since boot */
uint64_t loads[3]; /* 1, 5, and 15 minute load averages */
uint64_t totalram; /* Total usable main memory size */
@@ -242,8 +247,8 @@ class X86Linux64 : public X86Linux
class X86Linux32 : public X86Linux
{
public:
typedef struct M5_ATTR_PACKED {
typedef struct M5_ATTR_PACKED
{
uint64_t st_dev;
uint8_t __pad0[4];
uint32_t __st_ino;
@@ -353,7 +358,8 @@ class X86Linux32 : public X86Linux
static const unsigned NUM_MMAP_FLAGS;
typedef struct {
typedef struct
{
int32_t uptime; /* Seconds since boot */
uint32_t loads[3]; /* 1, 5, and 15 minute load averages */
uint32_t totalram; /* Total usable main memory size */

6
src/arch/x86/process.cc
View File

@@ -412,7 +412,8 @@ X86_64Process::initState()
/* Set up the content of the TSS and write it to physical memory. */
struct {
struct
{
uint32_t reserved0; // +00h
uint32_t RSP0_low; // +04h
uint32_t RSP0_high; // +08h
@@ -467,7 +468,8 @@ X86_64Process::initState()
GateDescriptorHigh PFGateHigh = 0;
PFGateHigh.offset = bits(PFHandlerVirtAddr, 63, 32);
struct {
struct
{
uint64_t low;
uint64_t high;
} PFGate = {PFGateLow, PFGateHigh};

3
src/arch/x86/remote_gdb.hh
View File

@@ -59,7 +59,8 @@ class RemoteGDB : public BaseRemoteGDB
{
using BaseGdbRegCache::BaseGdbRegCache;
private:
struct {
struct
{
uint32_t eax;
uint32_t ecx;
uint32_t edx;

3
src/base/inet.hh
View File

@@ -576,7 +576,8 @@ struct M5_ATTR_PACKED ip6_opt_hdr
{
uint8_t ext_nxt;
uint8_t ext_len;
union {
union
{
struct ip6_opt_fragment fragment;
struct ip6_opt_routing_type2 rtType2;
struct ip6_opt_dstopts dstOpts;

3
src/base/stats/text.cc
View File

@@ -78,7 +78,8 @@ float __nan();
float
__nan()
{
union {
union
{
uint32_t ui;
float f;
} nan;

9
src/cpu/kvm/x86_cpu.cc
View File

@@ -75,8 +75,10 @@ struct M5_ATTR_PACKED FXSave
uint8_t ftwx;
uint8_t pad0;
uint16_t last_opcode;
union {
struct {
union
{
struct
{
uint32_t fpu_ip;
uint16_t fpu_cs;
uint16_t pad1;
@@ -85,7 +87,8 @@ struct M5_ATTR_PACKED FXSave
uint16_t pad2;
} ctrl32;
struct {
struct
{
uint64_t fpu_ip;
uint64_t fpu_dp;
} ctrl64;

3
src/cpu/o3/commit.hh
View File

@@ -102,7 +102,8 @@ class DefaultCommit
/** Overall commit status. Used to determine if the CPU can deschedule
* itself due to a lack of activity.
*/
enum CommitStatus{
enum CommitStatus
{
Active,
Inactive
};

3
src/cpu/o3/impl.hh
View File

@@ -70,7 +70,8 @@ struct O3CPUImpl
*/
typedef O3CPU CPUType;
enum {
enum
{
MaxWidth = 8,
MaxThreads = 4
};

3
src/cpu/o3/lsq_unit.hh
View File

@@ -566,7 +566,8 @@ class LSQUnit
// Will also need how many read/write ports the Dcache has. Or keep track
// of that in stage that is one level up, and only call executeLoad/Store
// the appropriate number of times.
struct LSQUnitStats : public Stats::Group{
struct LSQUnitStats : public Stats::Group
{
LSQUnitStats(Stats::Group *parent);
/** Total number of loads forwaded from LSQ stores. */

3
src/cpu/pred/ltage.hh
View File

@@ -75,7 +75,8 @@ class LTAGE : public TAGE
LoopPredictor *loopPredictor;
// more provider types
enum {
enum
{
LOOP = TAGEBase::LAST_TAGE_PROVIDER_TYPE + 1,
LAST_LTAGE_PROVIDER_TYPE = LOOP
};

3
src/cpu/pred/tage_base.hh
View File

@@ -108,7 +108,8 @@ class TAGEBase : public SimObject
public:
// provider type
enum {
enum
{
BIMODAL_ONLY = 0,
TAGE_LONGEST_MATCH,
BIMODAL_ALT_MATCH,

3
src/cpu/pred/tage_sc_l.hh
View File

@@ -178,7 +178,8 @@ class TAGE_SC_L: public LTAGE
};
// more provider types
enum {
enum
{
SC = LAST_LTAGE_PROVIDER_TYPE + 1
};

3
src/dev/arm/a9scu.hh
View File

@@ -48,7 +48,8 @@
class A9SCU : public BasicPioDevice
{
protected:
enum {
enum
{
Control = 0x00,
Config = 0x04,
};

6
src/dev/arm/gic_v2.hh
View File

@@ -60,7 +60,8 @@ class GicV2 : public BaseGic, public BaseGicRegisters
{
protected:
// distributor memory addresses
enum {
enum
{
GICD_CTLR = 0x000, // control register
GICD_TYPER = 0x004, // controller type
GICD_IIDR = 0x008, // implementer id
@@ -89,7 +90,8 @@ class GicV2 : public BaseGic, public BaseGicRegisters
static const AddrRange GICD_ICFGR; // interrupt config registers
// cpu memory addresses
enum {
enum
{
GICC_CTLR = 0x00, // CPU control register
GICC_PMR = 0x04, // Interrupt priority mask
GICC_BPR = 0x08, // binary point register

9
src/dev/arm/gic_v3.hh
View File

@@ -78,7 +78,8 @@ class Gicv3 : public BaseGic
static const int PPI_MAX = 16;
// Interrupt states for PPIs, SGIs and SPIs, as per SPEC 4.1.2 section
typedef enum {
typedef enum
{
INT_INACTIVE,
INT_PENDING,
INT_ACTIVE,
@@ -86,13 +87,15 @@ class Gicv3 : public BaseGic
} IntStatus;
// Interrupt groups, as per SPEC section 4.6
typedef enum {
typedef enum
{
G0S,
G1S,
G1NS,
} GroupId;
typedef enum {
typedef enum
{
INT_LEVEL_SENSITIVE,
INT_EDGE_TRIGGERED,
} IntTriggerType;

9
src/dev/arm/gic_v3_cpu_interface.hh
View File

@@ -151,7 +151,8 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
static const uint8_t GIC_MIN_VBPR = 7 - VIRTUAL_PREEMPTION_BITS;
typedef struct {
typedef struct
{
uint32_t intid;
uint8_t prio;
Gicv3::GroupId group;
@@ -160,7 +161,8 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
hppi_t hppi;
// GIC CPU interface memory mapped control registers (legacy)
enum {
enum
{
GICC_CTLR = 0x0000,
GICC_PMR = 0x0004,
GICC_BPR = 0x0008,
@@ -180,7 +182,8 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
static const AddrRange GICC_NSAPR;
// GIC CPU virtual interface memory mapped control registers (legacy)
enum {
enum
{
GICH_HCR = 0x0000,
GICH_VTR = 0x0004,
GICH_VMCR = 0x0008,

3
src/dev/arm/gic_v3_distributor.hh
View File

@@ -58,7 +58,8 @@ class Gicv3Distributor : public Serializable
Gicv3 * gic;
const uint32_t itLines;
enum {
enum
{
// Control Register
GICD_CTLR = 0x0000,
// Interrupt Controller Type Register

9
src/dev/arm/gic_v3_redistributor.hh
View File

@@ -72,7 +72,8 @@ class Gicv3Redistributor : public Serializable
static const uint32_t RD_base = 0x0;
static const uint32_t SGI_base = 0x10000;
enum {
enum
{
// Control Register
GICR_CTLR = RD_base + 0x0000,
// Implementer Identification Register
@@ -104,7 +105,8 @@ class Gicv3Redistributor : public Serializable
bool peInLowPowerState;
enum {
enum
{
// Interrupt Group Register 0
GICR_IGROUPR0 = SGI_base + 0x0080,
// Interrupt Set-Enable Register 0
@@ -133,7 +135,8 @@ class Gicv3Redistributor : public Serializable
static const AddrRange GICR_IPRIORITYR;
// GIC physical LPI Redistributor register
enum {
enum
{
// Set LPI Pending Register
GICR_SETLPIR = RD_base + 0x0040,
// Clear LPI Pending Register

3
src/dev/arm/rtc_pl031.hh
View File

@@ -48,7 +48,8 @@
class PL031 : public AmbaIntDevice
{
protected:
enum {
enum
{
DataReg = 0x00,
MatchReg = 0x04,
LoadReg = 0x08,

3
src/dev/arm/rv_ctrl.hh
View File

@@ -83,7 +83,8 @@ class RealViewCtrl : public BasicPioDevice
};
protected:
enum {
enum
{
IdReg = 0x00,
SwReg = 0x04,
Led = 0x08,

3
src/dev/arm/smmu_v3_caches.hh
View File

@@ -51,7 +51,8 @@
#define WALK_CACHE_LEVELS 4
enum {
enum
{
SMMU_CACHE_REPL_ROUND_ROBIN,
SMMU_CACHE_REPL_RANDOM,
SMMU_CACHE_REPL_LRU,

24
src/dev/arm/smmu_v3_defs.hh
View File

@@ -42,14 +42,16 @@
#include "base/bitunion.hh"
enum {
enum
{
SMMU_SECURE_SZ = 0x184, // Secure regs are within page0
SMMU_PAGE_ZERO_SZ = 0x10000,
SMMU_PAGE_ONE_SZ = 0x10000,
SMMU_REG_SIZE = SMMU_PAGE_ONE_SZ + SMMU_PAGE_ZERO_SZ
};
enum {
enum
{
STE_CONFIG_ABORT = 0x0,
STE_CONFIG_BYPASS = 0x4,
STE_CONFIG_STAGE1_ONLY = 0x5,
@@ -57,27 +59,31 @@ enum {
STE_CONFIG_STAGE1_AND_2 = 0x7,
};
enum {
enum
{
STAGE1_CFG_1L = 0x0,
STAGE1_CFG_2L_4K = 0x1,
STAGE1_CFG_2L_64K = 0x2,
};
enum {
enum
{
ST_CFG_SPLIT_SHIFT = 6,
ST_CD_ADDR_SHIFT = 6,
CD_TTB_SHIFT = 4,
STE_S2TTB_SHIFT = 4,
};
enum {
enum
{
TRANS_GRANULE_4K = 0x0,
TRANS_GRANULE_64K = 0x1,
TRANS_GRANULE_16K = 0x2,
TRANS_GRANULE_INVALID = 0x3,
};
enum {
enum
{
ST_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL,
ST_CFG_SIZE_MASK = 0x000000000000003fULL,
ST_CFG_SPLIT_MASK = 0x00000000000007c0ULL,
@@ -309,7 +315,8 @@ struct ContextDescriptor
uint64_t _pad[3];
};
enum {
enum
{
CR0_SMMUEN_MASK = 0x1,
CR0_PRIQEN_MASK = 0x2,
CR0_EVENTQEN_MASK = 0x4,
@@ -395,7 +402,8 @@ struct SMMUEvent
uint64_t ipa;
};
enum {
enum
{
SMMU_MAX_TRANS_ID = 64
};

3
src/dev/arm/timer_cpulocal.hh
View File

@@ -63,7 +63,8 @@ class CpuLocalTimer : public BasicPioDevice
{
public:
enum {
enum
{
TimerLoadReg = 0x00,
TimerCounterReg = 0x04,
TimerControlReg = 0x08,

3
src/dev/arm/timer_sp804.hh
View File

@@ -60,7 +60,8 @@ class Sp804 : public AmbaPioDevice
{
public:
enum {
enum
{
LoadReg = 0x00,
CurrentReg = 0x04,
ControlReg = 0x08,

6
src/dev/arm/vio_mmio.hh
View File

@@ -58,7 +58,8 @@ class MmioVirtIO : public BasicPioDevice
/** @{ */
/** Offsets into VirtIO MMIO space. */
enum : Addr {
enum : Addr
{
OFF_MAGIC = 0x00,
OFF_VERSION = 0x04,
OFF_DEVICE_ID = 0x08,
@@ -82,7 +83,8 @@ class MmioVirtIO : public BasicPioDevice
/** @} */
enum {
enum
{
INT_USED_RING = 1 << 0,
INT_CONFIG = 1 << 1,
};

191
src/dev/hsa/hsa.h
View File

@@ -115,7 +115,8 @@ extern "C" {
/**
* @brief Status codes.
*/
typedef enum {
typedef enum
{
/**
* The function has been executed successfully.
*/
@@ -289,7 +290,8 @@ hsa_status_t HSA_API hsa_status_string(
/**
* @brief Three-dimensional coordinate.
*/
typedef struct hsa_dim3_s {
typedef struct hsa_dim3_s
{
/**
* X dimension.
*/
@@ -309,7 +311,8 @@ typedef struct hsa_dim3_s {
/**
* @brief Access permissions.
*/
typedef enum {
typedef enum
{
/**
* Read-only access.
*/
@@ -387,7 +390,8 @@ hsa_status_t HSA_API hsa_shut_down();
* @brief Endianness. A convention used to interpret the bytes making up a data
* word.
*/
typedef enum {
typedef enum
{
/**
* The least significant byte is stored in the smallest address.
*/
@@ -402,7 +406,8 @@ typedef enum {
* @brief Machine model. A machine model determines the size of certain data
* types in HSA runtime and an agent.
*/
typedef enum {
typedef enum
{
/**
* Small machine model. Addresses use 32 bits.
*/
@@ -419,7 +424,8 @@ typedef enum {
* runtime allocator to reserve shared virtual memory, while in the full profile
* any host pointer can be shared across all the agents.
*/
typedef enum {
typedef enum
{
/**
* Base profile.
*/
@@ -433,7 +439,8 @@ typedef enum {
/**
* @brief System attributes.
*/
typedef enum {
typedef enum
{
/**
* Major version of the HSA runtime specification supported by the
* implementation. The type of this attribute is uint16_t.
@@ -500,7 +507,8 @@ hsa_status_t HSA_API hsa_system_get_info(
/**
* @brief HSA extensions.
*/
typedef enum {
typedef enum
{
/**
* Finalizer extension.
*/
@@ -708,7 +716,8 @@ hsa_status_t HSA_API hsa_system_get_major_extension_table(
* may also accept AQL packets for execution (agent dispatch packets or kernel
* dispatch packets launching HSAIL-derived binaries).
*/
typedef struct hsa_agent_s {
typedef struct hsa_agent_s
{
/**
* Opaque handle. Two handles reference the same object of the enclosing type
* if and only if they are equal.
@@ -719,7 +728,8 @@ typedef struct hsa_agent_s {
/**
* @brief Agent features.
*/
typedef enum {
typedef enum
{
/**
* The agent supports AQL packets of kernel dispatch type. If this
* feature is enabled, the agent is also a kernel agent.
@@ -734,7 +744,8 @@ typedef enum {
/**
* @brief Hardware device type.
*/
typedef enum {
typedef enum
{
/**
* CPU device.
*/
@@ -752,7 +763,8 @@ typedef enum {
/**
* @brief Default floating-point rounding mode.
*/
typedef enum {
typedef enum
{
/**
* Use a default floating-point rounding mode specified elsewhere.
*/
@@ -773,7 +785,8 @@ typedef enum {
/**
* @brief Agent attributes.
*/
typedef enum {
typedef enum
{
/**
* Agent name. The type of this attribute is a NUL-terminated char[64]. The
* name must be at most 63 characters long (not including the NUL terminator)
@@ -1062,7 +1075,8 @@ hsa_status_t HSA_API hsa_agent_set_info(
/**
* @brief Exception policies applied in the presence of hardware exceptions.
*/
typedef enum {
typedef enum
{
/**
* If a hardware exception is detected, a work-item signals an exception.
*/
@@ -1108,7 +1122,8 @@ hsa_status_t HSA_API HSA_DEPRECATED hsa_agent_get_exception_policies(
/**
* @brief Cache handle.
*/
typedef struct hsa_cache_s {
typedef struct hsa_cache_s
{
/**
* Opaque handle. Two handles reference the same object of the enclosing type
* if and only if they are equal.
@@ -1119,7 +1134,8 @@ typedef struct hsa_cache_s {
/**
* @brief Cache attributes.
*/
typedef enum {
typedef enum
{
/**
* The length of the cache name in bytes, not including the NUL terminator.
* The type of this attribute is uint32_t.
@@ -1284,7 +1300,8 @@ hsa_status_t HSA_API hsa_agent_major_extension_supported(
/**
* @brief Signal handle.
*/
typedef struct hsa_signal_s {
typedef struct hsa_signal_s
{
/**
* Opaque handle. Two handles reference the same object of the enclosing type
* if and only if they are equal. The value 0 is reserved.
@@ -1907,7 +1924,8 @@ void HSA_API HSA_DEPRECATED hsa_signal_xor_release(
/**
* @brief Wait condition operator.
*/
typedef enum {
typedef enum
{
/**
* The two operands are equal.
*/
@@ -1929,7 +1947,8 @@ typedef enum {
/**
* @brief State of the application thread during a signal wait.
*/
typedef enum {
typedef enum
{
/**
* The application thread may be rescheduled while waiting on the signal.
*/
@@ -2012,7 +2031,8 @@ hsa_signal_value_t HSA_API HSA_DEPRECATED hsa_signal_wait_acquire(
/**
* @brief Group of signals.
*/
typedef struct hsa_signal_group_s {
typedef struct hsa_signal_group_s
{
/**
* Opaque handle. Two handles reference the same object of the enclosing type
* if and only if they are equal.
@@ -2152,7 +2172,8 @@ hsa_status_t HSA_API hsa_signal_group_wait_any_relaxed(
* the global segment using a region. A region might be associated with more
* than one agent.
*/
typedef struct hsa_region_s {
typedef struct hsa_region_s
{
/**
* Opaque handle. Two handles reference the same object of the enclosing type
* if and only if they are equal.
@@ -2171,7 +2192,8 @@ typedef struct hsa_region_s {
* @brief Queue type. Intended to be used for dynamic queue protocol
* determination.
*/
typedef enum {
typedef enum
{
/**
* Queue supports multiple producers.
*/
@@ -2193,7 +2215,8 @@ typedef uint32_t hsa_queue_type32_t;
/**
* @brief Queue features.
*/
typedef enum {
typedef enum
{
/**
* Queue supports kernel dispatch packets.
*/
@@ -2213,7 +2236,8 @@ typedef enum {
* base_address, or use HSA runtime APIs to access the doorbell signal.
*
*/
typedef struct hsa_queue_s {
typedef struct hsa_queue_s
{
/**
* Queue type.
*/
@@ -2715,7 +2739,8 @@ void HSA_API hsa_queue_store_read_index_screlease(
/**
* @brief Packet type.
*/
typedef enum {
typedef enum
{
/**
* Vendor-specific packet.
*/
@@ -2753,7 +2778,8 @@ typedef enum {
/**
* @brief Scope of the memory fence operation associated with a packet.
*/
typedef enum {
typedef enum
{
/**
* No scope (no fence is applied). The packet relies on external fences to
* ensure visibility of memory updates.
@@ -2777,7 +2803,8 @@ typedef enum {
* determined by the corresponding value in ::hsa_packet_header_width_t. The
* offset and the width are expressed in bits.
*/
typedef enum {
typedef enum
{
/**
* Packet type. The value of this sub-field must be one of
* ::hsa_packet_type_t. If the type is ::HSA_PACKET_TYPE_VENDOR_SPECIFIC, the
@@ -2818,12 +2845,13 @@ typedef enum {
* @deprecated Renamed as ::HSA_PACKET_HEADER_SCRELEASE_FENCE_SCOPE.
*/
HSA_PACKET_HEADER_RELEASE_FENCE_SCOPE = 11
} hsa_packet_header_t;
} hsa_packet_header_t;
/**
* @brief Width (in bits) of the sub-fields in ::hsa_packet_header_t.
*/
typedef enum {
typedef enum
{
HSA_PACKET_HEADER_WIDTH_TYPE = 8,
HSA_PACKET_HEADER_WIDTH_BARRIER = 1,
HSA_PACKET_HEADER_WIDTH_SCACQUIRE_FENCE_SCOPE = 2,
@@ -2836,7 +2864,7 @@ typedef enum {
* @deprecated Use HSA_PACKET_HEADER_WIDTH_SCRELEASE_FENCE_SCOPE.
*/
HSA_PACKET_HEADER_WIDTH_RELEASE_FENCE_SCOPE = 2
} hsa_packet_header_width_t;
} hsa_packet_header_width_t;
/**
* @brief Sub-fields of the kernel dispatch packet @a setup field. The offset
@@ -2845,26 +2873,29 @@ typedef enum {
* corresponding value in ::hsa_kernel_dispatch_packet_setup_width_t. The
* offset and the width are expressed in bits.
*/
typedef enum {
typedef enum
{
/**
* Number of dimensions of the grid. Valid values are 1, 2, or 3.
*
*/
HSA_KERNEL_DISPATCH_PACKET_SETUP_DIMENSIONS = 0
} hsa_kernel_dispatch_packet_setup_t;
} hsa_kernel_dispatch_packet_setup_t;
/**
* @brief Width (in bits) of the sub-fields in
* ::hsa_kernel_dispatch_packet_setup_t.
*/
typedef enum {
typedef enum
{
HSA_KERNEL_DISPATCH_PACKET_SETUP_WIDTH_DIMENSIONS = 2
} hsa_kernel_dispatch_packet_setup_width_t;
} hsa_kernel_dispatch_packet_setup_width_t;
/**
* @brief AQL kernel dispatch packet
*/
typedef struct hsa_kernel_dispatch_packet_s {
typedef struct hsa_kernel_dispatch_packet_s
{
/**
* Packet header. Used to configure multiple packet parameters such as the
* packet type. The parameters are described by ::hsa_packet_header_t.
@@ -2975,7 +3006,8 @@ typedef struct hsa_kernel_dispatch_packet_s {
/**
* @brief Agent dispatch packet.
*/
typedef struct hsa_agent_dispatch_packet_s {
typedef struct hsa_agent_dispatch_packet_s
{
/**
* Packet header. Used to configure multiple packet parameters such as the
* packet type. The parameters are described by ::hsa_packet_header_t.
@@ -3029,7 +3061,8 @@ typedef struct hsa_agent_dispatch_packet_s {
/**
* @brief Barrier-AND packet.
*/
typedef struct hsa_barrier_and_packet_s {
typedef struct hsa_barrier_and_packet_s
{
/**
* Packet header. Used to configure multiple packet parameters such as the
* packet type. The parameters are described by ::hsa_packet_header_t.
@@ -3069,7 +3102,8 @@ typedef struct hsa_barrier_and_packet_s {
/**
* @brief Barrier-OR packet.
*/
typedef struct hsa_barrier_or_packet_s {
typedef struct hsa_barrier_or_packet_s
{
/**
* Packet header. Used to configure multiple packet parameters such as the
* packet type. The parameters are described by ::hsa_packet_header_t.
@@ -3115,7 +3149,8 @@ typedef struct hsa_barrier_or_packet_s {
/**
* @brief Memory segments associated with a region.
*/
typedef enum {
typedef enum
{
/**
* Global segment. Used to hold data that is shared by all agents.
*/
@@ -3143,7 +3178,8 @@ typedef enum {
/**
* @brief Global region flags.
*/
typedef enum {
typedef enum
{
/**
* The application can use memory in the region to store kernel arguments, and
* provide the values for the kernarg segment of a kernel dispatch. If this
@@ -3168,7 +3204,8 @@ typedef enum {
/**
* @brief Attributes of a memory region.
*/
typedef enum {
typedef enum
{
/**
* Segment where memory in the region can be used. The type of this
* attribute is ::hsa_region_segment_t.
@@ -3485,7 +3522,8 @@ hsa_status_t HSA_API hsa_memory_deregister(
/**
* @brief Instruction set architecture.
*/
typedef struct hsa_isa_s {
typedef struct hsa_isa_s
{
/**
* Opaque handle. Two handles reference the same object of the enclosing type
* if and only if they are equal.
@@ -3557,7 +3595,8 @@ hsa_status_t HSA_API hsa_agent_iterate_isas(
/**
* @brief Instruction set architecture attributes.
*/
typedef enum {
typedef enum
{
/**
* The length of the ISA name in bytes, not including the NUL terminator. The
* type of this attribute is uint32_t.
@@ -3767,7 +3806,8 @@ hsa_status_t HSA_API hsa_isa_get_exception_policies(
/**
* @brief Floating-point types.
*/
typedef enum {
typedef enum
{
/**
* 16-bit floating-point type.
*/
@@ -3785,7 +3825,8 @@ typedef enum {
/**
* @brief Flush to zero modes.
*/
typedef enum {
typedef enum
{
/**
* Flush to zero.
*/
@@ -3799,7 +3840,8 @@ typedef enum {
/**
* @brief Round methods.
*/
typedef enum {
typedef enum
{
/**
* Single round method.
*/
@@ -3846,7 +3888,8 @@ hsa_status_t HSA_API hsa_isa_get_round_method(
/**
* @brief Wavefront handle
*/
typedef struct hsa_wavefront_s {
typedef struct hsa_wavefront_s
{
/**
* Opaque handle. Two handles reference the same object of the enclosing type
* if and only if they are equal.
@@ -3857,7 +3900,8 @@ typedef struct hsa_wavefront_s {
/**
* @brief Wavefront attributes.
*/
typedef enum {
typedef enum
{
/**
* Number of work-items in the wavefront. Must be a power of 2 in the range
* [1,256]. The type of this attribute is uint32_t.
@@ -3965,7 +4009,8 @@ hsa_status_t HSA_API HSA_DEPRECATED hsa_isa_compatible(
* ::hsa_code_object_reader_create_from_file), or from memory (if created using
* ::hsa_code_object_reader_create_from_memory).
*/
typedef struct hsa_code_object_reader_s {
typedef struct hsa_code_object_reader_s
{
/**
* Opaque handle. Two handles reference the same object of the enclosing type
* if and only if they are equal.
@@ -4056,7 +4101,8 @@ hsa_status_t HSA_API hsa_code_object_reader_destroy(
* ISA for finalized kernels and indirect functions together with the allocated
* global or readonly segment variables they reference.
*/
typedef struct hsa_executable_s {
typedef struct hsa_executable_s
{
/**
* Opaque handle. Two handles reference the same object of the enclosing type
* if and only if they are equal.
@@ -4067,7 +4113,8 @@ typedef struct hsa_executable_s {
/**
* @brief Executable state.
*/
typedef enum {
typedef enum
{
/**
* Executable state, which allows the user to load code objects and define
* external variables. Variable addresses, kernel code handles, and
@@ -4186,7 +4233,8 @@ hsa_status_t HSA_API hsa_executable_destroy(
/**
* @brief Loaded code object handle.
*/
typedef struct hsa_loaded_code_object_s {
typedef struct hsa_loaded_code_object_s
{
/**
* Opaque handle. Two handles reference the same object of the enclosing type
* if and only if they are equal.
@@ -4347,7 +4395,8 @@ hsa_status_t HSA_API hsa_executable_freeze(
/**
* @brief Executable attributes.
*/
typedef enum {
typedef enum
{
/**
* Profile this executable is created for. The type of this attribute is
* ::hsa_profile_t.
@@ -4598,7 +4647,8 @@ hsa_status_t HSA_API hsa_executable_validate_alt(
* associated with it. An operation on a symbol whose associated executable has
* been destroyed results in undefined behavior.
*/
typedef struct hsa_executable_symbol_s {
typedef struct hsa_executable_symbol_s
{
/**
* Opaque handle. Two handles reference the same object of the enclosing type
* if and only if they are equal.
@@ -4687,7 +4737,8 @@ hsa_status_t HSA_API hsa_executable_get_symbol_by_name(
/**
* @brief Symbol type.
*/
typedef enum {
typedef enum
{
/**
* Variable.
*/
@@ -4705,7 +4756,8 @@ typedef enum {
/**
* @brief Linkage type of a symbol.
*/
typedef enum {
typedef enum
{
/**
* Module linkage.
*/
@@ -4719,7 +4771,8 @@ typedef enum {
/**
* @brief Allocation type of a variable.
*/
typedef enum {
typedef enum
{
/**
* Agent allocation.
*/
@@ -4733,7 +4786,8 @@ typedef enum {
/**
* @brief Memory segment associated with a variable.
*/
typedef enum {
typedef enum
{
/**
* Global memory segment.
*/
@@ -4747,7 +4801,8 @@ typedef enum {
/**
* @brief Executable symbol attributes.
*/
typedef enum {
typedef enum
{
/**
* The kind of the symbol. The type of this attribute is ::hsa_symbol_kind_t.
*/
@@ -5075,7 +5130,8 @@ hsa_status_t HSA_API hsa_executable_iterate_program_symbols(
* ISA for finalized kernels and indirect functions together with information
* about the global or readonly segment variables they reference.
*/
typedef struct hsa_code_object_s {
typedef struct hsa_code_object_s
{
/**
* Opaque handle. Two handles reference the same object of the enclosing type
* if and only if they are equal.
@@ -5089,7 +5145,8 @@ typedef struct hsa_code_object_s {
* @brief Application data handle that is passed to the serialization
* and deserialization functions.
*/
typedef struct hsa_callback_data_s {
typedef struct hsa_callback_data_s
{
/**
* Opaque handle.
*/
@@ -5215,7 +5272,8 @@ hsa_status_t HSA_API HSA_DEPRECATED hsa_code_object_destroy(
*
* @brief Code object type.
*/
typedef enum {
typedef enum
{
/**
* Produces code object that contains ISA for all kernels and indirect
* functions in HSA source.
@@ -5228,7 +5286,8 @@ typedef enum {
*
* @brief Code object attributes.
*/
typedef enum {
typedef enum
{
/**
* The version of the code object. The type of this attribute is a
* NUL-terminated char[64]. The name must be at most 63 characters long (not
@@ -5358,7 +5417,8 @@ hsa_status_t HSA_API HSA_DEPRECATED hsa_executable_load_code_object(
* associated with it. An operation on a symbol whose associated code object has
* been destroyed results in undefined behavior.
*/
typedef struct hsa_code_symbol_s {
typedef struct hsa_code_symbol_s
{
/**
* Opaque handle. Two handles reference the same object of the enclosing type
* if and only if they are equal.
@@ -5435,7 +5495,8 @@ hsa_status_t HSA_API HSA_DEPRECATED hsa_code_object_get_symbol_from_name(
*
* @brief Code object symbol attributes.
*/
typedef enum {
typedef enum
{
/**
* The type of the symbol. The type of this attribute is ::hsa_symbol_kind_t.
*/

15
src/dev/hsa/hsa_packet.hh
View File

@@ -38,7 +38,8 @@
#include <cstdint>
typedef struct hsa_packet_header_s {
typedef struct hsa_packet_header_s
{
// TODO: replace with more portable impl based on offset, length
uint16_t type:8;
uint16_t barrier:1;
@@ -48,7 +49,8 @@ typedef struct hsa_packet_header_s {
} hsa_packet_header_bitfield_t;
//TODO: put an _ in front of these guys to avoud prob with hsa.h for now
typedef struct _hsa_dispatch_packet_s {
typedef struct _hsa_dispatch_packet_s
{
uint16_t header;
uint16_t setup;
uint16_t workgroup_size_x;
@@ -66,7 +68,8 @@ typedef struct _hsa_dispatch_packet_s {
uint64_t completion_signal;
} _hsa_dispatch_packet_t;
typedef struct _hsa_agent_dispatch_packet_s {
typedef struct _hsa_agent_dispatch_packet_s
{
uint16_t header;
uint16_t type;
uint32_t reserved0;
@@ -76,7 +79,8 @@ typedef struct _hsa_agent_dispatch_packet_s {
uint64_t completion_signal;
} _hsa_agent_dispatch_packet_t;
typedef struct _hsa_barrier_and_packet_s {
typedef struct _hsa_barrier_and_packet_s
{
uint16_t header;
uint16_t reserved0;
uint32_t reserved1;
@@ -85,7 +89,8 @@ typedef struct _hsa_barrier_and_packet_s {
uint64_t completion_signal;
} _hsa_barrier_and_packet_t;
typedef struct _hsa_barrier_or_packet_s {
typedef struct _hsa_barrier_or_packet_s
{
uint16_t header;
uint16_t reserved0;
uint32_t reserved1;

6
src/dev/hsa/hsa_packet_processor.hh
View File

@@ -55,7 +55,8 @@
// Ideally, each queue should store this status and
// the processPkt() should make decisions based on that
// status variable.
typedef enum {
typedef enum
{
UNBLOCKED = 0, // Unblocked queue, can submit packets.
BLOCKED_BBIT, // Queue blocked by barrier bit.
// Can submit packet packets after
@@ -205,7 +206,8 @@ class AQLRingBuffer
uint64_t compltnPending() { return (_dispIdx - _rdIdx); }
};
typedef struct QueueContext {
typedef struct QueueContext
{
HSAQueueDescriptor* qDesc;
AQLRingBuffer* aqlBuf;
// used for HSA packets that enforce synchronization with barrier bit

9
src/dev/hsa/hsa_signal.hh
View File

@@ -46,9 +46,11 @@ enum amd_signal_kind_t
};
// AMD Signal.
typedef struct amd_signal_s {
typedef struct amd_signal_s
{
amd_signal_kind64_t kind;
union {
union
{
volatile int64_t value;
volatile uint32_t* legacy_hardware_doorbell_ptr;
volatile uint64_t* hardware_doorbell_ptr;
@@ -58,7 +60,8 @@ typedef struct amd_signal_s {
uint32_t reserved1;
uint64_t start_ts;
uint64_t end_ts;
union {
union
{
uint64_t queue_ptr;
uint64_t reserved2;
};

6
src/dev/mc146818.hh
View File

@@ -91,10 +91,12 @@ class MC146818 : public EventManager
RTCTickEvent tickEvent;
/** Data for real-time clock function */
union {
union
{
uint8_t clock_data[10];
struct {
struct
{
uint8_t sec;
uint8_t sec_alrm;
uint8_t min;

9
src/dev/net/dist_packet.hh
View File

@@ -89,17 +89,20 @@ class DistHeaderPkt
* (from EthPacketData::simLength).
*/
unsigned simLength;
union {
union
{
Tick sendDelay;
Tick syncRepeat;
};
union {
union
{
/**
* Actual length of the simulated Ethernet packet.
* (from EthPacketData::length).
*/
unsigned dataPacketLength;
struct {
struct
{
ReqType needCkpt;
ReqType needStopSync;
ReqType needExit;

166
src/dev/net/i8254xGBe_defs.hh
View File

@@ -188,8 +188,10 @@ enum IntTypes
// Receive Descriptor struct
struct RxDesc
{
union {
struct {
union
{
struct
{
Addr buf;
uint16_t len;
uint16_t csum;
@@ -197,18 +199,22 @@ struct RxDesc
uint8_t errors;
uint16_t vlan;
} legacy;
struct {
struct
{
Addr pkt;
Addr hdr;
} adv_read;
struct {
struct
{
uint16_t rss_type:4;
uint16_t pkt_type:12;
uint16_t __reserved1:5;
uint16_t header_len:10;
uint16_t sph:1;
union {
struct {
union
{
struct
{
uint16_t id;
uint16_t csum;
};
@@ -317,7 +323,9 @@ struct Regs : public Serializable
}
};
struct CTRL : public Reg<uint32_t> { // 0x0000 CTRL Register
struct CTRL : public Reg<uint32_t>
{
// 0x0000 CTRL Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(fd,0,1); // full duplex
ADD_FIELD32(bem,1,1); // big endian mode
@@ -353,7 +361,9 @@ struct Regs : public Serializable
};
CTRL ctrl;
struct STATUS : public Reg<uint32_t> { // 0x0008 STATUS Register
struct STATUS : public Reg<uint32_t>
{
// 0x0008 STATUS Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(fd,0,1); // full duplex
ADD_FIELD32(lu,1,1); // link up
@@ -370,7 +380,9 @@ struct Regs : public Serializable
};
STATUS sts;
struct EECD : public Reg<uint32_t> { // 0x0010 EECD Register
struct EECD : public Reg<uint32_t>
{
// 0x0010 EECD Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(sk,0,1); // clack input to the eeprom
ADD_FIELD32(cs,1,1); // chip select to eeprom
@@ -387,7 +399,9 @@ struct Regs : public Serializable
} ;
EECD eecd;
struct EERD : public Reg<uint32_t> { // 0x0014 EERD Register
struct EERD : public Reg<uint32_t>
{
// 0x0014 EERD Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(start,0,1); // start read
ADD_FIELD32(done,1,1); // done read
@@ -396,7 +410,9 @@ struct Regs : public Serializable
};
EERD eerd;
struct CTRL_EXT : public Reg<uint32_t> { // 0x0018 CTRL_EXT Register
struct CTRL_EXT : public Reg<uint32_t>
{
// 0x0018 CTRL_EXT Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(gpi_en,0,4); // enable interrupts from gpio
ADD_FIELD32(phyint,5,1); // reads the phy internal int status
@@ -416,7 +432,9 @@ struct Regs : public Serializable
};
CTRL_EXT ctrl_ext;
struct MDIC : public Reg<uint32_t> { // 0x0020 MDIC Register
struct MDIC : public Reg<uint32_t>
{
// 0x0020 MDIC Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(data,0,16); // data
ADD_FIELD32(regadd,16,5); // register address
@@ -428,7 +446,9 @@ struct Regs : public Serializable
};
MDIC mdic;
struct ICR : public Reg<uint32_t> { // 0x00C0 ICR Register
struct ICR : public Reg<uint32_t>
{
// 0x00C0 ICR Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(txdw,0,1) // tx descr witten back
ADD_FIELD32(txqe,1,1) // tx queue empty
@@ -452,7 +472,9 @@ struct Regs : public Serializable
uint32_t imr; // register that contains the current interrupt mask
struct ITR : public Reg<uint32_t> { // 0x00C4 ITR Register
struct ITR : public Reg<uint32_t>
{
// 0x00C4 ITR Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(interval, 0,16); // minimum inter-interrutp inteval
// specified in 256ns interrupts
@@ -464,7 +486,9 @@ struct Regs : public Serializable
// automatically clearing all interrupts that have a bit in the IAM set
uint32_t iam;
struct RCTL : public Reg<uint32_t> { // 0x0100 RCTL Register
struct RCTL : public Reg<uint32_t>
{
// 0x0100 RCTL Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(rst,0,1); // Reset
ADD_FIELD32(en,1,1); // Enable
@@ -499,13 +523,17 @@ struct Regs : public Serializable
};
RCTL rctl;
struct FCTTV : public Reg<uint32_t> { // 0x0170 FCTTV
struct FCTTV : public Reg<uint32_t>
{
// 0x0170 FCTTV
using Reg<uint32_t>::operator=;
ADD_FIELD32(ttv,0,16); // Transmit Timer Value
};
FCTTV fcttv;
struct TCTL : public Reg<uint32_t> { // 0x0400 TCTL Register
struct TCTL : public Reg<uint32_t>
{
// 0x0400 TCTL Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(rst,0,1); // Reset
ADD_FIELD32(en,1,1); // Enable
@@ -521,14 +549,18 @@ struct Regs : public Serializable
};
TCTL tctl;
struct PBA : public Reg<uint32_t> { // 0x1000 PBA Register
struct PBA : public Reg<uint32_t>
{
// 0x1000 PBA Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(rxa,0,16);
ADD_FIELD32(txa,16,16);
};
PBA pba;
struct FCRTL : public Reg<uint32_t> { // 0x2160 FCRTL Register
struct FCRTL : public Reg<uint32_t>
{
// 0x2160 FCRTL Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(rtl,3,28); // make this bigger than the spec so we can have
// a larger buffer
@@ -536,7 +568,9 @@ struct Regs : public Serializable
};
FCRTL fcrtl;
struct FCRTH : public Reg<uint32_t> { // 0x2168 FCRTL Register
struct FCRTH : public Reg<uint32_t>
{
// 0x2168 FCRTL Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(rth,3,13); // make this bigger than the spec so we can have
//a larger buffer
@@ -544,20 +578,26 @@ struct Regs : public Serializable
};
FCRTH fcrth;
struct RDBA : public Reg<uint64_t> { // 0x2800 RDBA Register
struct RDBA : public Reg<uint64_t>
{
// 0x2800 RDBA Register
using Reg<uint64_t>::operator=;
ADD_FIELD64(rdbal,0,32); // base address of rx descriptor ring
ADD_FIELD64(rdbah,32,32); // base address of rx descriptor ring
};
RDBA rdba;
struct RDLEN : public Reg<uint32_t> { // 0x2808 RDLEN Register
struct RDLEN : public Reg<uint32_t>
{
// 0x2808 RDLEN Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(len,7,13); // number of bytes in the descriptor buffer
};
RDLEN rdlen;
struct SRRCTL : public Reg<uint32_t> { // 0x280C SRRCTL Register
struct SRRCTL : public Reg<uint32_t>
{
// 0x280C SRRCTL Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(pktlen, 0, 8);
ADD_FIELD32(hdrlen, 8, 8); // guess based on header, not documented
@@ -568,26 +608,34 @@ struct Regs : public Serializable
};
SRRCTL srrctl;
struct RDH : public Reg<uint32_t> { // 0x2810 RDH Register
struct RDH : public Reg<uint32_t>
{
// 0x2810 RDH Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(rdh,0,16); // head of the descriptor ring
};
RDH rdh;
struct RDT : public Reg<uint32_t> { // 0x2818 RDT Register
struct RDT : public Reg<uint32_t>
{
// 0x2818 RDT Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(rdt,0,16); // tail of the descriptor ring
};
RDT rdt;
struct RDTR : public Reg<uint32_t> { // 0x2820 RDTR Register
struct RDTR : public Reg<uint32_t>
{
// 0x2820 RDTR Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(delay,0,16); // receive delay timer
ADD_FIELD32(fpd, 31,1); // flush partial descriptor block ??
};
RDTR rdtr;
struct RXDCTL : public Reg<uint32_t> { // 0x2828 RXDCTL Register
struct RXDCTL : public Reg<uint32_t>
{
// 0x2828 RXDCTL Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(pthresh,0,6); // prefetch threshold, less that this
// consider prefetch
@@ -598,38 +646,50 @@ struct Regs : public Serializable
};
RXDCTL rxdctl;
struct RADV : public Reg<uint32_t> { // 0x282C RADV Register
struct RADV : public Reg<uint32_t>
{
// 0x282C RADV Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(idv,0,16); // absolute interrupt delay
};
RADV radv;
struct RSRPD : public Reg<uint32_t> { // 0x2C00 RSRPD Register
struct RSRPD : public Reg<uint32_t>
{
// 0x2C00 RSRPD Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(idv,0,12); // size to interrutp on small packets
};
RSRPD rsrpd;
struct TDBA : public Reg<uint64_t> { // 0x3800 TDBAL Register
struct TDBA : public Reg<uint64_t>
{
// 0x3800 TDBAL Register
using Reg<uint64_t>::operator=;
ADD_FIELD64(tdbal,0,32); // base address of transmit descriptor ring
ADD_FIELD64(tdbah,32,32); // base address of transmit descriptor ring
};
TDBA tdba;
struct TDLEN : public Reg<uint32_t> { // 0x3808 TDLEN Register
struct TDLEN : public Reg<uint32_t>
{
// 0x3808 TDLEN Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(len,7,13); // number of bytes in the descriptor buffer
};
TDLEN tdlen;
struct TDH : public Reg<uint32_t> { // 0x3810 TDH Register
struct TDH : public Reg<uint32_t>
{
// 0x3810 TDH Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(tdh,0,16); // head of the descriptor ring
};
TDH tdh;
struct TXDCA_CTL : public Reg<uint32_t> { // 0x3814 TXDCA_CTL Register
struct TXDCA_CTL : public Reg<uint32_t>
{
// 0x3814 TXDCA_CTL Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(cpu_mask, 0, 5);
ADD_FIELD32(enabled, 5,1);
@@ -637,19 +697,25 @@ struct Regs : public Serializable
};
TXDCA_CTL txdca_ctl;
struct TDT : public Reg<uint32_t> { // 0x3818 TDT Register
struct TDT : public Reg<uint32_t>
{
// 0x3818 TDT Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(tdt,0,16); // tail of the descriptor ring
};
TDT tdt;
struct TIDV : public Reg<uint32_t> { // 0x3820 TIDV Register
struct TIDV : public Reg<uint32_t>
{
// 0x3820 TIDV Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(idv,0,16); // interrupt delay
};
TIDV tidv;
struct TXDCTL : public Reg<uint32_t> { // 0x3828 TXDCTL Register
struct TXDCTL : public Reg<uint32_t>
{
// 0x3828 TXDCTL Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(pthresh, 0,6); // if number of descriptors control has is
// below this number, a prefetch is considered
@@ -664,13 +730,17 @@ struct Regs : public Serializable
};
TXDCTL txdctl;
struct TADV : public Reg<uint32_t> { // 0x382C TADV Register
struct TADV : public Reg<uint32_t>
{
// 0x382C TADV Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(idv,0,16); // absolute interrupt delay
};
TADV tadv;
/*
struct TDWBA : public Reg<uint64_t> { // 0x3838 TDWBA Register
struct TDWBA : public Reg<uint64_t>
{
// 0x3838 TDWBA Register
using Reg<uint64_t>::operator=;
ADD_FIELD64(en,0,1); // enable transmit description ring address writeback
ADD_FIELD64(tdwbal,2,32); // base address of transmit descriptor ring address writeback
@@ -679,7 +749,9 @@ struct Regs : public Serializable
TDWBA tdwba;*/
uint64_t tdwba;
struct RXCSUM : public Reg<uint32_t> { // 0x5000 RXCSUM Register
struct RXCSUM : public Reg<uint32_t>
{
// 0x5000 RXCSUM Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(pcss,0,8);
ADD_FIELD32(ipofld,8,1);
@@ -690,7 +762,9 @@ struct Regs : public Serializable
uint32_t rlpml; // 0x5004 RLPML probably maximum accepted packet size
struct RFCTL : public Reg<uint32_t> { // 0x5008 RFCTL Register
struct RFCTL : public Reg<uint32_t>
{
// 0x5008 RFCTL Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(iscsi_dis,0,1);
ADD_FIELD32(iscsi_dwc,1,5);
@@ -705,7 +779,9 @@ struct Regs : public Serializable
};
RFCTL rfctl;
struct MANC : public Reg<uint32_t> { // 0x5820 MANC Register
struct MANC : public Reg<uint32_t>
{
// 0x5820 MANC Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(smbus,0,1); // SMBus enabled #####
ADD_FIELD32(asf,1,1); // ASF enabled #####
@@ -737,7 +813,9 @@ struct Regs : public Serializable
};
MANC manc;
struct SWSM : public Reg<uint32_t> { // 0x5B50 SWSM register
struct SWSM : public Reg<uint32_t>
{
// 0x5B50 SWSM register
using Reg<uint32_t>::operator=;
ADD_FIELD32(smbi,0,1); // Semaphone bit
ADD_FIELD32(swesmbi, 1,1); // Software eeporm semaphore
@@ -746,7 +824,9 @@ struct Regs : public Serializable
};
SWSM swsm;
struct FWSM : public Reg<uint32_t> { // 0x5B54 FWSM register
struct FWSM : public Reg<uint32_t>
{
// 0x5B54 FWSM register
using Reg<uint32_t>::operator=;
ADD_FIELD32(eep_fw_semaphore,0,1);
ADD_FIELD32(fw_mode, 1,3);

3
src/dev/net/sinic.hh
View File

@@ -104,7 +104,8 @@ class Device : public Base
};
/** device register file */
struct {
struct
{
uint32_t Config; // 0x00
uint32_t Command; // 0x04
uint32_t IntrStatus; // 0x08

20
src/dev/pci/copy_engine_defs.hh
View File

@@ -116,7 +116,9 @@ struct Regs : public Serializable
uint8_t chanCount;
uint8_t xferCap;
struct INTRCTRL : public Reg<uint8_t> { // 0x03
struct INTRCTRL : public Reg<uint8_t>
{
// 0x03
using Reg<uint8_t>::operator =;
ADD_FIELD8(master_int_enable,0,1);
ADD_FIELD8(interrupt_status,1,1);
@@ -146,7 +148,9 @@ struct Regs : public Serializable
struct ChanRegs : public Serializable
{
struct CHANCTRL : public Reg<uint16_t> { // channelX + 0x00
struct CHANCTRL : public Reg<uint16_t>
{
// channelX + 0x00
using Reg<uint16_t>::operator =;
ADD_FIELD16(interrupt_disable,0,1);
ADD_FIELD16(error_completion_enable, 2,1);
@@ -157,7 +161,9 @@ struct ChanRegs : public Serializable
};
CHANCTRL ctrl;
struct CHANSTS : public Reg<uint64_t> { // channelX + 0x04
struct CHANSTS : public Reg<uint64_t>
{
// channelX + 0x04
ADD_FIELD64(dma_transfer_status, 0, 3);
ADD_FIELD64(unaffiliated_error, 3, 1);
ADD_FIELD64(soft_error, 4, 1);
@@ -167,7 +173,9 @@ struct ChanRegs : public Serializable
uint64_t descChainAddr;
struct CHANCMD : public Reg<uint8_t> { // channelX + 0x14
struct CHANCMD : public Reg<uint8_t>
{
// channelX + 0x14
ADD_FIELD8(start_dma,0,1);
ADD_FIELD8(append_dma,1,1);
ADD_FIELD8(suspend_dma,2,1);
@@ -179,7 +187,9 @@ struct ChanRegs : public Serializable
uint64_t completionAddr;
struct CHANERR : public Reg<uint32_t> { // channel X + 0x28
struct CHANERR : public Reg<uint32_t>
{
// channel X + 0x28
ADD_FIELD32(source_addr_error,0,1);
ADD_FIELD32(dest_addr_error,1,1);
ADD_FIELD32(ndesc_addr_error,2,1);

18
src/dev/pci/pcireg.h
View File

@@ -68,7 +68,8 @@ union PCIConfig
{
uint8_t data[64];
struct {
struct
{
uint16_t vendor;
uint16_t device;
uint16_t command;
@@ -220,7 +221,8 @@ union PCIConfig
union PMCAP
{
uint8_t data[6];
struct {
struct
{
uint16_t pid; /* 0:7 cid
* 8:15 next
*/
@@ -254,7 +256,8 @@ union PMCAP
union MSICAP
{
uint8_t data[24];
struct {
struct
{
uint16_t mid; /* 0:7 cid
* 8:15 next
*/
@@ -282,7 +285,8 @@ union MSICAP
union MSIXCAP
{
uint8_t data[12];
struct {
struct
{
uint16_t mxid; /* 0:7 cid
* 8:15 next
*/
@@ -302,7 +306,8 @@ union MSIXCAP
union MSIXTable
{
struct {
struct
{
uint32_t addr_lo;
uint32_t addr_hi;
uint32_t msg_data;
@@ -324,7 +329,8 @@ struct MSIXPbaEntry
struct PXCAP
{
uint8_t data[48];
struct {
struct
{
uint16_t pxid; /* 0:7 cid
* 8:15 next
*/

9
src/dev/ps2/types.hh
View File

@@ -51,7 +51,8 @@
namespace Ps2 {
enum {
enum
{
SelfTestPass = 0xAA,
ReadID = 0xF2,
Enable = 0xF4,
@@ -65,7 +66,8 @@ enum {
namespace Keyboard {
enum {
enum
{
LEDWrite = 0xED,
DiagnosticEcho = 0xEE,
AlternateScanCodes = 0xF0,
@@ -85,7 +87,8 @@ extern const std::vector<uint8_t> ID;
namespace Mouse {
enum {
enum
{
Scale1to1 = 0xE6,
Scale2to1 = 0xE7,
SetResolution = 0xE8,

6
src/dev/riscv/vio_mmio.hh
View File

@@ -59,7 +59,8 @@ class MmioVirtIO : public PlicIntDevice
/** @{ */
/** Offsets into VirtIO MMIO space. */
enum : Addr {
enum : Addr
{
OFF_MAGIC = 0x00,
OFF_VERSION = 0x04,
OFF_DEVICE_ID = 0x08,
@@ -83,7 +84,8 @@ class MmioVirtIO : public PlicIntDevice
/** @} */
enum {
enum
{
INT_USED_RING = 1 << 0,
INT_CONFIG = 1 << 1,
};

3
src/dev/storage/ide_ctrl.hh
View File

@@ -78,7 +78,8 @@ class IdeController : public PciDevice
udmaControl, raz1, udmaTiming, raz2});
}
enum {
enum
{
TimeRegWithDecodeEnabled = 0x8000
};

21
src/dev/storage/ide_disk.hh
View File

@@ -66,7 +66,8 @@ class ChunkGenerator;
#define PRD_COUNT_MASK 0xfffe
#define PRD_EOT_MASK 0x8000
typedef struct PrdEntry {
typedef struct PrdEntry
{
uint32_t baseAddr;
uint16_t byteCount;
uint16_t endOfTable;
@@ -122,21 +123,24 @@ class PrdTableEntry
#define DEV0 (0)
#define DEV1 (1)
typedef struct CommandReg {
typedef struct CommandReg
{
uint16_t data;
uint8_t error;
uint8_t sec_count;
uint8_t sec_num;
uint8_t cyl_low;
uint8_t cyl_high;
union {
union
{
uint8_t drive;
uint8_t head;
};
uint8_t command;
} CommandReg_t;
typedef enum Events {
typedef enum Events
{
None = 0,
Transfer,
ReadWait,
@@ -146,7 +150,8 @@ typedef enum Events {
DmaWrite
} Events_t;
typedef enum DevAction {
typedef enum DevAction
{
ACT_NONE = 0,
ACT_CMD_WRITE,
ACT_CMD_COMPLETE,
@@ -164,7 +169,8 @@ typedef enum DevAction {
ACT_SRST_CLEAR
} DevAction_t;
typedef enum DevState {
typedef enum DevState
{
// Device idle
Device_Idle_S = 0,
Device_Idle_SI,
@@ -192,7 +198,8 @@ typedef enum DevState {
Device_Dma_Abort
} DevState_t;
typedef enum DmaState {
typedef enum DmaState
{
Dma_Idle = 0,
Dma_Start,
Dma_Transfer

9
src/kern/linux/linux.hh
View File

@@ -61,7 +61,8 @@ class Linux : public OperatingSystem
/// Stat buffer. Note that we can't call it 'stat' since that
/// gets #defined to something else on some systems. This type
/// can be specialized by architecture specific "Linux" classes
typedef struct {
typedef struct
{
uint32_t st_dev; //!< device
uint32_t st_ino; //!< inode
uint32_t st_mode; //!< mode
@@ -81,7 +82,8 @@ class Linux : public OperatingSystem
} tgt_stat;
// same for stat64
typedef struct {
typedef struct
{
uint64_t st_dev;
uint64_t st_ino;
uint64_t st_rdev;
@@ -159,7 +161,8 @@ class Linux : public OperatingSystem
// For select().
// linux-3.14-src/include/uapi/linux/posix_types.h
struct fd_set{
struct fd_set
{
#ifndef LINUX__FD_SETSIZE
#define LINUX__FD_SETSIZE 1024
unsigned long fds_bits[LINUX__FD_SETSIZE / (8 * sizeof(long))];

15
src/kern/operatingsystem.hh
View File

@@ -67,7 +67,8 @@ class OperatingSystem
static const int _SYS_NMLN = 65;
/// Interface struct for uname().
typedef struct {
typedef struct
{
char sysname[_SYS_NMLN]; //!< System name.
char nodename[_SYS_NMLN]; //!< Node name.
char release[_SYS_NMLN]; //!< OS release.
@@ -76,26 +77,30 @@ class OperatingSystem
} utsname;
/// Limit struct for getrlimit/setrlimit.
typedef struct {
typedef struct
{
uint64_t rlim_cur; //!< soft limit
uint64_t rlim_max; //!< hard limit
} rlimit;
/// For gettimeofday().
typedef struct {
typedef struct
{
int64_t tv_sec; //!< seconds
int64_t tv_usec; //!< microseconds
} timeval;
// For writev/readv
typedef struct {
typedef struct
{
uint64_t iov_base; // void *
uint64_t iov_len;
} tgt_iovec;
/// For getrusage().
typedef struct {
typedef struct
{
timeval ru_utime; //!< user time used
timeval ru_stime; //!< system time used
int64_t ru_maxrss; //!< max rss

9
src/kern/solaris/solaris.hh
View File

@@ -64,7 +64,8 @@ class Solaris : public OperatingSystem
/// Stat buffer. Note that we can't call it 'stat' since that
/// gets #defined to something else on some systems.
typedef struct {
typedef struct
{
uint64_t st_dev; //!< device
uint64_t st_ino; //!< inode
uint32_t st_mode; //!< mode
@@ -83,7 +84,8 @@ class Solaris : public OperatingSystem
} tgt_stat;
// same for stat64
typedef struct {
typedef struct
{
uint64_t st_dev; //!< device
uint64_t st_ino; //!< inode
uint32_t st_mode; //!< mode
@@ -105,7 +107,8 @@ class Solaris : public OperatingSystem
static const int _SYS_NMLN = 257;
/// Interface struct for uname().
typedef struct utsname {
typedef struct utsname
{
char sysname[_SYS_NMLN]; //!< System name.
char nodename[_SYS_NMLN]; //!< Node name.
char release[_SYS_NMLN]; //!< OS release.

3
src/mem/backdoor.hh
View File

@@ -43,7 +43,8 @@ class MemBackdoor
typedef std::function<void(const MemBackdoor &backdoor)> CbFunction;
public:
enum Flags{
enum Flags
{
// How data is allowed to be accessed through this backdoor.
NoAccess = 0x0,
Readable = 0x1,

3
src/mem/cache/compressors/base_delta.hh vendored
View File

@@ -80,7 +80,8 @@ class BaseDelta : public DictionaryCompressor<BaseType>
* These are used as indexes to reference the pattern data. If a new
* pattern is added, it must be done before NUM_PATTERNS.
*/
typedef enum {
typedef enum
{
X, M, NUM_PATTERNS
} PatternNumber;

3
src/mem/cache/compressors/cpack.hh vendored
View File

@@ -64,7 +64,8 @@ class CPack : public DictionaryCompressor<uint32_t>
* These are used as indexes to reference the pattern data. If a new
* pattern is added, it must be done before NUM_PATTERNS.
*/
typedef enum {
typedef enum
{
ZZZZ, XXXX, MMMM, MMXX, ZZZX, MMMX, NUM_PATTERNS
} PatternNumber;

3
src/mem/cache/compressors/fpc.hh vendored
View File

@@ -75,7 +75,8 @@ class FPC : public DictionaryCompressor<uint32_t>
* The possible patterns. If a new pattern is added, it must be done
* before NUM_PATTERNS.
*/
typedef enum {
typedef enum
{
ZERO_RUN, SIGN_EXTENDED_4_BITS, SIGN_EXTENDED_1_BYTE,
SIGN_EXTENDED_HALFWORD, ZERO_PADDED_HALFWORD,
SIGN_EXTENDED_TWO_HALFWORDS, REP_BYTES, UNCOMPRESSED,

3
src/mem/cache/compressors/fpcd.hh vendored
View File

@@ -92,7 +92,8 @@ class FPCD : public DictionaryCompressor<uint32_t>
* These are used as indexes to reference the pattern data. If a new
* pattern is added, it must be done before NUM_PATTERNS.
*/
typedef enum {
typedef enum
{
ZZZZ, FFFF, MMMMPenultimate, MMMMPrevious, ZZZX, XZZZ, RRRR,
MMMXPenultimate, MMMXPrevious, ZZXX, ZXZX, FFXX, XXZZ,
MMXXPenultimate, MMXXPrevious, XXXX, NUM_PATTERNS

3
src/mem/cache/compressors/repeated_qwords.hh vendored
View File

@@ -60,7 +60,8 @@ class RepeatedQwords : public DictionaryCompressor<uint64_t>
* These are used as indexes to reference the pattern data. If a new
* pattern is added, it must be done before NUM_PATTERNS.
*/
typedef enum {
typedef enum
{
X, M, NUM_PATTERNS
} PatternNumber;

3
src/mem/cache/compressors/zero.hh vendored
View File

@@ -60,7 +60,8 @@ class Zero : public DictionaryCompressor<uint64_t>
* These are used as indexes to reference the pattern data. If a new
* pattern is added, it must be done before NUM_PATTERNS.
*/
typedef enum {
typedef enum
{
X, Z, NUM_PATTERNS
} PatternNumber;

4
src/mem/packet.hh
View File

@@ -262,8 +262,8 @@ class Packet : public Printable
typedef ::Flags<FlagsType> Flags;
private:
enum : FlagsType {
enum : FlagsType
{
// Flags to transfer across when copying a packet
COPY_FLAGS = 0x000000FF,

12
src/mem/request.hh
View File

@@ -96,7 +96,8 @@ class Request
typedef uint8_t ArchFlagsType;
typedef ::Flags<FlagsType> Flags;
enum : FlagsType {
enum : FlagsType
{
/**
* Architecture specific flags.
*
@@ -243,7 +244,8 @@ class Request
/** Requestor Ids that are statically allocated
* @{*/
enum : RequestorID {
enum : RequestorID
{
/** This requestor id is used for writeback requests by the caches */
wbRequestorId = 0,
/**
@@ -291,7 +293,8 @@ class Request
* For atomics, the GLC bit is used to distinguish between between atomic
* return/no-return operations. These flags are used by GPUDynInst.
*/
enum : CacheCoherenceFlagsType {
enum : CacheCoherenceFlagsType
{
/** mem_sync_op flags */
INV_L1 = 0x00000001,
FLUSH_L2 = 0x00000020,
@@ -307,7 +310,8 @@ class Request
typedef uint16_t PrivateFlagsType;
typedef ::Flags<PrivateFlagsType> PrivateFlags;
enum : PrivateFlagsType {
enum : PrivateFlagsType
{
/** Whether or not the size is valid. */
VALID_SIZE = 0x00000001,
/** Whether or not paddr is valid (has been written yet). */

3
src/mem/ruby/common/TriggerQueue.hh
View File

@@ -53,7 +53,8 @@ template<typename T>
class TriggerQueue
{
private:
struct ValType {
struct ValType
{
T val;
bool non_blocking;
};

3
src/mem/stack_dist_calc.hh
View File

@@ -345,7 +345,8 @@ class StackDistCalc
/**
* Node which takes form of Leaf, INode or Root
*/
struct Node{
struct Node
{
// Sum of the left children
uint64_t sumLeft;

3
src/python/m5/params.py
View File

@@ -1334,7 +1334,8 @@ enum class $name
else:
code('''\
$wrapper $wrapper_name {
enum $name {
enum $name
{
''')
code.indent(1)
code.indent(1)

3
src/sim/insttracer.hh
View File

@@ -91,7 +91,8 @@ class InstRecord
* @TODO fix this and record all destintations that an instruction writes
* @see data_status
*/
union {
union
{
uint64_t as_int;
double as_double;
::VecRegContainer<TheISA::VecRegSizeBytes>* as_vec;

6
src/sim/syscall_emul.cc
View File

@@ -1112,7 +1112,8 @@ SyscallReturn
getdentsFunc(SyscallDesc *desc, ThreadContext *tc,
int tgt_fd, VPtr<> buf_ptr, unsigned count)
{
typedef struct linux_dirent {
typedef struct linux_dirent
{
unsigned long d_ino;
unsigned long d_off;
unsigned short d_reclen;
@@ -1129,7 +1130,8 @@ SyscallReturn
getdents64Func(SyscallDesc *desc, ThreadContext *tc,
int tgt_fd, VPtr<> buf_ptr, unsigned count)
{
typedef struct linux_dirent64 {
typedef struct linux_dirent64
{
ino64_t d_ino;
off64_t d_off;
unsigned short d_reclen;