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configs: Do not assume single mem range in RealView

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The SimpleSystem was assuming a single memory range for RealView
platforms by selecting the first element of the list only:

mem_range = self.realview._mem_regions[0]

This patch is fixing this by evaluating the entire list of platform
ranges.

Change-Id: I453fff7857966076c1419b95ddb9177e51d9f8d5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39636
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2021-01-21 11:35:04 +00:00
parent 95fdb9f3c4
commit 5e24869079
1 changed files with 25 additions and 7 deletions
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32
configs/example/arm/devices.py
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@@ -1,4 +1,4 @@
# Copyright (c) 2016-2017, 2019 ARM Limited
# Copyright (c) 2016-2017, 2019, 2021 Arm Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -301,14 +301,32 @@ class BaseSimpleSystem(ArmSystem):
self.iobus = IOXBar()
# Device DMA -> MEM
mem_range = self.realview._mem_regions[0]
assert int(mem_range.size()) >= int(Addr(mem_size))
self.mem_ranges = [
AddrRange(start=mem_range.start, size=mem_size) ]
self.mem_ranges = self.getMemRanges(int(Addr(mem_size)))
self._clusters = []
self._num_cpus = 0
def getMemRanges(self, mem_size):
"""
Define system memory ranges. This depends on the physical
memory map provided by the realview platform and by the memory
size provided by the user (mem_size argument).
The method is iterating over all platform ranges until they cover
the entire user's memory requirements.
"""
mem_ranges = []
for mem_range in self.realview._mem_regions:
size_in_range = min(mem_size, mem_range.size())
mem_ranges.append(
AddrRange(start=mem_range.start, size=size_in_range))
mem_size -= size_in_range
if mem_size == 0:
return mem_ranges
raise ValueError("memory size too big for platform capabilities")
def numCpuClusters(self):
return len(self._clusters)
@@ -361,10 +379,10 @@ class SimpleSystem(BaseSimpleSystem):
self._caches = caches
if self._caches:
self.iocache = IOCache(addr_ranges=[self.mem_ranges[0]])
self.iocache = IOCache(addr_ranges=self.mem_ranges)
else:
self.dmabridge = Bridge(delay='50ns',
ranges=[self.mem_ranges[0]])
ranges=self.mem_ranges)
def connect(self):
self.iobridge.mem_side_port = self.iobus.cpu_side_ports