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cpu: Merge the BaseDynInst and the BaseO3DynInst classes.

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Despite the generic sounding name and sort of generic contents, the
BaseDynInst was actually tied to the O3 CPU. Having the two independent
moving pieces created complexity but provided no real benefit. This was
evidenced by the fact that no CPU other than O3 actually used that
class.

Change-Id: I4ea1d053e2e172ececdc3113b8d76d5ad7490fc7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42094
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-02-27 03:37:26 -08:00
parent 55498f45dd
commit 1daf4bf39d
8 changed files with 1217 additions and 1557 deletions
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1194
src/cpu/base_dyn_inst.hh
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File diff suppressed because it is too large Load Diff

270
src/cpu/base_dyn_inst_impl.hh
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@@ -1,270 +0,0 @@
/*
* Copyright (c) 2011, 2019 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __CPU_BASE_DYN_INST_IMPL_HH__
#define __CPU_BASE_DYN_INST_IMPL_HH__
#include <iostream>
#include <set>
#include <sstream>
#include <string>
#include "base/cprintf.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "cpu/base_dyn_inst.hh"
#include "cpu/exetrace.hh"
#include "debug/DynInst.hh"
#include "debug/IQ.hh"
#include "mem/request.hh"
#include "sim/faults.hh"
template <class Impl>
BaseDynInst<Impl>::BaseDynInst(const StaticInstPtr &_staticInst,
const StaticInstPtr &_macroop,
TheISA::PCState _pc, TheISA::PCState _predPC,
InstSeqNum seq_num, ImplCPU *cpu)
: staticInst(_staticInst), cpu(cpu),
thread(nullptr),
traceData(nullptr),
regs(staticInst->numSrcRegs(), staticInst->numDestRegs()),
macroop(_macroop),
memData(nullptr),
savedReq(nullptr),
reqToVerify(nullptr)
{
seqNum = seq_num;
pc = _pc;
predPC = _predPC;
initVars();
}
template <class Impl>
BaseDynInst<Impl>::BaseDynInst(const StaticInstPtr &_staticInst,
const StaticInstPtr &_macroop)
: staticInst(_staticInst), traceData(NULL),
regs(staticInst->numSrcRegs(), staticInst->numDestRegs()),
macroop(_macroop)
{
seqNum = 0;
initVars();
}
template <class Impl>
void
BaseDynInst<Impl>::initVars()
{
memData = NULL;
effAddr = 0;
physEffAddr = 0;
readyRegs = 0;
memReqFlags = 0;
// hardware transactional memory
htmUid = -1;
htmDepth = 0;
status.reset();
instFlags.reset();
instFlags[RecordResult] = true;
instFlags[Predicate] = true;
instFlags[MemAccPredicate] = true;
lqIdx = -1;
sqIdx = -1;
// Eventually make this a parameter.
threadNumber = 0;
// Initialize the fault to be NoFault.
fault = NoFault;
#ifndef NDEBUG
++cpu->instcount;
if (cpu->instcount > 1500) {
#ifdef DEBUG
cpu->dumpInsts();
dumpSNList();
#endif
assert(cpu->instcount <= 1500);
}
DPRINTF(DynInst,
"DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
seqNum, cpu->name(), cpu->instcount);
#endif
#ifdef DEBUG
cpu->snList.insert(seqNum);
#endif
}
template <class Impl>
BaseDynInst<Impl>::~BaseDynInst()
{
if (memData) {
delete [] memData;
}
if (traceData) {
delete traceData;
}
fault = NoFault;
#ifndef NDEBUG
--cpu->instcount;
DPRINTF(DynInst,
"DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
seqNum, cpu->name(), cpu->instcount);
#endif
#ifdef DEBUG
cpu->snList.erase(seqNum);
#endif
}
#ifdef DEBUG
template <class Impl>
void
BaseDynInst<Impl>::dumpSNList()
{
std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
int count = 0;
while (sn_it != cpu->snList.end()) {
cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
count++;
sn_it++;
}
}
#endif
template <class Impl>
void
BaseDynInst<Impl>::dump()
{
cprintf("T%d : %#08d `", threadNumber, pc.instAddr());
std::cout << staticInst->disassemble(pc.instAddr());
cprintf("'\n");
}
template <class Impl>
void
BaseDynInst<Impl>::dump(std::string &outstring)
{
std::ostringstream s;
s << "T" << threadNumber << " : 0x" << pc.instAddr() << " "
<< staticInst->disassemble(pc.instAddr());
outstring = s.str();
}
template <class Impl>
void
BaseDynInst<Impl>::markSrcRegReady()
{
DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
seqNum, readyRegs+1, numSrcRegs(), readyToIssue());
if (++readyRegs == numSrcRegs()) {
setCanIssue();
}
}
template <class Impl>
void
BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
{
regs.readySrcIdx(src_idx, true);
markSrcRegReady();
}
template <class Impl>
bool
BaseDynInst<Impl>::eaSrcsReady() const
{
// For now I am assuming that src registers 1..n-1 are the ones that the
// EA calc depends on. (i.e. src reg 0 is the source of the data to be
// stored)
for (int i = 1; i < numSrcRegs(); ++i) {
if (!regs.readySrcIdx(i))
return false;
}
return true;
}
template <class Impl>
void
BaseDynInst<Impl>::setSquashed()
{
status.set(Squashed);
if (!isPinnedRegsRenamed() || isPinnedRegsSquashDone())
return;
// This inst has been renamed already so it may go through rename
// again (e.g. if the squash is due to memory access order violation).
// Reset the write counters for all pinned destination register to ensure
// that they are in a consistent state for a possible re-rename. This also
// ensures that dest regs will be pinned to the same phys register if
// re-rename happens.
for (int idx = 0; idx < numDestRegs(); idx++) {
PhysRegIdPtr phys_dest_reg = regs.renamedDestIdx(idx);
if (phys_dest_reg->isPinned()) {
phys_dest_reg->incrNumPinnedWrites();
if (isPinnedRegsWritten())
phys_dest_reg->incrNumPinnedWritesToComplete();
}
}
setPinnedRegsSquashDone();
}
#endif//__CPU_BASE_DYN_INST_IMPL_HH__

4
src/cpu/checker/cpu.hh
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@@ -49,7 +49,6 @@
#include "arch/types.hh"
#include "base/statistics.hh"
#include "cpu/base.hh"
#include "cpu/base_dyn_inst.hh"
#include "cpu/exec_context.hh"
#include "cpu/inst_res.hh"
#include "cpu/pc_event.hh"
@@ -60,9 +59,6 @@
#include "params/CheckerCPU.hh"
#include "sim/eventq.hh"
class BaseTLB;
template <class>
class BaseDynInst;
class ThreadContext;
class Request;

1
src/cpu/checker/cpu_impl.hh
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@@ -47,7 +47,6 @@
#include "base/refcnt.hh"
#include "config/the_isa.hh"
#include "cpu/base_dyn_inst.hh"
#include "cpu/exetrace.hh"
#include "cpu/reg_class.hh"
#include "cpu/simple_thread.hh"

1
src/cpu/o3/SConscript
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@@ -35,7 +35,6 @@ if 'O3CPU' in env['CPU_MODELS']:
SimObject('FuncUnitConfig.py')
SimObject('O3CPU.py')
Source('base_dyn_inst.cc')
Source('commit.cc')
Source('cpu.cc')
Source('decode.cc')

34
src/cpu/o3/base_dyn_inst.cc
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@@ -1,34 +0,0 @@
/*
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "cpu/base_dyn_inst_impl.hh"
#include "cpu/o3/cpu.hh"
#include "cpu/o3/isa_specific.hh"
// Explicit instantiation
template class BaseDynInst<O3CPUImpl>;

1096
src/cpu/o3/dyn_inst.hh
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174
src/cpu/o3/dyn_inst_impl.hh
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@@ -44,25 +44,57 @@
#include <algorithm>
#include "cpu/o3/dyn_inst.hh"
#include "debug/DynInst.hh"
#include "debug/IQ.hh"
#include "debug/O3PipeView.hh"
template <class Impl>
BaseO3DynInst<Impl>::BaseO3DynInst(const StaticInstPtr &staticInst,
const StaticInstPtr &macroop,
TheISA::PCState pc, TheISA::PCState predPC,
InstSeqNum seq_num, O3CPU *cpu)
: BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu)
BaseO3DynInst<Impl>::BaseO3DynInst(const StaticInstPtr &static_inst,
const StaticInstPtr &_macroop,
TheISA::PCState _pc,
TheISA::PCState pred_pc,
InstSeqNum seq_num,
typename Impl::O3CPU *_cpu)
: seqNum(seq_num), staticInst(static_inst), cpu(_cpu), pc(_pc),
regs(staticInst->numSrcRegs(), staticInst->numDestRegs()),
predPC(pred_pc), macroop(_macroop)
{
initVars();
this->regs.init();
status.reset();
instFlags.reset();
instFlags[RecordResult] = true;
instFlags[Predicate] = true;
instFlags[MemAccPredicate] = true;
#ifndef NDEBUG
++cpu->instcount;
if (cpu->instcount > 1500) {
#ifdef DEBUG
cpu->dumpInsts();
dumpSNList();
#endif
assert(cpu->instcount <= 1500);
}
DPRINTF(DynInst,
"DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
seqNum, cpu->name(), cpu->instcount);
#endif
#ifdef DEBUG
cpu->snList.insert(seqNum);
#endif
}
template <class Impl>
BaseO3DynInst<Impl>::BaseO3DynInst(const StaticInstPtr &_staticInst,
const StaticInstPtr &_macroop)
: BaseDynInst<Impl>(_staticInst, _macroop)
{
initVars();
}
: BaseO3DynInst<Impl>(_staticInst, _macroop, {}, {}, 0, nullptr)
{}
template <class Impl>BaseO3DynInst<Impl>::~BaseO3DynInst()
{
@@ -97,27 +129,121 @@ template <class Impl>BaseO3DynInst<Impl>::~BaseO3DynInst()
}
}
#endif
delete [] memData;
delete traceData;
fault = NoFault;
#ifndef NDEBUG
--cpu->instcount;
DPRINTF(DynInst,
"DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
seqNum, cpu->name(), cpu->instcount);
#endif
#ifdef DEBUG
cpu->snList.erase(seqNum);
#endif
};
#ifdef DEBUG
template <class Impl>
void
BaseO3DynInst<Impl>::dumpSNList()
{
std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
int count = 0;
while (sn_it != cpu->snList.end()) {
cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
count++;
sn_it++;
}
}
#endif
template <class Impl>
void
BaseO3DynInst<Impl>::dump()
{
cprintf("T%d : %#08d `", threadNumber, pc.instAddr());
std::cout << staticInst->disassemble(pc.instAddr());
cprintf("'\n");
}
template <class Impl>
void
BaseO3DynInst<Impl>::dump(std::string &outstring)
{
std::ostringstream s;
s << "T" << threadNumber << " : 0x" << pc.instAddr() << " "
<< staticInst->disassemble(pc.instAddr());
outstring = s.str();
}
template <class Impl>
void
BaseO3DynInst<Impl>::markSrcRegReady()
{
DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
seqNum, readyRegs+1, numSrcRegs(), readyToIssue());
if (++readyRegs == numSrcRegs()) {
setCanIssue();
}
}
template <class Impl>
void
BaseO3DynInst<Impl>::markSrcRegReady(RegIndex src_idx)
{
regs.readySrcIdx(src_idx, true);
markSrcRegReady();
}
template <class Impl>
bool
BaseO3DynInst<Impl>::eaSrcsReady() const
{
// For now I am assuming that src registers 1..n-1 are the ones that the
// EA calc depends on. (i.e. src reg 0 is the source of the data to be
// stored)
for (int i = 1; i < numSrcRegs(); ++i) {
if (!regs.readySrcIdx(i))
return false;
}
return true;
}
template <class Impl>
void
BaseO3DynInst<Impl>::initVars()
BaseO3DynInst<Impl>::setSquashed()
{
this->regs.init();
status.set(Squashed);
#if TRACING_ON
// Value -1 indicates that particular phase
// hasn't happened (yet).
fetchTick = -1;
decodeTick = -1;
renameTick = -1;
dispatchTick = -1;
issueTick = -1;
completeTick = -1;
commitTick = -1;
storeTick = -1;
#endif
if (!isPinnedRegsRenamed() || isPinnedRegsSquashDone())
return;
// This inst has been renamed already so it may go through rename
// again (e.g. if the squash is due to memory access order violation).
// Reset the write counters for all pinned destination register to ensure
// that they are in a consistent state for a possible re-rename. This also
// ensures that dest regs will be pinned to the same phys register if
// re-rename happens.
for (int idx = 0; idx < numDestRegs(); idx++) {
PhysRegIdPtr phys_dest_reg = regs.renamedDestIdx(idx);
if (phys_dest_reg->isPinned()) {
phys_dest_reg->incrNumPinnedWrites();
if (isPinnedRegsWritten())
phys_dest_reg->incrNumPinnedWritesToComplete();
}
}
setPinnedRegsSquashDone();
}
template <class Impl>