derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

cpu: Simplify the RegId class a little.

Browse Source 
Having const and non const reference accessors for the RegId index are
basically the same thing as just making the index value public but with
more complexity. Stop allowing updates through the accessor, and
simplify/fix the one location that was using that.

Also, there is no good reason to return an integer value by const
reference instead of returning it by value, since the value being passed
around (a pointer) is the same size, and just makes the value harder to
access.

Change-Id: I377ffc5878ef9bffa2ac53626a87c019a585ab1a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42684
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-02-23 19:09:46 -08:00
parent 6f3c197742
commit 3c3c2c3076
2 changed files with 10 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
src/cpu/o3/cpu.cc
View File

@@ -773,29 +773,23 @@ FullO3CPU<Impl>::insertThread(ThreadID tid)
//Bind Int Regs to Rename Map
const auto &regClasses = isa[tid]->regClasses();
for (RegId reg_id(IntRegClass, 0);
reg_id.index() < regClasses.at(IntRegClass).size();
reg_id.index()++) {
for (RegIndex idx = 0; idx < regClasses.at(IntRegClass).size(); idx++) {
PhysRegIdPtr phys_reg = freeList.getIntReg();
renameMap[tid].setEntry(reg_id, phys_reg);
renameMap[tid].setEntry(RegId(IntRegClass, idx), phys_reg);
scoreboard.setReg(phys_reg);
}
//Bind Float Regs to Rename Map
for (RegId reg_id(FloatRegClass, 0);
reg_id.index() < regClasses.at(FloatRegClass).size();
reg_id.index()++) {
for (RegIndex idx = 0; idx < regClasses.at(FloatRegClass).size(); idx++) {
PhysRegIdPtr phys_reg = freeList.getFloatReg();
renameMap[tid].setEntry(reg_id, phys_reg);
renameMap[tid].setEntry(RegId(FloatRegClass, idx), phys_reg);
scoreboard.setReg(phys_reg);
}
//Bind condition-code Regs to Rename Map
for (RegId reg_id(CCRegClass, 0);
reg_id.index() < regClasses.at(CCRegClass).size();
reg_id.index()++) {
for (RegIndex idx = 0; idx < regClasses.at(CCRegClass).size(); idx++) {
PhysRegIdPtr phys_reg = freeList.getCCReg();
renameMap[tid].setEntry(reg_id, phys_reg);
renameMap[tid].setEntry(RegId(CCRegClass, idx), phys_reg);
scoreboard.setReg(phys_reg);
}

9
src/cpu/reg_class.hh
View File

@@ -168,13 +168,12 @@ class RegId
/** Index accessors */
/** @{ */
const RegIndex& index() const { return regIdx; }
RegIndex& index() { return regIdx; }
RegIndex index() const { return regIdx; }
/** Index flattening.
* Required to be able to use a vector for the register mapping.
*/
inline RegIndex
RegIndex
flatIndex() const
{
switch (regClass) {
@@ -194,9 +193,9 @@ class RegId
/** @} */
/** Elem accessor */
const RegIndex& elemIndex() const { return elemIdx; }
RegIndex elemIndex() const { return elemIdx; }
/** Class accessor */
const RegClass& classValue() const { return regClass; }
RegClass classValue() const { return regClass; }
/** Return a const char* with the register class name. */
const char* className() const { return regClassStrings[regClass]; }