derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

misc: Fix coding style for union's opening braces

Browse Source 
The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, 2 and 3 levels of indentation, using:

    grep -nrE --exclude-dir=systemc \
        "^ *union [A-Za-z].* {$" src/

Then the following commands were run to replace:

    <indent level>union X ... {

by:

    <indent level>union X ...
    <indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc \
        "^union [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^union ([A-Za-z].*) \{$/union \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    union [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    union ([A-Za-z].*) \{$/    union \1\n    \{/g'

and so on.

Change-Id: I066854eb27a8acd2cc2dfa41596bb1b1f66c71b1
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43328
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
This commit is contained in:
Daniel R. Carvalho
2021-03-19 19:11:44 -03:00
committed by Daniel Carvalho
parent df8ef51d61
commit b2c0b191e1
7 changed files with 38 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

27
src/arch/arm/isa/insts/macromem.isa
View File

@@ -194,7 +194,8 @@ let {{
regs = (size + 3) // 4
subst = { "size" : size, "regs" : regs }
memDecl = '''
union MemUnion {
union MemUnion
{
uint8_t bytes[%(size)d];
Element elements[%(size)d / sizeof(Element)];
uint32_t floatRegBits[%(regs)d];
@@ -312,7 +313,8 @@ let {{
const unsigned regs = 2 * dRegs;
const unsigned perDReg =
(2 * sizeof(uint32_t)) / sizeof(Element);
union convStruct {
union convStruct
{
uint32_t cRegs[regs];
Element elements[dRegs * perDReg];
} conv1, conv2;
@@ -358,7 +360,8 @@ let {{
const unsigned regs = 2 * dRegs;
const unsigned perDReg =
(2 * sizeof(uint32_t)) / sizeof(Element);
union convStruct {
union convStruct
{
uint32_t cRegs[regs];
Element elements[dRegs * perDReg];
} conv1, conv2;
@@ -431,12 +434,14 @@ let {{
microUnpackNeonCode = '''
const unsigned perDReg = (2 * sizeof(uint32_t)) / sizeof(Element);
union SourceRegs {
union SourceRegs
{
uint32_t fRegs[2 * %(sRegs)d];
Element elements[%(sRegs)d * perDReg];
} sourceRegs;
union DestReg {
union DestReg
{
uint32_t fRegs[2];
Element elements[perDReg];
} destRegs[%(dRegs)d];
@@ -479,12 +484,14 @@ let {{
microUnpackAllNeonCode = '''
const unsigned perDReg = (2 * sizeof(uint32_t)) / sizeof(Element);
union SourceRegs {
union SourceRegs
{
uint32_t fRegs[2 * %(sRegs)d];
Element elements[%(sRegs)d * perDReg];
} sourceRegs;
union DestReg {
union DestReg
{
uint32_t fRegs[2];
Element elements[perDReg];
} destRegs[%(dRegs)d];
@@ -529,12 +536,14 @@ let {{
const unsigned perDReg =
(2 * sizeof(uint32_t)) / sizeof(Element);
union SourceReg {
union SourceReg
{
uint32_t fRegs[2];
Element elements[perDReg];
} sourceRegs[%(sRegs)d];
union DestRegs {
union DestRegs
{
uint32_t fRegs[2 * %(dRegs)d];
Element elements[%(dRegs)d * perDReg];
} destRegs;

3
src/arch/arm/isa/insts/neon64_mem.isa
View File

@@ -59,7 +59,8 @@ let {{
'''
memDecl = '''
const int MaxNumBytes = 16;
union MemUnion {
union MemUnion
{
uint8_t bytes[MaxNumBytes];
uint32_t floatRegBits[MaxNumBytes / 4];
};

3
src/arch/arm/kvm/armv8_cpu.cc
View File

@@ -81,7 +81,8 @@ kvmFPReg(const int num)
(SIMD_REG(fp_regs.vregs[1]) - SIMD_REG(fp_regs.vregs[0])) * num;
}
union KvmFPReg {
union KvmFPReg
{
union {
uint32_t i;
float f;

3
src/arch/gcn3/gpu_decoder.hh
View File

@@ -1635,7 +1635,8 @@ namespace Gcn3ISA
unsigned int SRC1_ABS : 1;
};
union InstFormat {
union InstFormat
{
InFmt_DS iFmt_DS;
InFmt_DS_1 iFmt_DS_1;
InFmt_EXP iFmt_EXP;

3
src/cpu/inst_res.hh
View File

@@ -46,7 +46,8 @@
class InstResult
{
public:
union MultiResult {
union MultiResult
{
uint64_t integer;
double dbl;
TheISA::VecRegContainer vector;

15
src/dev/pci/pcireg.h
View File

@@ -64,7 +64,8 @@ BitUnion16(PciCommandRegister)
Bitfield<0> ioSpace;
EndBitUnion(PciCommandRegister)
union PCIConfig {
union PCIConfig
{
uint8_t data[64];
struct {
@@ -216,7 +217,8 @@ union PCIConfig {
* Defines the Power Management capability register and all its associated
* bitfields for a PCIe device.
*/
union PMCAP {
union PMCAP
{
uint8_t data[6];
struct {
uint16_t pid; /* 0:7 cid
@@ -249,7 +251,8 @@ union PMCAP {
* can be filled in if a device model supports both, but only 1 of
* MSI/MSIX/INTx interrupt mode can be selected at a given time.
*/
union MSICAP {
union MSICAP
{
uint8_t data[24];
struct {
uint16_t mid; /* 0:7 cid
@@ -276,7 +279,8 @@ union MSICAP {
* Defines the MSI-X Capability register and its associated bitfields for
* a PCIe device.
*/
union MSIXCAP {
union MSIXCAP
{
uint8_t data[12];
struct {
uint16_t mxid; /* 0:7 cid
@@ -296,7 +300,8 @@ union MSIXCAP {
};
};
union MSIXTable {
union MSIXTable
{
struct {
uint32_t addr_lo;
uint32_t addr_hi;

3
src/sim/syscall_emul.cc
View File

@@ -1516,7 +1516,8 @@ getsockoptFunc(SyscallDesc *desc, ThreadContext *tc,
VPtr<> lenPtr)
{
// union of all possible return value types from getsockopt
union val {
union val
{
int i_val;
long l_val;
struct linger linger_val;