derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch,cpu: Collapse away TheISA::advancePC.

Browse Source 
In most ISAs except MIPS and Power, this was implemented as
inst->advancePC(). It works just fine to call this function all the
time, but the idea had originally been that for ISAs which could simply
advance the PC using the PC itself, they could save the virtual function
call. Since the only ISAs which could skip the call were MIPS and Power,
and neither is at the point where that level of performance tuning
matters, this function can be collapsed with little downside.

If this turns out to be a performance bottleneck in the future, the way
the PC is managed could be revisited to see if we can factor out this
trip to the instruction object in the first place.

Change-Id: I533d1ad316e5c936466c529b7f1238a9ab87bd1c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39335
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Alex Dutu <alexandru.dutu@amd.com>
This commit is contained in:
Gabe Black
2021-01-18 19:18:05 -08:00
parent 7ac67eaf1b
commit 2cb09e4042
16 changed files with 13 additions and 54 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/arch/arm/utility.hh
View File

@@ -375,12 +375,6 @@ isGenericTimerSystemAccessTrapEL3(const MiscRegIndex miscReg,
bool SPAlignmentCheckEnabled(ThreadContext* tc);
inline void
advancePC(PCState &pc, const StaticInstPtr &inst)
{
inst->advancePC(pc);
}
Addr truncPage(Addr addr);
Addr roundPage(Addr addr);

8
src/arch/mips/utility.hh
View File

@@ -72,14 +72,6 @@ RoundPage(Addr addr)
return (addr + PageBytes - 1) & ~(PageBytes - 1);
}
void copyRegs(ThreadContext *src, ThreadContext *dest);
inline void
advancePC(PCState &pc, const StaticInstPtr &inst)
{
pc.advance();
}
};

6
src/arch/power/utility.hh
View File

@@ -39,12 +39,6 @@ namespace PowerISA {
void copyRegs(ThreadContext *src, ThreadContext *dest);
inline void
advancePC(PCState &pc, const StaticInstPtr &inst)
{
pc.advance();
}
} // namespace PowerISA

2
src/arch/riscv/faults.cc
View File

@@ -141,7 +141,7 @@ RiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
pcState.set(addr);
} else {
invokeSE(tc, inst);
advancePC(pcState, inst);
inst->advancePC(pcState);
}
tc->pcState(pcState);
}

6
src/arch/riscv/utility.hh
View File

@@ -142,12 +142,6 @@ registerName(RegId reg)
}
}
inline void
advancePC(PCState &pc, const StaticInstPtr &inst)
{
inst->advancePC(pc);
}
} // namespace RiscvISA
#endif // __ARCH_RISCV_UTILITY_HH__

6
src/arch/sparc/utility.hh
View File

@@ -43,12 +43,6 @@ namespace SparcISA
void copyRegs(ThreadContext *src, ThreadContext *dest);
inline void
advancePC(PCState &pc, const StaticInstPtr &inst)
{
inst->advancePC(pc);
}
} // namespace SparcISA
#endif

6
src/arch/x86/utility.hh
View File

@@ -46,12 +46,6 @@ namespace X86ISA
{
void copyRegs(ThreadContext *src, ThreadContext *dest);
inline void
advancePC(PCState &pc, const StaticInstPtr &inst)
{
inst->advancePC(pc);
}
/**
* Reconstruct the rflags register from the internal gem5 register
* state.

2
src/cpu/base_dyn_inst.hh
View File

@@ -590,7 +590,7 @@ class BaseDynInst : public ExecContext, public RefCounted
mispredicted()
{
TheISA::PCState tempPC = pc;
TheISA::advancePC(tempPC, staticInst);
staticInst->advancePC(tempPC);
return !(tempPC == predPC);
}

2
src/cpu/checker/cpu_impl.hh
View File

@@ -72,7 +72,7 @@ Checker<Impl>::advancePC(const Fault &fault)
if (curStaticInst->isLastMicroop())
curMacroStaticInst = StaticInst::nullStaticInstPtr;
TheISA::PCState pcState = thread->pcState();
TheISA::advancePC(pcState, curStaticInst);
curStaticInst->advancePC(pcState);
thread->pcState(pcState);
DPRINTF(Checker, "Advancing PC to %s.\n", thread->pcState());
}

6
src/cpu/minor/execute.cc
View File

@@ -39,7 +39,6 @@
#include "arch/locked_mem.hh"
#include "arch/registers.hh"
#include "arch/utility.hh"
#include "cpu/minor/cpu.hh"
#include "cpu/minor/exec_context.hh"
#include "cpu/minor/fetch1.hh"
@@ -239,9 +238,8 @@ Execute::tryToBranch(MinorDynInstPtr inst, Fault fault, BranchData &branch)
/* The reason for the branch data we're about to generate, set below */
BranchData::Reason reason = BranchData::NoBranch;
if (fault == NoFault)
{
TheISA::advancePC(target, inst->staticInst);
if (fault == NoFault) {
inst->staticInst->advancePC(target);
thread->pcState(target);
DPRINTF(Branch, "Advancing current PC from: %s to: %s\n",

2
src/cpu/minor/fetch2.cc
View File

@@ -455,7 +455,7 @@ Fetch2::evaluate()
#endif
/* Advance PC for the next instruction */
TheISA::advancePC(fetch_info.pc, decoded_inst);
decoded_inst->advancePC(fetch_info.pc);
/* Predict any branches and issue a branch if
* necessary */

2
src/cpu/o3/commit_impl.hh
View File

@@ -1109,7 +1109,7 @@ DefaultCommit<Impl>::commitInsts()
cpu->traceFunctions(pc[tid].instAddr());
TheISA::advancePC(pc[tid], head_inst->staticInst);
head_inst->staticInst->advancePC(pc[tid]);
// Keep track of the last sequence number commited
lastCommitedSeqNum[tid] = head_inst->seqNum;

2
src/cpu/o3/fetch_impl.hh
View File

@@ -527,7 +527,7 @@ DefaultFetch<Impl>::lookupAndUpdateNextPC(
bool predict_taken;
if (!inst->isControl()) {
TheISA::advancePC(nextPC, inst->staticInst);
inst->staticInst->advancePC(nextPC);
inst->setPredTarg(nextPC);
inst->setPredTaken(false);
return false;

2
src/cpu/o3/iew_impl.hh
View File

@@ -460,7 +460,7 @@ DefaultIEW<Impl>::squashDueToBranch(const DynInstPtr& inst, ThreadID tid)
toCommit->branchTaken[tid] = inst->pcState().branching();
TheISA::PCState pc = inst->pcState();
TheISA::advancePC(pc, inst->staticInst);
inst->staticInst->advancePC(pc);
toCommit->pc[tid] = pc;
toCommit->mispredictInst[tid] = inst;

6
src/cpu/pred/bpred_unit.cc
View File

@@ -227,7 +227,7 @@ BPredUnit::predict(const StaticInstPtr &inst, const InstSeqNum &seqNum,
RAS[tid].pop();
predict_record.pushedRAS = false;
}
TheISA::advancePC(target, inst);
inst->advancePC(target);
}
} else {
predict_record.wasIndirect = true;
@@ -256,7 +256,7 @@ BPredUnit::predict(const StaticInstPtr &inst, const InstSeqNum &seqNum,
RAS[tid].pop();
predict_record.pushedRAS = false;
}
TheISA::advancePC(target, inst);
inst->advancePC(target);
}
iPred->recordIndirect(pc.instAddr(), target.instAddr(), seqNum,
tid);
@@ -266,7 +266,7 @@ BPredUnit::predict(const StaticInstPtr &inst, const InstSeqNum &seqNum,
if (inst->isReturn()) {
predict_record.wasReturn = true;
}
TheISA::advancePC(target, inst);
inst->advancePC(target);
}
predict_record.target = target.instAddr();

3
src/cpu/simple/base.cc
View File

@@ -41,7 +41,6 @@
#include "cpu/simple/base.hh"
#include "arch/utility.hh"
#include "base/cprintf.hh"
#include "base/inifile.hh"
#include "base/loader/symtab.hh"
@@ -481,7 +480,7 @@ BaseSimpleCPU::advancePC(const Fault &fault)
if (curStaticInst->isLastMicroop())
curMacroStaticInst = StaticInst::nullStaticInstPtr;
TheISA::PCState pcState = thread->pcState();
TheISA::advancePC(pcState, curStaticInst);
curStaticInst->advancePC(pcState);
thread->pcState(pcState);
}
}