diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh index 5b3b849b43..3c8acb22ea 100644 --- a/src/arch/arm/utility.hh +++ b/src/arch/arm/utility.hh @@ -375,12 +375,6 @@ isGenericTimerSystemAccessTrapEL3(const MiscRegIndex miscReg, bool SPAlignmentCheckEnabled(ThreadContext* tc); -inline void -advancePC(PCState &pc, const StaticInstPtr &inst) -{ - inst->advancePC(pc); -} - Addr truncPage(Addr addr); Addr roundPage(Addr addr); diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh index 1804680078..f86e93acdf 100644 --- a/src/arch/mips/utility.hh +++ b/src/arch/mips/utility.hh @@ -72,14 +72,6 @@ RoundPage(Addr addr) return (addr + PageBytes - 1) & ~(PageBytes - 1); } -void copyRegs(ThreadContext *src, ThreadContext *dest); - -inline void -advancePC(PCState &pc, const StaticInstPtr &inst) -{ - pc.advance(); -} - }; diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh index 03df7fb6de..13183f1c37 100644 --- a/src/arch/power/utility.hh +++ b/src/arch/power/utility.hh @@ -39,12 +39,6 @@ namespace PowerISA { void copyRegs(ThreadContext *src, ThreadContext *dest); -inline void -advancePC(PCState &pc, const StaticInstPtr &inst) -{ - pc.advance(); -} - } // namespace PowerISA diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc index 8c273f2a98..4b2581053f 100644 --- a/src/arch/riscv/faults.cc +++ b/src/arch/riscv/faults.cc @@ -141,7 +141,7 @@ RiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) pcState.set(addr); } else { invokeSE(tc, inst); - advancePC(pcState, inst); + inst->advancePC(pcState); } tc->pcState(pcState); } diff --git a/src/arch/riscv/utility.hh b/src/arch/riscv/utility.hh index 3bbbd716e2..f033b2b4c3 100644 --- a/src/arch/riscv/utility.hh +++ b/src/arch/riscv/utility.hh @@ -142,12 +142,6 @@ registerName(RegId reg) } } -inline void -advancePC(PCState &pc, const StaticInstPtr &inst) -{ - inst->advancePC(pc); -} - } // namespace RiscvISA #endif // __ARCH_RISCV_UTILITY_HH__ diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh index f179c1751b..87626b7ac2 100644 --- a/src/arch/sparc/utility.hh +++ b/src/arch/sparc/utility.hh @@ -43,12 +43,6 @@ namespace SparcISA void copyRegs(ThreadContext *src, ThreadContext *dest); -inline void -advancePC(PCState &pc, const StaticInstPtr &inst) -{ - inst->advancePC(pc); -} - } // namespace SparcISA #endif diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh index 9cd4e943c0..a572637c41 100644 --- a/src/arch/x86/utility.hh +++ b/src/arch/x86/utility.hh @@ -46,12 +46,6 @@ namespace X86ISA { void copyRegs(ThreadContext *src, ThreadContext *dest); - inline void - advancePC(PCState &pc, const StaticInstPtr &inst) - { - inst->advancePC(pc); - } - /** * Reconstruct the rflags register from the internal gem5 register * state. diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index a5a842a50e..87049f0d7f 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -590,7 +590,7 @@ class BaseDynInst : public ExecContext, public RefCounted mispredicted() { TheISA::PCState tempPC = pc; - TheISA::advancePC(tempPC, staticInst); + staticInst->advancePC(tempPC); return !(tempPC == predPC); } diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh index 7dc62e0d82..66d1859ea7 100644 --- a/src/cpu/checker/cpu_impl.hh +++ b/src/cpu/checker/cpu_impl.hh @@ -72,7 +72,7 @@ Checker::advancePC(const Fault &fault) if (curStaticInst->isLastMicroop()) curMacroStaticInst = StaticInst::nullStaticInstPtr; TheISA::PCState pcState = thread->pcState(); - TheISA::advancePC(pcState, curStaticInst); + curStaticInst->advancePC(pcState); thread->pcState(pcState); DPRINTF(Checker, "Advancing PC to %s.\n", thread->pcState()); } diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc index 7575cf9eab..a7f66e2603 100644 --- a/src/cpu/minor/execute.cc +++ b/src/cpu/minor/execute.cc @@ -39,7 +39,6 @@ #include "arch/locked_mem.hh" #include "arch/registers.hh" -#include "arch/utility.hh" #include "cpu/minor/cpu.hh" #include "cpu/minor/exec_context.hh" #include "cpu/minor/fetch1.hh" @@ -239,9 +238,8 @@ Execute::tryToBranch(MinorDynInstPtr inst, Fault fault, BranchData &branch) /* The reason for the branch data we're about to generate, set below */ BranchData::Reason reason = BranchData::NoBranch; - if (fault == NoFault) - { - TheISA::advancePC(target, inst->staticInst); + if (fault == NoFault) { + inst->staticInst->advancePC(target); thread->pcState(target); DPRINTF(Branch, "Advancing current PC from: %s to: %s\n", diff --git a/src/cpu/minor/fetch2.cc b/src/cpu/minor/fetch2.cc index c8901bd9dc..d5a6619051 100644 --- a/src/cpu/minor/fetch2.cc +++ b/src/cpu/minor/fetch2.cc @@ -455,7 +455,7 @@ Fetch2::evaluate() #endif /* Advance PC for the next instruction */ - TheISA::advancePC(fetch_info.pc, decoded_inst); + decoded_inst->advancePC(fetch_info.pc); /* Predict any branches and issue a branch if * necessary */ diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 4eae365445..a435f3e1ba 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -1109,7 +1109,7 @@ DefaultCommit::commitInsts() cpu->traceFunctions(pc[tid].instAddr()); - TheISA::advancePC(pc[tid], head_inst->staticInst); + head_inst->staticInst->advancePC(pc[tid]); // Keep track of the last sequence number commited lastCommitedSeqNum[tid] = head_inst->seqNum; diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 7c54509cd2..ab59fe16a1 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -527,7 +527,7 @@ DefaultFetch::lookupAndUpdateNextPC( bool predict_taken; if (!inst->isControl()) { - TheISA::advancePC(nextPC, inst->staticInst); + inst->staticInst->advancePC(nextPC); inst->setPredTarg(nextPC); inst->setPredTaken(false); return false; diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh index fe50055952..ee2d0e76de 100644 --- a/src/cpu/o3/iew_impl.hh +++ b/src/cpu/o3/iew_impl.hh @@ -460,7 +460,7 @@ DefaultIEW::squashDueToBranch(const DynInstPtr& inst, ThreadID tid) toCommit->branchTaken[tid] = inst->pcState().branching(); TheISA::PCState pc = inst->pcState(); - TheISA::advancePC(pc, inst->staticInst); + inst->staticInst->advancePC(pc); toCommit->pc[tid] = pc; toCommit->mispredictInst[tid] = inst; diff --git a/src/cpu/pred/bpred_unit.cc b/src/cpu/pred/bpred_unit.cc index b25d11577a..a8d25926c1 100644 --- a/src/cpu/pred/bpred_unit.cc +++ b/src/cpu/pred/bpred_unit.cc @@ -227,7 +227,7 @@ BPredUnit::predict(const StaticInstPtr &inst, const InstSeqNum &seqNum, RAS[tid].pop(); predict_record.pushedRAS = false; } - TheISA::advancePC(target, inst); + inst->advancePC(target); } } else { predict_record.wasIndirect = true; @@ -256,7 +256,7 @@ BPredUnit::predict(const StaticInstPtr &inst, const InstSeqNum &seqNum, RAS[tid].pop(); predict_record.pushedRAS = false; } - TheISA::advancePC(target, inst); + inst->advancePC(target); } iPred->recordIndirect(pc.instAddr(), target.instAddr(), seqNum, tid); @@ -266,7 +266,7 @@ BPredUnit::predict(const StaticInstPtr &inst, const InstSeqNum &seqNum, if (inst->isReturn()) { predict_record.wasReturn = true; } - TheISA::advancePC(target, inst); + inst->advancePC(target); } predict_record.target = target.instAddr(); diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 0941388f73..fe3e34d1e7 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -41,7 +41,6 @@ #include "cpu/simple/base.hh" -#include "arch/utility.hh" #include "base/cprintf.hh" #include "base/inifile.hh" #include "base/loader/symtab.hh" @@ -481,7 +480,7 @@ BaseSimpleCPU::advancePC(const Fault &fault) if (curStaticInst->isLastMicroop()) curMacroStaticInst = StaticInst::nullStaticInstPtr; TheISA::PCState pcState = thread->pcState(); - TheISA::advancePC(pcState, curStaticInst); + curStaticInst->advancePC(pcState); thread->pcState(pcState); } }