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arch,cpu,sim: Move the null and nop StaticInstPtrs to their own files.

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The nullStaticInstPtr was low overhead, but the nopStaticInstPtr needed
an actual StaticInst implementation it could point to, and that brought
with it some (minor) additional dependencies. Specifically, the
implementation of advancePC needs the definition of TheISA::PCState,
while all other signatures/impementations in StaticInst are already
passing around that type by reference or could be made to, reducing
dependencies further.

Change-Id: I9ac6a6e5a3106858ea1fc727648f61dc39738a59
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42968
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-03-15 02:43:38 -07:00
parent 96229439e6
commit 14f14f9a62
21 changed files with 245 additions and 100 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
src/arch/arm/faults.hh
View File

@@ -46,6 +46,7 @@
#include "arch/arm/regs/misc.hh"
#include "arch/arm/types.hh"
#include "base/logging.hh"
#include "cpu/null_static_inst.hh"
#include "sim/faults.hh"
#include "sim/full_system.hh"
@@ -221,9 +222,9 @@ class ArmFault : public FaultBase
MiscRegIndex getFaultAddrReg64() const;
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr) override;
nullStaticInstPtr) override;
void invoke64(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
nullStaticInstPtr);
void update(ThreadContext *tc);
bool isResetSPSR(){ return bStep; }
@@ -295,7 +296,7 @@ class Reset : public ArmFaultVals<Reset>
public:
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr) override;
nullStaticInstPtr) override;
};
class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
@@ -323,7 +324,7 @@ class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
{}
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr) override;
nullStaticInstPtr) override;
bool routeToHyp(ThreadContext *tc) const override;
ExceptionClass ec(ThreadContext *tc) const override;
uint32_t iss() const override;
@@ -344,7 +345,7 @@ class SupervisorCall : public ArmFaultVals<SupervisorCall>
}
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr) override;
nullStaticInstPtr) override;
bool routeToHyp(ThreadContext *tc) const override;
ExceptionClass ec(ThreadContext *tc) const override;
uint32_t iss() const override;
@@ -361,7 +362,7 @@ class SecureMonitorCall : public ArmFaultVals<SecureMonitorCall>
}
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr) override;
nullStaticInstPtr) override;
ExceptionClass ec(ThreadContext *tc) const override;
uint32_t iss() const override;
uint32_t vectorCatchFlag() const override { return 0x00000400; }
@@ -467,7 +468,7 @@ class AbortFault : public ArmFaultVals<T>
bool getFaultVAddr(Addr &va) const override;
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr) override;
nullStaticInstPtr) override;
FSR getFsr(ThreadContext *tc) const override;
uint8_t getFaultStatusCode(ThreadContext *tc) const;
@@ -590,7 +591,7 @@ class PCAlignmentFault : public ArmFaultVals<PCAlignmentFault>
PCAlignmentFault(Addr _faultPC) : faultPC(_faultPC)
{}
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr) override;
nullStaticInstPtr) override;
bool routeToHyp(ThreadContext *tc) const override;
};
@@ -608,7 +609,7 @@ class SystemError : public ArmFaultVals<SystemError>
public:
SystemError();
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr) override;
nullStaticInstPtr) override;
bool routeToMonitor(ThreadContext *tc) const override;
bool routeToHyp(ThreadContext *tc) const override;
};
@@ -629,7 +630,7 @@ class HardwareBreakpoint : public ArmFaultVals<HardwareBreakpoint>
Addr vAddr;
public:
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr) override;
nullStaticInstPtr) override;
HardwareBreakpoint(Addr _vaddr, uint32_t _iss);
bool routeToHyp(ThreadContext *tc) const override;
ExceptionClass ec(ThreadContext *tc) const override;
@@ -645,7 +646,7 @@ class Watchpoint : public ArmFaultVals<Watchpoint>
public:
Watchpoint(ExtMachInst _mach_inst, Addr _vaddr, bool _write, bool _cm);
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr) override;
nullStaticInstPtr) override;
bool routeToHyp(ThreadContext *tc) const override;
uint32_t iss() const override;
ExceptionClass ec(ThreadContext *tc) const override;
@@ -671,7 +672,7 @@ class ArmSev : public ArmFaultVals<ArmSev>
public:
ArmSev () {}
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr) override;
nullStaticInstPtr) override;
};
/// Illegal Instruction Set State fault (AArch64 only)

5
src/arch/generic/debugfaults.hh
View File

@@ -41,6 +41,7 @@
#include <string>
#include "base/logging.hh"
#include "cpu/null_static_inst.hh"
#include "cpu/thread_context.hh"
#include "sim/faults.hh"
@@ -74,7 +75,7 @@ class M5DebugFault : public FaultBase
void
invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr) override
nullStaticInstPtr) override
{
debugFunc();
advancePC(tc, inst);
@@ -106,7 +107,7 @@ class M5DebugOnceFault : public M5DebugFault
void
invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr) override
nullStaticInstPtr) override
{
if (!once) {
once = true;

15
src/arch/mips/faults.hh
View File

@@ -32,6 +32,7 @@
#include "arch/mips/pra_constants.hh"
#include "arch/mips/regs/misc.hh"
#include "cpu/null_static_inst.hh"
#include "cpu/thread_context.hh"
#include "debug/MipsPRA.hh"
#include "sim/faults.hh"
@@ -99,7 +100,7 @@ class MipsFaultBase : public FaultBase
}
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
nullStaticInstPtr);
};
template <typename T>
@@ -131,7 +132,7 @@ class ResetFault : public MipsFault<ResetFault>
{
public:
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
nullStaticInstPtr);
};
@@ -139,14 +140,14 @@ class SoftResetFault : public MipsFault<SoftResetFault>
{
public:
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
nullStaticInstPtr);
};
class NonMaskableInterrupt : public MipsFault<NonMaskableInterrupt>
{
public:
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
nullStaticInstPtr);
};
class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
@@ -159,7 +160,7 @@ class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
void
invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr)
nullStaticInstPtr)
{
MipsFault<CoprocessorUnusableFault>::invoke(tc, inst);
if (FullSystem) {
@@ -194,7 +195,7 @@ class AddressFault : public MipsFault<T>
void
invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr)
nullStaticInstPtr)
{
MipsFault<T>::invoke(tc, inst);
if (FullSystem)
@@ -247,7 +248,7 @@ class TlbFault : public AddressFault<T>
void
invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr)
nullStaticInstPtr)
{
if (FullSystem) {
DPRINTF(MipsPRA, "Fault %s encountered.\n", this->name());

3
src/arch/riscv/faults.hh
View File

@@ -35,6 +35,7 @@
#include "arch/riscv/isa.hh"
#include "arch/riscv/registers.hh"
#include "cpu/null_static_inst.hh"
#include "cpu/thread_context.hh"
#include "sim/faults.hh"
@@ -121,7 +122,7 @@ class Reset : public FaultBase
FaultName name() const override { return _name; }
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr) override;
nullStaticInstPtr) override;
};
class InterruptFault : public RiscvFault

15
src/arch/sparc/faults.hh
View File

@@ -29,6 +29,7 @@
#ifndef __SPARC_FAULTS_HH__
#define __SPARC_FAULTS_HH__
#include "cpu/null_static_inst.hh"
#include "cpu/static_inst.hh"
#include "sim/faults.hh"
@@ -69,7 +70,7 @@ class SparcFaultBase : public FaultBase
{}
};
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
nullStaticInstPtr);
virtual TrapType trapType() = 0;
virtual FaultPriority priority() = 0;
virtual FaultStat & countStat() = 0;
@@ -98,7 +99,7 @@ class PowerOnReset : public SparcFault<PowerOnReset>
{
public:
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
nullStaticInstPtr);
};
class WatchDogReset : public SparcFault<WatchDogReset> {};
@@ -212,7 +213,7 @@ class FastInstructionAccessMMUMiss :
FastInstructionAccessMMUMiss() : vaddr(0)
{}
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
nullStaticInstPtr);
};
class FastDataAccessMMUMiss : public SparcFault<FastDataAccessMMUMiss>
@@ -225,7 +226,7 @@ class FastDataAccessMMUMiss : public SparcFault<FastDataAccessMMUMiss>
FastDataAccessMMUMiss() : vaddr(0)
{}
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
nullStaticInstPtr);
};
class FastDataAccessProtection : public SparcFault<FastDataAccessProtection> {};
@@ -244,7 +245,7 @@ class SpillNNormal : public EnumeratedFault<SpillNNormal>
SpillNNormal(uint32_t n) : EnumeratedFault<SpillNNormal>(n) {;}
// These need to be handled specially to enable spill traps in SE
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
nullStaticInstPtr);
};
class SpillNOther : public EnumeratedFault<SpillNOther>
@@ -261,7 +262,7 @@ class FillNNormal : public EnumeratedFault<FillNNormal>
{}
// These need to be handled specially to enable fill traps in SE
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
nullStaticInstPtr);
};
class FillNOther : public EnumeratedFault<FillNOther>
@@ -278,7 +279,7 @@ class TrapInstruction : public EnumeratedFault<TrapInstruction>
{}
// In SE, trap instructions are requesting services from the OS.
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
nullStaticInstPtr);
};
/*

17
src/arch/x86/faults.hh
View File

@@ -43,6 +43,7 @@
#include "arch/x86/tlb.hh"
#include "base/bitunion.hh"
#include "base/logging.hh"
#include "cpu/null_static_inst.hh"
#include "sim/faults.hh"
namespace X86ISA
@@ -69,7 +70,7 @@ class X86FaultBase : public FaultBase
virtual bool isSoft() { return false; }
void invoke(ThreadContext *tc, const StaticInstPtr &inst=
StaticInst::nullStaticInstPtr) override;
nullStaticInstPtr) override;
virtual std::string describe() const;
@@ -98,7 +99,7 @@ class X86Trap : public X86FaultBase
using X86FaultBase::X86FaultBase;
void invoke(ThreadContext *tc, const StaticInstPtr &inst=
StaticInst::nullStaticInstPtr) override;
nullStaticInstPtr) override;
};
// Base class for x86 aborts which seem to be catastrophic failures.
@@ -108,7 +109,7 @@ class X86Abort : public X86FaultBase
using X86FaultBase::X86FaultBase;
void invoke(ThreadContext *tc, const StaticInstPtr &inst=
StaticInst::nullStaticInstPtr) override;
nullStaticInstPtr) override;
};
// Base class for x86 interrupts.
@@ -129,7 +130,7 @@ class UnimpInstFault : public FaultBase
void
invoke(ThreadContext *tc, const StaticInstPtr &inst=
StaticInst::nullStaticInstPtr) override
nullStaticInstPtr) override
{
panic("Unimplemented instruction!");
}
@@ -211,7 +212,7 @@ class InvalidOpcode : public X86Fault
InvalidOpcode() : X86Fault("Invalid-Opcode", "#UD", 6) {}
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr) override;
nullStaticInstPtr) override;
};
class DeviceNotAvailable : public X86Fault
@@ -290,7 +291,7 @@ class PageFault : public X86Fault
void
invoke(ThreadContext *tc, const StaticInstPtr &inst=
StaticInst::nullStaticInstPtr);
nullStaticInstPtr);
virtual std::string describe() const;
};
@@ -351,7 +352,7 @@ class InitInterrupt : public X86Interrupt
{}
void invoke(ThreadContext *tc, const StaticInstPtr &inst=
StaticInst::nullStaticInstPtr) override;
nullStaticInstPtr) override;
};
class StartupInterrupt : public X86Interrupt
@@ -362,7 +363,7 @@ class StartupInterrupt : public X86Interrupt
{}
void invoke(ThreadContext *tc, const StaticInstPtr &inst=
StaticInst::nullStaticInstPtr) override;
nullStaticInstPtr) override;
};
class SoftwareInterrupt : public X86Interrupt

2
src/cpu/SConscript
View File

@@ -102,6 +102,8 @@ Source('exetrace.cc')
Source('func_unit.cc')
Source('inteltrace.cc')
Source('nativetrace.cc')
Source('nop_static_inst.cc')
Source('null_static_inst.cc')
Source('profile.cc')
Source('reg_class.cc')
Source('static_inst.cc')

9
src/cpu/checker/cpu_impl.hh
View File

@@ -48,6 +48,7 @@
#include "base/refcnt.hh"
#include "config/the_isa.hh"
#include "cpu/exetrace.hh"
#include "cpu/null_static_inst.hh"
#include "cpu/reg_class.hh"
#include "cpu/simple_thread.hh"
#include "cpu/static_inst.hh"
@@ -63,13 +64,13 @@ void
Checker<Impl>::advancePC(const Fault &fault)
{
if (fault != NoFault) {
curMacroStaticInst = StaticInst::nullStaticInstPtr;
curMacroStaticInst = nullStaticInstPtr;
fault->invoke(tc, curStaticInst);
thread->decoder.reset();
} else {
if (curStaticInst) {
if (curStaticInst->isLastMicroop())
curMacroStaticInst = StaticInst::nullStaticInstPtr;
curMacroStaticInst = nullStaticInstPtr;
TheISA::PCState pcState = thread->pcState();
curStaticInst->advancePC(pcState);
thread->pcState(pcState);
@@ -110,7 +111,7 @@ Checker<Impl>::handlePendingInt()
}
boundaryInst = NULL;
thread->decoder.reset();
curMacroStaticInst = StaticInst::nullStaticInstPtr;
curMacroStaticInst = nullStaticInstPtr;
}
template <class Impl>
@@ -384,7 +385,7 @@ Checker<Impl>::verify(const DynInstPtr &completed_inst)
willChangePC = true;
newPCState = thread->pcState();
DPRINTF(Checker, "Fault, PC is now %s\n", newPCState);
curMacroStaticInst = StaticInst::nullStaticInstPtr;
curMacroStaticInst = nullStaticInstPtr;
}
} else {
advancePC(fault);

3
src/cpu/minor/dyn_inst.cc
View File

@@ -44,6 +44,7 @@
#include "arch/registers.hh"
#include "cpu/base.hh"
#include "cpu/minor/trace.hh"
#include "cpu/null_static_inst.hh"
#include "cpu/reg_class.hh"
#include "debug/MinorExecute.hh"
#include "enums/OpClass.hh"
@@ -79,7 +80,7 @@ void
MinorDynInst::init()
{
if (!bubbleInst) {
bubbleInst = new MinorDynInst(StaticInst::nullStaticInstPtr);
bubbleInst = new MinorDynInst(nullStaticInstPtr);
assert(bubbleInst->isBubble());
/* Make bubbleInst immortal */
bubbleInst->incref();

4
src/cpu/minor/fetch2.cc
View File

@@ -43,6 +43,7 @@
#include "base/logging.hh"
#include "base/trace.hh"
#include "cpu/minor/pipeline.hh"
#include "cpu/null_static_inst.hh"
#include "cpu/pred/bpred_unit.hh"
#include "debug/Branch.hh"
#include "debug/Fetch.hh"
@@ -355,8 +356,7 @@ Fetch2::evaluate()
/* Make a new instruction and pick up the line, stream,
* prediction, thread ids from the incoming line */
dyn_inst = new MinorDynInst(
StaticInst::nullStaticInstPtr, line_in->id);
dyn_inst = new MinorDynInst(nullStaticInstPtr, line_in->id);
/* Fetch and prediction sequence numbers originate here */
dyn_inst->id.fetchSeqNum = fetch_info.fetchSeqNum;

63
src/cpu/nop_static_inst.cc Normal file
View File

@@ -0,0 +1,63 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "cpu/nop_static_inst.hh"
#include "cpu/static_inst.hh"
namespace
{
class NopStaticInst : public StaticInst
{
public:
NopStaticInst() : StaticInst("gem5 nop", No_OpClass) {}
Fault
execute(ExecContext *xc, Trace::InstRecord *traceData) const override
{
return NoFault;
}
void
advancePC(TheISA::PCState &pcState) const override
{
pcState.advance();
}
std::string
generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const override
{
return mnemonic;
}
};
}
StaticInstPtr nopStaticInstPtr = new NopStaticInst;

36
src/cpu/nop_static_inst.hh Normal file
View File

@@ -0,0 +1,36 @@
/*
* Copyright 2021 Google Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __CPU_NOP_STATIC_INST_HH__
#define __CPU_NOP_STATIC_INST_HH__
#include "cpu/static_inst_fwd.hh"
/// Pointer to a statically allocated generic "nop" instruction object.
extern StaticInstPtr nopStaticInstPtr;
#endif // __CPU_NOP_STATIC_INST_HH__

33
src/cpu/null_static_inst.cc Normal file
View File

@@ -0,0 +1,33 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "cpu/null_static_inst.hh"
#include "cpu/static_inst.hh"
const StaticInstPtr nullStaticInstPtr;

36
src/cpu/null_static_inst.hh Normal file
View File

@@ -0,0 +1,36 @@
/*
* Copyright 2021 Google Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __CPU_NULL_STATIC_INST_HH__
#define __CPU_NULL_STATIC_INST_HH__
#include "cpu/static_inst_fwd.hh"
/// Statically allocated null StaticInstPtr.
extern const StaticInstPtr nullStaticInstPtr;
#endif // __CPU_NULL_STATIC_INST_HH__

8
src/cpu/o3/commit_impl.hh
View File

@@ -48,11 +48,12 @@
#include "base/loader/symtab.hh"
#include "base/logging.hh"
#include "config/the_isa.hh"
#include "cpu/base.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/exetrace.hh"
#include "cpu/null_static_inst.hh"
#include "cpu/o3/commit.hh"
#include "cpu/o3/thread_state.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "cpu/timebuf.hh"
#include "debug/Activity.hh"
#include "debug/Commit.hh"
@@ -1296,8 +1297,7 @@ DefaultCommit<Impl>::commitHead(const DynInstPtr &head_inst, unsigned inst_num)
// prevents external agents from changing any specific state
// that the trap need.
cpu->trap(inst_fault, tid,
head_inst->notAnInst() ?
StaticInst::nullStaticInstPtr :
head_inst->notAnInst() ? nullStaticInstPtr :
head_inst->staticInst);
// Exit state update mode to avoid accidental updating.

9
src/cpu/o3/fetch_impl.hh
View File

@@ -53,9 +53,11 @@
#include "base/types.hh"
#include "config/the_isa.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "cpu/nop_static_inst.hh"
#include "cpu/o3/cpu.hh"
#include "cpu/o3/fetch.hh"
#include "cpu/exetrace.hh"
#include "cpu/o3/isa_specific.hh"
#include "debug/Activity.hh"
#include "debug/Drain.hh"
#include "debug/Fetch.hh"
@@ -68,7 +70,6 @@
#include "sim/eventq.hh"
#include "sim/full_system.hh"
#include "sim/system.hh"
#include "cpu/o3/isa_specific.hh"
template<class Impl>
DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, const DerivO3CPUParams &params)
@@ -698,8 +699,8 @@ DefaultFetch<Impl>::finishTranslation(const Fault &fault,
DPRINTF(Fetch, "[tid:%i] Translation faulted, building noop.\n", tid);
// We will use a nop in ordier to carry the fault.
DynInstPtr instruction = buildInst(tid, StaticInst::nopStaticInstPtr,
NULL, fetchPC, fetchPC, false);
DynInstPtr instruction = buildInst(tid, nopStaticInstPtr, nullptr,
fetchPC, fetchPC, false);
instruction->setNotAnInst();
instruction->setPredTarg(fetchPC);

3
src/cpu/pred/tage_base.hh
View File

@@ -51,6 +51,7 @@
#include <vector>
#include "base/statistics.hh"
#include "cpu/null_static_inst.hh"
#include "cpu/static_inst.hh"
#include "params/TAGEBase.hh"
#include "sim/sim_object.hh"
@@ -287,7 +288,7 @@ class TAGEBase : public SimObject
virtual void updateHistories(
ThreadID tid, Addr branch_pc, bool taken, BranchInfo* b,
bool speculative,
const StaticInstPtr & inst = StaticInst::nullStaticInstPtr,
const StaticInstPtr & inst = nullStaticInstPtr,
Addr target = MaxAddr);
/**

5
src/cpu/simple/base.cc
View File

@@ -53,6 +53,7 @@
#include "cpu/checker/cpu.hh"
#include "cpu/checker/thread_context.hh"
#include "cpu/exetrace.hh"
#include "cpu/null_static_inst.hh"
#include "cpu/pred/bpred_unit.hh"
#include "cpu/simple/exec_context.hh"
#include "cpu/simple_thread.hh"
@@ -472,13 +473,13 @@ BaseSimpleCPU::advancePC(const Fault &fault)
//Since we're moving to a new pc, zero out the offset
t_info.fetchOffset = 0;
if (fault != NoFault) {
curMacroStaticInst = StaticInst::nullStaticInstPtr;
curMacroStaticInst = nullStaticInstPtr;
fault->invoke(threadContexts[curThread], curStaticInst);
thread->decoder.reset();
} else {
if (curStaticInst) {
if (curStaticInst->isLastMicroop())
curMacroStaticInst = StaticInst::nullStaticInstPtr;
curMacroStaticInst = nullStaticInstPtr;
TheISA::PCState pcState = thread->pcState();
curStaticInst->advancePC(pcState);
thread->pcState(pcState);

34
src/cpu/static_inst.cc
View File

@@ -30,40 +30,6 @@
#include <iostream>
#include "sim/core.hh"
namespace {
class NopStaticInst : public StaticInst
{
public:
NopStaticInst() : StaticInst("gem5 nop", No_OpClass) {}
Fault
execute(ExecContext *xc, Trace::InstRecord *traceData) const override
{
return NoFault;
}
void
advancePC(TheISA::PCState &pcState) const override
{
pcState.advance();
}
std::string
generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const override
{
return mnemonic;
}
};
}
StaticInstPtr StaticInst::nullStaticInstPtr;
StaticInstPtr StaticInst::nopStaticInstPtr = new NopStaticInst;
bool
StaticInst::hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
TheISA::PCState &tgt) const

3
src/cpu/static_inst.hh
View File

@@ -251,9 +251,6 @@ class StaticInst : public RefCounted, public StaticInstFlags
/// Pointer to a statically allocated "null" instruction object.
static StaticInstPtr nullStaticInstPtr;
/// Pointer to a statically allocated generic "nop" instruction object.
static StaticInstPtr nopStaticInstPtr;
virtual uint64_t getEMI() const { return 0; }
protected:

17
src/sim/faults.hh
View File

@@ -42,6 +42,7 @@
#define __FAULTS_HH__
#include "base/types.hh"
#include "cpu/null_static_inst.hh"
#include "cpu/static_inst.hh"
#include "mem/htm.hh"
#include "sim/stats.hh"
@@ -56,7 +57,7 @@ class FaultBase
public:
virtual FaultName name() const = 0;
virtual void invoke(ThreadContext * tc, const StaticInstPtr &inst=
StaticInst::nullStaticInstPtr);
nullStaticInstPtr);
virtual ~FaultBase() {};
};
@@ -73,7 +74,7 @@ class UnimpFault : public FaultBase
return "Unimplemented simulator feature";
}
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr) override;
nullStaticInstPtr) override;
};
// A fault to trigger a system call in SE mode.
@@ -82,7 +83,7 @@ class SESyscallFault : public FaultBase
const char *name() const override { return "syscall_fault"; }
void invoke(ThreadContext *tc, const StaticInstPtr &inst=
StaticInst::nullStaticInstPtr) override;
nullStaticInstPtr) override;
};
class ReExec : public FaultBase
@@ -90,7 +91,7 @@ class ReExec : public FaultBase
public:
virtual FaultName name() const override { return "Re-execution fault"; }
void invoke(ThreadContext *tc, const StaticInstPtr &inst=
StaticInst::nullStaticInstPtr) override;
nullStaticInstPtr) override;
};
/*
@@ -106,7 +107,7 @@ class SyscallRetryFault : public FaultBase
FaultName name() const override { return "System call retry fault"; }
SyscallRetryFault() {}
void invoke(ThreadContext *tc, const StaticInstPtr &inst=
StaticInst::nullStaticInstPtr) override;
nullStaticInstPtr) override;
};
class GenericPageTableFault : public FaultBase
@@ -117,7 +118,7 @@ class GenericPageTableFault : public FaultBase
FaultName name() const override { return "Generic page table fault"; }
GenericPageTableFault(Addr va) : vaddr(va) {}
void invoke(ThreadContext *tc, const StaticInstPtr &inst=
StaticInst::nullStaticInstPtr) override;
nullStaticInstPtr) override;
Addr getFaultVAddr() const { return vaddr; }
};
@@ -129,7 +130,7 @@ class GenericAlignmentFault : public FaultBase
FaultName name() const override { return "Generic alignment fault"; }
GenericAlignmentFault(Addr va) : vaddr(va) {}
void invoke(ThreadContext *tc, const StaticInstPtr &inst=
StaticInst::nullStaticInstPtr) override;
nullStaticInstPtr) override;
Addr getFaultVAddr() const { return vaddr; }
};
@@ -149,7 +150,7 @@ class GenericHtmFailureFault : public FaultBase
uint64_t getHtmUid() const { return htmUid; }
HtmFailureFaultCause getHtmFailureFaultCause() const { return cause; }
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr) override;
nullStaticInstPtr) override;
};
#endif // __FAULTS_HH__