arch-power: Fix power build.

Change-Id: I38b1d9e4360a8eb1cfc80bee369b5aa503dd6db2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44585
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
This commit is contained in:
Gabe Black
2021-04-16 23:09:17 -07:00
parent 3bd72b42d0
commit 96229439e6
4 changed files with 4 additions and 3 deletions

View File

@@ -30,6 +30,7 @@
#define __ARCH_POWER_INSTS_INTEGER_HH__
#include "arch/power/insts/static_inst.hh"
#include "arch/power/regs/misc.hh"
#include "base/bitfield.hh"
#include "base/cprintf.hh"

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@@ -325,7 +325,7 @@ decode OPCODE default Unknown::unknown() {
}
}
Xer xer = XER;
Cr cr = CR;
PowerISA::Cr cr = CR;
cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
CR = cr;
Rsv = 0;

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@@ -37,7 +37,7 @@ let {{
readFPSCRCode = 'Fpscr fpscr = FPSCR;'
computeCR1Code = '''
Cr cr = CR;
PowerISA::Cr cr = CR;
cr.cr1 = (fpscr.fx << 3) | (fpscr.fex << 2) |
(fpscr.vx << 1) | fpscr.ox;
CR = cr;

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@@ -76,7 +76,7 @@ readXERCode = 'Xer xer = XER;'
setXERCode = 'XER = xer;'
computeCR0Code = '''
Cr cr = CR;
PowerISA::Cr cr = CR;
cr.cr0 = makeCRFieldSigned(%(result)s, 0, xer.so);
CR = cr;
'''