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e970ad194e
Correction of timing dependency WR -<> RDA.
2019-10-17 15:47:27 +02:00
5f7cb7a326
Included memspec, dram and checker for GDDR5, GDDR5X and GDDR6.
2019-10-17 15:00:28 +02:00
a3fa363a87
Bugfix for triggering controllerMethod() multiple times at the same time.
2019-10-15 20:26:49 +02:00
2aa5d125c7
Fixed BM deadlock.
2019-10-15 16:09:59 +02:00
04a59c8bd2
Changed MemSpec::getExecutionTime() for different tRCDs.
2019-10-15 16:03:34 +02:00
ed29186adc
Included HBM2 example, fixed fifo strict issue with HBM2's command buses.
2019-10-11 20:35:45 +02:00
f4803f4b8c
Included checker for HBM2.
2019-10-10 18:17:21 +02:00
606d273bee
Included memspec and dram component for HBM2.
2019-10-10 15:21:58 +02:00
256abe449c
Included CheckerWideIO2, tPPD fix in CheckerLPDDR4.
2019-10-09 09:49:46 +02:00
a5b00ea3be
Further inclusion of WideIO2.
2019-10-08 15:27:18 +02:00
65db413a20
Included MemSpecWideIO2, some adaptions for all memspecs.
2019-10-08 14:14:42 +02:00
932027112e
Adapted timing checkers of DDR4 and WideIO to new refresh.
2019-10-07 15:37:23 +02:00
86d5082434
Further improvements in refresh managers.
2019-10-06 20:54:30 +02:00
d1f6bc6233
Improved flexible refresh, implemented first version of bankwise flexible refresh.
2019-10-06 18:56:13 +02:00
aa6a205872
Implemented first version of flexible refresh (only REFA).
2019-10-04 21:46:29 +02:00
b22cfa4a94
Improved controller method, some code and output formatting.
2019-10-03 19:04:34 +02:00
6e71e435c5
Implemented first version of new bankwise refresh.
2019-10-02 21:55:19 +02:00
4328f4550b
Updated CheckerLPDDR4 for new refresh, some renaming.
2019-10-02 21:54:05 +02:00
f4a018cfb3
Fixed display of rankwise commands.
2019-10-02 17:46:37 +02:00
abb9a37096
Added numberOfRanks to database.
2019-10-02 16:08:10 +02:00
7868af4b51
Implemented first version of new refresh (no REFB).
2019-10-01 20:53:01 +02:00
04ec683b57
Included LPDDR4 timing checker and example.
2019-09-26 21:31:17 +02:00
4950a2587e
Included LPDDR4 memspec and Dram, changed structure of MemSpec.h, removed ScheduledCommand.
2019-09-26 16:55:20 +02:00
8b7760a585
LPDDR4 address mapping and memspec.
2019-09-26 16:49:40 +02:00
47949922f3
Included LPDDR4 memspec.
2019-09-26 13:26:17 +02:00
cfbce483bd
Included timing checker for DDR4.
2019-09-24 15:18:37 +02:00
2690755024
Included JEDEC based memspecs, address mapping and simulation for DDR4.
2019-09-24 15:17:25 +02:00
149bfee201
Corrected refresh mode (1x, 2x and 4x) for DDR4.
2019-09-24 15:16:09 +02:00
805490d05c
Correction of address mappings.
2019-09-24 14:14:56 +02:00
fc10f72773
Minor changes in address mapping and configuration.
2019-09-23 22:16:56 +02:00
102b0667fd
Added bankgroups to address decoding.
2019-09-23 20:07:00 +02:00
bda10dca2f
Individual memspec files for different DRAMs.
2019-09-23 14:31:47 +02:00
c1b741d89b
Changed directory of configuration, added attribute unused to suppress warnings.
2019-09-23 13:24:47 +02:00
650e1d405b
Removed ScheduledCommand dependencies.
2019-09-23 10:23:02 +02:00
5fe5529c7c
Included various command lengths.
2019-09-20 17:35:01 +02:00
97542d5f97
Included missing memory allocation in Dram.
2019-09-19 14:46:55 +02:00
d06d9eec2c
Changed data structures of timing checkers from ScheduledCommand to sc_time.
2019-09-19 14:45:38 +02:00
b918f0f9ea
Added ranks to tdb files and TraceAnalyzer.
2019-09-18 18:24:10 +02:00
330b07d0e7
Changed data structures of Address Decoder for speedup.
2019-09-18 16:39:38 +02:00
6eef8ff1e6
Rank inclusion part 2.
2019-09-17 21:31:57 +02:00
5d7495383e
Changed internal data structures from std::map to std::vector for faster access.
2019-09-17 18:16:52 +02:00
3a7557544f
Rank inclusion part 1.
2019-09-16 15:16:14 +02:00
b9700f1ee5
Implemented some basics for ranks.
2019-09-12 14:56:06 +02:00
26c3bd23c1
Changed default colour grouping to phase.
2019-09-12 10:55:59 +02:00
fcde31f041
Included adaptive page policy.
2019-09-11 20:36:45 +02:00
62841a3590
Implemented closed page policy. Fixed bug in trace analyzer tests.
2019-09-11 16:02:36 +02:00
7fd5f05d3e
Renaming of ControllerNew to Controller.
2019-09-11 09:59:51 +02:00
7827a5f869
Added some addressmappings and memspecs for WIDEIO and WIDEIO2.
2019-09-10 15:22:05 +02:00
f40ace826b
Changed DRAMPower submodule commit and branch.
2019-08-26 17:14:23 +02:00
7934d2e160
Renaming libDRAMPowerIF to libDRAMPowerDummy.
2019-08-26 16:26:28 +02:00
2402180a9c
Merge branch 'DRAMSys4.0_ctrl' of https://git.eit.uni-kl.de/ems/astdm/dram.sys into DRAMSys4.0_ctrl
2019-08-25 23:14:19 +02:00
d4943bccc5
Debug Manager cleanup.
2019-08-25 23:13:05 +02:00
98c52b8a3e
Merge remote-tracking branch 'origin/master' into DRAMSys4.0_ctrl
2019-08-23 09:54:56 +02:00
f6072e9d4f
Fixed Memory Leak
2019-08-22 23:11:48 +02:00
d55d801a04
Merge branch 'master' of https://git.eit.uni-kl.de/ems/astdm/dram.sys
2019-08-22 23:03:05 +02:00
a6f679b86b
Add compile flag for macOS
2019-08-22 23:00:38 +02:00
9702d7a8f3
Add compile flag for macOS
2019-08-22 22:59:23 +02:00
6388b3d75c
DRAM command was not set in trace recorder
2019-08-22 22:40:28 +02:00
f5f3c729e0
Temporary fix of memory leak.
2019-08-22 22:16:33 +02:00
1fc5f3bf88
Some phase renaming in TraceAnalyzer.
2019-08-20 14:56:45 +02:00
4881b8ae76
Implemented initial version of timing checker for WideIO.
2019-08-20 10:58:28 +02:00
2ef1c2b189
Removed RefreshCheckerIF, RefreshCheckerDummy is now used as base class.
2019-08-20 10:11:56 +02:00
baa976dac4
Removed unused commands and extended protocol phases.
2019-08-20 09:51:55 +02:00
cbeaef32de
Removed specific memspec dependency in RefreshManager, changed RefreshChecker to RefreshCheckerDDR3.
2019-08-19 16:17:31 +02:00
7c87b954ec
Removed different refresh timings for different banks, removed ORGR parameters from mcconfigs.
2019-08-19 15:11:49 +02:00
35af025d4c
Removed unused configuration parameters, moved some currents and voltages to specific memspecs.
2019-08-19 13:51:27 +02:00
3f7296f2a5
Removed RGR timing parameters.
2019-08-19 11:16:27 +02:00
8115aba222
Fixed wrong PRE -<> PREA test in TraceAnalyzer.
2019-08-18 19:56:17 +02:00
4d936892d9
Included DRAMPower dummy, it can now be switched on and off again.
2019-08-18 19:23:53 +02:00
7b8bb86620
Removed old timing parameters, moved DramPower configuration to specific Drams.
2019-08-15 14:55:55 +02:00
7d675a9837
Renaming and minor improvements.
2019-08-14 21:19:42 +02:00
31101a0827
Finished bankwise refresh.
2019-08-14 20:19:27 +02:00
47ee187bc3
Working on RefreshManagerBankwise.
2019-08-14 13:48:04 +02:00
0918a78648
Included GenericController for polymorphism.
2019-08-14 09:44:24 +02:00
c2022667c5
Included files for RefreshManagerBankwise.
2019-08-13 14:23:44 +02:00
3b26997ea4
Updated structure of RefreshManager for bankwise refresh implementation.
2019-08-13 11:39:15 +02:00
38a099b8e8
Included RefreshChecker for different refresh modes.
2019-08-12 16:41:44 +02:00
e6dc4e7c75
Removed unused files of old controller.
2019-08-12 14:19:22 +02:00
05a8272ee6
Moved bandwidth calculation to GenericController.
2019-08-10 01:01:52 +02:00
dc194781f7
Code formatting.
2019-08-09 23:46:49 +02:00
08dc5e811a
Removed redundant check in controllerMethod.
2019-08-09 23:45:17 +02:00
1dea807da3
Included various events to avoid multiple triggers of controllerMethod at the same time.
2019-08-09 19:38:49 +02:00
2e40894097
Included RefreshManagerIF and RefreshManagerDummy to disable refresh.
2019-08-09 13:39:02 +02:00
1bd322e576
Fixed "PREA if all banks are precharged" issue.
2019-08-09 10:35:17 +02:00
88f57dd88f
Included refresh.
2019-08-08 16:22:33 +02:00
ca36faa403
Changed printDebugMessage into macro to turn it off completely for speedup.
2019-08-08 09:45:22 +02:00
c93a11fbf5
Code formatting.
2019-08-02 10:44:49 +02:00
85e9fc6930
Included bandwidth calculation. Fixed bug (RD/WR from wrong row).
2019-08-01 16:26:57 +02:00
6a66c89130
Included GenericController for verilator compatibility.
2019-08-01 11:00:31 +02:00
36373c9cce
Gave all sc_modules names. Added missing virtual destructors in different DRAMs.
2019-07-31 15:20:13 +02:00
ed96f9fb54
Added new CheckerDDR3, changed checker type in controller to CheckerIF for polymorphism.
2019-07-30 16:25:05 +02:00
1053f7c1b7
Created CheckerIF, removed old CheckerDDR3.
2019-07-30 16:03:49 +02:00
b9f0c31ddf
Moved controller state into timing checker. Inserted preambles.
2019-07-30 15:14:24 +02:00
b477424a98
Bugfix: Commands on one bank can overlap now.
2019-07-30 13:30:59 +02:00
fb9abb9cee
Changed type of payloadID to uint64_t for overflow prevention.
2019-07-29 20:55:40 +02:00
4fa59c2410
Included ControllerRecordable for disabling of trace recording.
2019-07-29 16:44:14 +02:00
91755962a2
Improvement in timing checker: additional map instead of for loops.
2019-07-29 14:17:03 +02:00
de650810dd
Changed interface of scheduler, small bugfix (wrong debug message in Controller).
2019-07-29 11:05:03 +02:00
dbcdf3f61d
Included FAW check.
2019-07-28 22:53:27 +02:00
42344ce87f
Removed lastDataStrobeCommands in ControllerState, removed unused methods in timing checker.
2019-07-28 21:50:28 +02:00
Lukas Steiner (2)