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Removed different refresh timings for different banks, removed ORGR parameters from mcconfigs.

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This commit is contained in:
Lukas Steiner (2)
2019-08-19 15:11:49 +02:00
parent 35af025d4c
commit 7c87b954ec
17 changed files with 19 additions and 161 deletions
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7
DRAMSys/library/resources/configs/mcconfigs/fifo.xml
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@@ -34,13 +34,6 @@
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>

7
DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml
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@@ -34,13 +34,6 @@
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>

7
DRAMSys/library/resources/configs/mcconfigs/fifo_ecc.xml
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@@ -34,13 +34,6 @@
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>

7
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml
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@@ -34,13 +34,6 @@
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>

7
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16.xml
View File

@@ -33,13 +33,6 @@
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>

7
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16_close_page.xml
View File

@@ -33,13 +33,6 @@
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>

7
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml
View File

@@ -34,13 +34,6 @@
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>

16
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16.xml
View File

@@ -17,22 +17,6 @@
<ControllerCoreRGR value="1"/>
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<ControllerCoreRGRRowInc value="1"/>
<!-- New commands using starndard timing values -->
<!--
<ControllerCoreRGRtRASBInClkCycles value="34"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="8"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="8"/>
<ControllerCoreRGRtRPBInClkCycles value="18"/>
<ControllerCoreRGRtRCBInClkCycles value="52"/>
<ControllerCoreRGRtFAWBInClkCycles value="37"/>
-->
<!-- New commands using optimal timing values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Select the banks you want to refresh. 1: yes, 0: no (max. 16 banks) -->
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>

7
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16_close_page.xml
View File

@@ -33,13 +33,6 @@
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>

7
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rp.xml
View File

@@ -34,13 +34,6 @@
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>

7
DRAMSys/library/resources/configs/mcconfigs/grp.xml
View File

@@ -34,13 +34,6 @@
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>

7
DRAMSys/library/resources/configs/mcconfigs/par_bs.xml
View File

@@ -34,13 +34,6 @@
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>

7
DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml
View File

@@ -33,13 +33,6 @@
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>

7
DRAMSys/library/resources/configs/mcconfigs/sms.xml
View File

@@ -34,13 +34,6 @@
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>

46
DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp
View File

@@ -115,17 +115,16 @@ void ConfigurationLoader::loadMCConfig(Configuration &config,
void ConfigurationLoader::loadMCConfig(Configuration &config,
XMLElement *mcconfig)
{
if (mcconfig->Attribute("src")) {
if (mcconfig->Attribute("src"))
{
XMLDocument doc;
string src(mcconfig->Attribute("src"));
config.mcconfigUri = src;
loadXML(src, doc);
loadMCConfig(config, doc.FirstChildElement("mcconfig"));
} else {
loadConfig(config, mcconfig);
}
else
loadConfig(config, mcconfig);
}
void ConfigurationLoader::loadMemSpec(Configuration &config, string memspecUri)
@@ -143,32 +142,30 @@ void ConfigurationLoader::loadMemSpec(Configuration &config,
string memoryType = queryStringParameter(memspec, "memoryType");
if (memoryType == "DDR4")
{
Configuration::getInstance().memSpec = new MemSpecDDR4;
Configuration::getInstance().memSpec = new MemSpecDDR4();
loadCommons(config, memspec);
loadDDR4(config, memspec);
}
else if (memoryType == "DDR3")
{
Configuration::getInstance().memSpec = new MemSpecDDR3;
Configuration::getInstance().memSpec = new MemSpecDDR3();
loadCommons(config, memspec);
loadDDR3(config, memspec);
}
else if (memoryType == "LPDDR4")
{
Configuration::getInstance().memSpec = new MemSpecLPDDR4;
Configuration::getInstance().memSpec = new MemSpecLPDDR4();
loadCommons(config, memspec);
loadLPDDR4(config, memspec);
}
else if (memoryType == "WIDEIO_SDR")
{
Configuration::getInstance().memSpec = new MemSpecWideIO;
Configuration::getInstance().memSpec = new MemSpecWideIO();
loadCommons(config, memspec);
loadWideIO(config, memspec);
}
else
{
reportFatal("ConfigurationLoader", "Unsupported DRAM type");
}
}
void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec)
@@ -181,7 +178,6 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec
// MemArchitecture
XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks");
//memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
memSpec->BurstLength = queryUIntParameter(architecture, "burstLength");
memSpec->DataRate = queryUIntParameter(architecture, "dataRate");
memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
@@ -243,11 +239,6 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec)
memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL");
memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL");
memSpec->refreshTimings.clear();
for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i)
memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC,
memSpec->tREFI);
// Currents and Volatages: TODO Check if this is correct.
XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec");
memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0");
@@ -272,8 +263,8 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec)
sc_time clk = memSpec->clk;
memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD_S");
memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD_L");
memSpec->tFAW = clk * queryUIntParameter(timings, "FAW");
memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
memSpec->tFAW = clk * queryUIntParameter(timings, "FAW");
memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
unsigned refMode = Configuration::getInstance().getRefMode();
if (refMode == 1)
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
@@ -283,7 +274,7 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec)
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC4");
else
SC_REPORT_FATAL("ConfigurationLoader", "Refresh Mode not supported");
memSpec->tRP = clk * queryUIntParameter(timings, "RP");
memSpec->tRP = clk * queryUIntParameter(timings, "RP");
memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD_S");
memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD_L");
memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR_S");
@@ -291,11 +282,6 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec)
memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL");
memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL");
memSpec->refreshTimings.clear();
for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i)
memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC,
memSpec->tREFI);
// Currents and Volatages:
XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec");
memSpec->iDD02 = queryDoubleParameter(powers, "idd02");
@@ -336,11 +322,6 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec)
memSpec->tRP = clk * queryUIntParameter(timings, "RPPB");
memSpec->tRRD = clk * queryUIntParameter(timings, "RRD");
memSpec->refreshTimings.clear();
for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i)
memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFCPB,
memSpec->tREFIPB);
// Currents and Volatages:
XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec");
memSpec->iDD02 = queryDoubleParameter(powers, "idd02");
@@ -373,11 +354,6 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec)
memSpec->tTAW = clk * queryUIntParameter(timings, "TAW");
memSpec->tWTR = clk * queryUIntParameter(timings, "WTR");
memSpec->refreshTimings.clear();
for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i)
memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC,
memSpec->tREFI);
// Currents and Volatages:
XMLElement *powers = memspec->FirstChildElement("mempowerspec");
memSpec->iDD02 = queryDoubleParameter(powers, "idd02");

14
DRAMSys/library/src/controller/core/configuration/MemSpec.cpp
View File

@@ -40,6 +40,8 @@
#include "../../Command.h"
#include "Configuration.h"
using namespace tlm;
const std::vector<Bank> &MemSpec::getBanks() const
{
static std::vector<Bank> banks;
@@ -76,7 +78,7 @@ sc_time MemSpec::getMinExecutionTimeForPowerDownCmd(Command command) const
// Returns the execution time for commands that have a fixed execution time
// TODO: override this method for different MemSpecs?
sc_time MemSpec::getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const
sc_time MemSpec::getExecutionTime(Command command, tlm_generic_payload &) const
{
if (command == Command::PRE || command == Command::PREA)
return tRP;
@@ -93,8 +95,7 @@ sc_time MemSpec::getExecutionTime(Command command, tlm::tlm_generic_payload &pay
else if (command == Command::REFA)
return tRFC;
else if (command == Command::REFB)
return getElementFromMap(refreshTimings,
DramExtension::getExtension(payload).getBank()).tRFC;
return tRFC;
else if (command == Command::PDXA || command == Command::PDXP || command == Command::SREFEX)
return clk;
else
@@ -105,7 +106,7 @@ sc_time MemSpec::getExecutionTime(Command command, tlm::tlm_generic_payload &pay
}
}
sc_time MemSpecLPDDR4::getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const
sc_time MemSpecLPDDR4::getExecutionTime(Command command, tlm_generic_payload &) const
{
if (command == Command::PRE)
return tRP;
@@ -124,10 +125,7 @@ sc_time MemSpecLPDDR4::getExecutionTime(Command command, tlm::tlm_generic_payloa
else if (command == Command::REFA)
return tRFC;
else if (command == Command::REFB)
{
return getElementFromMap(refreshTimings,
DramExtension::getExtension(payload).getBank()).tRFC;
}
return tRFCPB;
else if (command == Command::PDXA || command == Command::PDXP || command == Command::SREFEX)
return clk;
else

13
DRAMSys/library/src/controller/core/configuration/MemSpec.h
View File

@@ -45,15 +45,6 @@
using namespace tlm;
struct RefreshTiming
{
RefreshTiming() {}
RefreshTiming(sc_time tRFC, sc_time tREFI) : tRFC(tRFC), tREFI(tREFI) {}
sc_time tRFC;
sc_time tREFI;
};
struct MemSpec
{
const std::vector<Bank> &getBanks() const;
@@ -110,8 +101,8 @@ struct MemSpec
double iDD6;
double vDD;
std::map<Bank, RefreshTiming> refreshTimings;
//ensure that map is populated completely in memspecloader
// For different refresh frequencies on different banks, not implemented
//std::map<Bank, sc_time> refreshTimings;
virtual ~MemSpec() {}
};