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Removed unused configuration parameters, moved some currents and voltages to specific memspecs.

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This commit is contained in:
Lukas Steiner (2)
2019-08-19 13:51:27 +02:00
parent 3f7296f2a5
commit 35af025d4c
5 changed files with 100 additions and 116 deletions
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92
DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp
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@@ -181,7 +181,7 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec
// MemArchitecture
XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks");
memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
//memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
memSpec->BurstLength = queryUIntParameter(architecture, "burstLength");
memSpec->DataRate = queryUIntParameter(architecture, "dataRate");
memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
@@ -196,7 +196,6 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec
memSpec->tAL = clk * queryUIntParameter(timings, "AL");
memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
memSpec->tCL = clk * queryUIntParameter(timings, "CL");
memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
memSpec->tRC = clk * queryUIntParameter(timings, "RC");
@@ -207,6 +206,17 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec
memSpec->tWR = clk * queryUIntParameter(timings, "WR");
memSpec->tXP = clk * queryUIntParameter(timings, "XP");
memSpec->tXS = clk * queryUIntParameter(timings, "XS");
// Currents and voltages
XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec");
memSpec->iDD0 = queryDoubleParameter(powers, "idd0");
memSpec->iDD2N = queryDoubleParameter(powers, "idd2n");
memSpec->iDD3N = queryDoubleParameter(powers, "idd3n");
memSpec->iDD4R = queryDoubleParameter(powers, "idd4r");
memSpec->iDD4W = queryDoubleParameter(powers, "idd4w");
memSpec->iDD5 = queryDoubleParameter(powers, "idd5");
memSpec->iDD6 = queryDoubleParameter(powers, "idd6");
memSpec->vDD = queryDoubleParameter(powers, "vdd");
}
void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec)
@@ -216,12 +226,9 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
// MemArchitecture
//XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
//memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
memSpec->NumberOfBankGroups = 1;
memSpec->nActivate = 4;
memSpec->DLL = true;
memSpec->termination = true;
XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
memSpec->NumberOfBankGroups = 1;
// MemTimings specific for DDR3
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
@@ -243,21 +250,10 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec)
// Currents and Volatages: TODO Check if this is correct.
XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec");
memSpec->iDD0 = queryDoubleParameter(powers, "idd0");
memSpec->iDD02 = 0;
memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0");
memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1");
memSpec->iDD2N = queryDoubleParameter(powers, "idd2n");
memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0");
memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p1");
memSpec->iDD3N = queryDoubleParameter(powers, "idd3n");
memSpec->iDD4R = queryDoubleParameter(powers, "idd4r");
memSpec->iDD4W = queryDoubleParameter(powers, "idd4w");
memSpec->iDD5 = queryDoubleParameter(powers, "idd5");
memSpec->iDD6 = queryDoubleParameter(powers, "idd6");
memSpec->iDD62 = 0;
memSpec->vDD = queryDoubleParameter(powers, "vdd");
memSpec->vDD2 = 0;
}
void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec)
@@ -268,11 +264,8 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec)
// MemArchitecture
XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
//memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
memSpec->NumberOfBankGroups = queryUIntParameter(architecture, "nbrOfBankGroups");
memSpec->nActivate = 4;
memSpec->DLL = true;
memSpec->termination = true;
// MemTimings specific for DDR4
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
@@ -286,8 +279,10 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec)
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
else if (refMode == 2)
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC2");
else // if (refMode == 4)
else if (refMode == 4)
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC4");
else
SC_REPORT_FATAL("ConfigurationLoader", "Refresh Mode not supported");
memSpec->tRP = clk * queryUIntParameter(timings, "RP");
memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD_S");
memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD_L");
@@ -303,20 +298,12 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec)
// Currents and Volatages:
XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec");
memSpec->iDD0 = queryDoubleParameter(powers, "idd0");
memSpec->iDD02 = queryDoubleParameter(powers, "idd02");
memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0");
memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1");
memSpec->iDD2N = queryDoubleParameter(powers, "idd2n");
memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0");
memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p1");
memSpec->iDD3N = queryDoubleParameter(powers, "idd3n");
memSpec->iDD4R = queryDoubleParameter(powers, "idd4r");
memSpec->iDD4W = queryDoubleParameter(powers, "idd4w");
memSpec->iDD5 = queryDoubleParameter(powers, "idd5");
memSpec->iDD6 = queryDoubleParameter(powers, "idd6");
memSpec->iDD62 = queryDoubleParameter(powers, "idd62");
memSpec->vDD = queryDoubleParameter(powers, "vdd");
memSpec->vDD2 = queryDoubleParameter(powers, "vdd2");
}
@@ -328,12 +315,9 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
// MemArchitecture:
//XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
//memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
memSpec->NumberOfBankGroups = 1;
memSpec->nActivate = 4;
memSpec->DLL = false; // TODO: Correct?
memSpec->termination = true; // TODO: Correct?
XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
memSpec->NumberOfBankGroups = 1;
// MemTimings specific for LPDDR4
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
@@ -359,20 +343,12 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec)
// Currents and Volatages:
XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec");
memSpec->iDD0 = queryDoubleParameter(powers, "idd0");
memSpec->iDD02 = queryDoubleParameter(powers, "idd02");
memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p");
memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p2");
memSpec->iDD2N = queryDoubleParameter(powers, "idd2n");
memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p");
memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p2");
memSpec->iDD3N = queryDoubleParameter(powers, "idd3n");
memSpec->iDD4R = queryDoubleParameter(powers, "idd4r");
memSpec->iDD4W = queryDoubleParameter(powers, "idd4w");
memSpec->iDD5 = queryDoubleParameter(powers, "idd5");
memSpec->iDD6 = queryDoubleParameter(powers, "idd6");
memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p");
memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p2");
memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p");
memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p2");
memSpec->iDD62 = queryDoubleParameter(powers, "idd62");
memSpec->vDD = queryDoubleParameter(powers, "vdd");
memSpec->vDD2 = queryDoubleParameter(powers, "vdd2");
}
@@ -383,12 +359,8 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
// MemSpecification
//XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec");
//memSpec->NumberOfRanks = 1; // TODO: is part of some memspecs for WideIO
memSpec->NumberOfBankGroups = 1;
memSpec->nActivate = 2;
memSpec->DLL = false;
memSpec->termination = false;
memSpec->NumberOfRanks = 1;
memSpec->NumberOfBankGroups = 1;
// MemTimings specific for WideIO
XMLElement *timings = memspec->FirstChildElement("memtimingspec");
@@ -408,28 +380,20 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec)
// Currents and Volatages:
XMLElement *powers = memspec->FirstChildElement("mempowerspec");
memSpec->iDD0 = queryDoubleParameter(powers, "idd0");
memSpec->iDD02 = queryDoubleParameter(powers, "idd02");
memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0");
memSpec->iDD2P02 = queryDoubleParameter(powers, "idd2p02");
memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1");
memSpec->iDD2P12 = queryDoubleParameter(powers, "idd2p12");
memSpec->iDD2N = queryDoubleParameter(powers, "idd2n");
memSpec->iDD2N2 = queryDoubleParameter(powers, "idd2n2");
memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0");
memSpec->iDD3P02 = queryDoubleParameter(powers, "idd3p02");
memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p1");
memSpec->iDD3P12 = queryDoubleParameter(powers, "idd3p12");
memSpec->iDD3N = queryDoubleParameter(powers, "idd3n");
memSpec->iDD3N2 = queryDoubleParameter(powers, "idd3n2");
memSpec->iDD4R = queryDoubleParameter(powers, "idd4r");
memSpec->iDD4R2 = queryDoubleParameter(powers, "idd4r2");
memSpec->iDD4W = queryDoubleParameter(powers, "idd4w");
memSpec->iDD4W2 = queryDoubleParameter(powers, "idd4w2");
memSpec->iDD5 = queryDoubleParameter(powers, "idd5");
memSpec->iDD52 = queryDoubleParameter(powers, "idd52");
memSpec->iDD6 = queryDoubleParameter(powers, "idd6");
memSpec->iDD62 = queryDoubleParameter(powers, "idd62");
memSpec->vDD = queryDoubleParameter(powers, "vdd");
memSpec->vDD2 = queryDoubleParameter(powers, "vdd2");
}

70
DRAMSys/library/src/controller/core/configuration/MemSpec.h
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@@ -43,6 +43,8 @@
#include "../../../common/dramExtensions.h"
#include "../../Command.h"
using namespace tlm;
struct RefreshTiming
{
RefreshTiming() {}
@@ -63,7 +65,7 @@ struct MemSpec
// Returns the minimum execution time for commands that have a variable execution time
sc_time getMinExecutionTimeForPowerDownCmd(Command command) const;
virtual sc_time getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const;
virtual sc_time getExecutionTime(Command command, tlm_generic_payload &payload) const;
std::string MemoryId = "not defined.";
std::string MemoryType = "not defined.";
@@ -71,23 +73,17 @@ struct MemSpec
unsigned int NumberOfBanks;
unsigned int NumberOfRanks;
unsigned int BurstLength;
unsigned int nActivate;
unsigned int DataRate;
unsigned int NumberOfRows;
unsigned int NumberOfColumns;
unsigned int bitWidth;
unsigned int NumberOfBankGroups;
bool DLL;
bool termination;
// Memspec Variables:
double clkMHz;
sc_time clk;
sc_time tAL; // additive delay (delayed execution in dram)
sc_time tCKE; // min time in pdna or pdnp
sc_time tCKESR; // min time in sref
sc_time tCL; // unused, will be used in the future
sc_time tDQSCK;
sc_time tRAS; // active-time (act -> pre same bank)
sc_time tRC; // RAS-cycle-time (min time bw 2 succesive ACT to same bank)
sc_time tRCD; // act -> read/write
@@ -100,33 +96,19 @@ struct MemSpec
sc_time tREFI;
sc_time tRFC;
sc_time tRP;
// only used in DRAMPower
sc_time tAL; // additive delay (delayed execution in dram)
sc_time tDQSCK;
// Currents and Voltages:
double iDD0;
double iDD02;
double iDD2P0;
double iDD2P02;
double iDD2P1;
double iDD2P12;
double iDD2N;
double iDD2N2;
double iDD3P0;
double iDD3P02;
double iDD3P1;
double iDD3P12;
double iDD3N;
double iDD3N2;
double iDD4R;
double iDD4R2;
double iDD4W;
double iDD4W2;
double iDD5;
double iDD52;
double iDD6;
double iDD62;
double vDD;
double vDD2;
std::map<Bank, RefreshTiming> refreshTimings;
//ensure that map is populated completely in memspecloader
@@ -142,6 +124,11 @@ struct MemSpecDDR3 : public MemSpec
sc_time tWTR;
sc_time tXPDLL;
sc_time tXSDLL;
double iDD2P0;
double iDD2P1;
double iDD3P0;
double iDD3P1;
};
struct MemSpecDDR4 : public MemSpec
@@ -155,6 +142,14 @@ struct MemSpecDDR4 : public MemSpec
sc_time tWTR_L;
sc_time tXPDLL;
sc_time tXSDLL;
double iDD02;
double iDD2P0;
double iDD2P1;
double iDD3P0;
double iDD3P1;
double iDD62;
double vDD2;
};
struct MemSpecLPDDR4 : public MemSpec
@@ -170,7 +165,15 @@ struct MemSpecLPDDR4 : public MemSpec
sc_time tRPAB;
sc_time tRRD;
virtual sc_time getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const override;
double iDD02;
double iDD2P0;
double iDD2P1;
double iDD3P0;
double iDD3P1;
double iDD62;
double vDD2;
virtual sc_time getExecutionTime(Command command, tlm_generic_payload &payload) const override;
};
struct MemSpecWideIO : public MemSpec
@@ -179,6 +182,23 @@ struct MemSpecWideIO : public MemSpec
sc_time tRRD;
sc_time tTAW;
sc_time tWTR;
double iDD02;
double iDD2P0;
double iDD2P02;
double iDD2P1;
double iDD2P12;
double iDD2N2;
double iDD3P0;
double iDD3P02;
double iDD3P1;
double iDD3P12;
double iDD3N2;
double iDD4R2;
double iDD4W2;
double iDD52;
double iDD62;
double vDD2;
};
#endif // MEMSPEC_H

28
DRAMSys/library/src/simulation/DramDDR3.cpp
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@@ -63,8 +63,8 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name)
memArchSpec.nbrOfRanks = memSpec->NumberOfRanks;
memArchSpec.width = memSpec->bitWidth;
memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups;
memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true);
memArchSpec.dll = memSpec->DLL;
memArchSpec.twoVoltageDomains = false;
memArchSpec.dll = true;
MemTimingSpec memTimingSpec;
memTimingSpec.FAWB = memSpec->tFAW / clk;
@@ -109,29 +109,29 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name)
MemPowerSpec memPowerSpec;
memPowerSpec.idd0 = memSpec->iDD0;
memPowerSpec.idd02 = memSpec->iDD02;
memPowerSpec.idd02 = 0;
memPowerSpec.idd2p0 = memSpec->iDD2P0;
memPowerSpec.idd2p02 = memSpec->iDD2P02;
memPowerSpec.idd2p02 = 0;
memPowerSpec.idd2p1 = memSpec->iDD2P1;
memPowerSpec.idd2p12 = memSpec->iDD2P12;
memPowerSpec.idd2p12 = 0;
memPowerSpec.idd2n = memSpec->iDD2N;
memPowerSpec.idd2n2 = memSpec->iDD2N2;
memPowerSpec.idd2n2 = 0;
memPowerSpec.idd3p0 = memSpec->iDD3P0;
memPowerSpec.idd3p02 = memSpec->iDD3P02;
memPowerSpec.idd3p02 = 0;
memPowerSpec.idd3p1 = memSpec->iDD3P1;
memPowerSpec.idd3p12 = memSpec->iDD3P12;
memPowerSpec.idd3p12 = 0;
memPowerSpec.idd3n = memSpec->iDD3N;
memPowerSpec.idd3n2 = memSpec->iDD3N2;
memPowerSpec.idd3n2 = 0;
memPowerSpec.idd4r = memSpec->iDD4R;
memPowerSpec.idd4r2 = memSpec->iDD4R2;
memPowerSpec.idd4r2 = 0;
memPowerSpec.idd4w = memSpec->iDD4W;
memPowerSpec.idd4w2 = memSpec->iDD4W2;
memPowerSpec.idd4w2 = 0;
memPowerSpec.idd5 = memSpec->iDD5;
memPowerSpec.idd52 = memSpec->iDD52;
memPowerSpec.idd52 = 0;
memPowerSpec.idd6 = memSpec->iDD6;
memPowerSpec.idd62 = memSpec->iDD62;
memPowerSpec.idd62 = 0;
memPowerSpec.vdd = memSpec->vDD;
memPowerSpec.vdd2 = memSpec->vDD2;
memPowerSpec.vdd2 = 0;
MemorySpecification powerSpec;
powerSpec.id = memSpec->MemoryId;

22
DRAMSys/library/src/simulation/DramDDR4.cpp
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@@ -63,8 +63,8 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name)
memArchSpec.nbrOfRanks = memSpec->NumberOfRanks;
memArchSpec.width = memSpec->bitWidth;
memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups;
memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true);
memArchSpec.dll = memSpec->DLL;
memArchSpec.twoVoltageDomains = true;
memArchSpec.dll = true;
MemTimingSpec memTimingSpec;
memTimingSpec.FAWB = memSpec->tFAW / clk;
@@ -111,23 +111,23 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name)
memPowerSpec.idd0 = memSpec->iDD0;
memPowerSpec.idd02 = memSpec->iDD02;
memPowerSpec.idd2p0 = memSpec->iDD2P0;
memPowerSpec.idd2p02 = memSpec->iDD2P02;
memPowerSpec.idd2p02 = 0;
memPowerSpec.idd2p1 = memSpec->iDD2P1;
memPowerSpec.idd2p12 = memSpec->iDD2P12;
memPowerSpec.idd2p12 = 0;
memPowerSpec.idd2n = memSpec->iDD2N;
memPowerSpec.idd2n2 = memSpec->iDD2N2;
memPowerSpec.idd2n2 = 0;
memPowerSpec.idd3p0 = memSpec->iDD3P0;
memPowerSpec.idd3p02 = memSpec->iDD3P02;
memPowerSpec.idd3p02 = 0;
memPowerSpec.idd3p1 = memSpec->iDD3P1;
memPowerSpec.idd3p12 = memSpec->iDD3P12;
memPowerSpec.idd3p12 = 0;
memPowerSpec.idd3n = memSpec->iDD3N;
memPowerSpec.idd3n2 = memSpec->iDD3N2;
memPowerSpec.idd3n2 = 0;
memPowerSpec.idd4r = memSpec->iDD4R;
memPowerSpec.idd4r2 = memSpec->iDD4R2;
memPowerSpec.idd4r2 = 0;
memPowerSpec.idd4w = memSpec->iDD4W;
memPowerSpec.idd4w2 = memSpec->iDD4W2;
memPowerSpec.idd4w2 = 0;
memPowerSpec.idd5 = memSpec->iDD5;
memPowerSpec.idd52 = memSpec->iDD52;
memPowerSpec.idd52 = 0;
memPowerSpec.idd6 = memSpec->iDD6;
memPowerSpec.idd62 = memSpec->iDD62;
memPowerSpec.vdd = memSpec->vDD;

4
DRAMSys/library/src/simulation/DramWideIO.cpp
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@@ -65,8 +65,8 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name)
memArchSpec.nbrOfRanks = memSpec->NumberOfRanks;
memArchSpec.width = memSpec->bitWidth;
memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups;
memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true);
memArchSpec.dll = memSpec->DLL;
memArchSpec.twoVoltageDomains = true;
memArchSpec.dll = false;
MemTimingSpec memTimingSpec;
memTimingSpec.FAWB = memSpec->tTAW / clk;