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Removed RGR timing parameters.

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This commit is contained in:
Lukas Steiner (2)
2019-08-19 11:16:27 +02:00
parent 8115aba222
commit 3f7296f2a5
5 changed files with 21 additions and 71 deletions
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36
DRAMSys/library/src/controller/core/configuration/Configuration.cpp
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@@ -236,18 +236,6 @@ void Configuration::setParameter(std::string name, std::string value)
RGRB14 = string2bool(value);
else if (name == "ControllerCoreRGRB15")
RGRB15 = string2bool(value);
else if (name == "ControllerCoreRGRtRASBInClkCycles")
trasbclk = string2int(value);
else if (name == "ControllerCoreRGRtRRDB_LInClkCycles")
trrdblclk = string2int(value);
else if (name == "ControllerCoreRGRtRRDB_SInClkCycles")
trrdbsclk = string2int(value);
else if (name == "ControllerCoreRGRtRPBInClkCycles")
trpbclk = string2int(value);
else if (name == "ControllerCoreRGRtRCBInClkCycles")
trcbclk = string2int(value);
else if (name == "ControllerCoreRGRtFAWBInClkCycles")
tfawbclk = string2int(value);
else if (name == "ControllerCoreRefForceMaxPostponeBurst")
ControllerCoreRefForceMaxPostponeBurst = string2bool(value);
else if (name == "ControllerCoreRefEnablePostpone") {
@@ -401,30 +389,6 @@ unsigned int Configuration::getBytesPerBurst()
return bytesPerBurst;
}
sc_time Configuration::getTrasb()
{
return trasbclk * memSpec->clk;
}
sc_time Configuration::getTrrdb_L()
{
return trrdblclk * memSpec->clk;
}
sc_time Configuration::getTrrdb_S()
{
return trrdbsclk * memSpec->clk;
}
sc_time Configuration::getTrpb()
{
return trpbclk * memSpec->clk;
}
sc_time Configuration::getTrcb()
{
return trcbclk * memSpec->clk;
}
sc_time Configuration::getTfawb()
{
return tfawbclk * memSpec->clk;
}
bool Configuration::getRGRBank(unsigned int w)
{
bool flg = w == 0 ? RGRB0 : w == 1 ? RGRB1 : w == 2 ? RGRB2 : w == 3 ? RGRB3 : w

14
DRAMSys/library/src/controller/core/configuration/Configuration.h
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@@ -88,20 +88,6 @@ struct Configuration
unsigned int NumberOfMemChannels = 1;
bool ControllerCoreRefDisable = false;
bool RowGranularRef = false;
// TODO: will be removed in the future
unsigned int trasbclk = 0;
sc_time getTrasb();
unsigned int trrdblclk = 0;
sc_time getTrrdb_L();
unsigned int trrdbsclk = 0;
sc_time getTrrdb_S();
unsigned int trpbclk = 0;
sc_time getTrpb();
unsigned int trcbclk = 0;
sc_time getTrcb();
unsigned int tfawbclk = 0;
sc_time getTfawb();
// -----------------------------------
bool RGRB0 = true;
bool RGRB1 = true;
bool RGRB2 = true;

14
DRAMSys/library/src/simulation/DramDDR3.cpp
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@@ -67,13 +67,13 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name)
memArchSpec.dll = memSpec->DLL;
MemTimingSpec memTimingSpec;
memTimingSpec.FAWB = Configuration::getInstance().tfawbclk;
memTimingSpec.RASB = Configuration::getInstance().trasbclk;
memTimingSpec.RCB = Configuration::getInstance().trcbclk;
memTimingSpec.RPB = Configuration::getInstance().trpbclk;
memTimingSpec.RRDB = Configuration::getInstance().trrdblclk;
memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk;
memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk;
memTimingSpec.FAWB = memSpec->tFAW / clk;
memTimingSpec.RASB = memSpec->tRAS / clk;
memTimingSpec.RCB = memSpec->tRC / clk;
memTimingSpec.RPB = memSpec->tRP / clk;
memTimingSpec.RRDB = memSpec->tRRD / clk;
memTimingSpec.RRDB_L = memSpec->tRRD / clk;
memTimingSpec.RRDB_S = memSpec->tRRD / clk;
memTimingSpec.AL = memSpec->tAL / clk;
memTimingSpec.CCD = memSpec->tCCD / clk;
memTimingSpec.CCD_L = memSpec->tCCD / clk;

14
DRAMSys/library/src/simulation/DramDDR4.cpp
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@@ -67,13 +67,13 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name)
memArchSpec.dll = memSpec->DLL;
MemTimingSpec memTimingSpec;
memTimingSpec.FAWB = Configuration::getInstance().tfawbclk;
memTimingSpec.RASB = Configuration::getInstance().trasbclk;
memTimingSpec.RCB = Configuration::getInstance().trcbclk;
memTimingSpec.RPB = Configuration::getInstance().trpbclk;
memTimingSpec.RRDB = Configuration::getInstance().trrdblclk;
memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk;
memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk;
memTimingSpec.FAWB = memSpec->tFAW / clk;
memTimingSpec.RASB = memSpec->tRAS / clk;
memTimingSpec.RCB = memSpec->tRC / clk;
memTimingSpec.RPB = memSpec->tRP / clk;
memTimingSpec.RRDB = memSpec->tRRD_S / clk;
memTimingSpec.RRDB_L = memSpec->tRRD_L / clk;
memTimingSpec.RRDB_S = memSpec->tRRD_S / clk;
memTimingSpec.AL = memSpec->tAL / clk;
memTimingSpec.CCD = memSpec->tCCD_S / clk;
memTimingSpec.CCD_L = memSpec->tCCD_L / clk;

14
DRAMSys/library/src/simulation/DramWideIO.cpp
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@@ -69,13 +69,13 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name)
memArchSpec.dll = memSpec->DLL;
MemTimingSpec memTimingSpec;
memTimingSpec.FAWB = Configuration::getInstance().tfawbclk;
memTimingSpec.RASB = Configuration::getInstance().trasbclk;
memTimingSpec.RCB = Configuration::getInstance().trcbclk;
memTimingSpec.RPB = Configuration::getInstance().trpbclk;
memTimingSpec.RRDB = Configuration::getInstance().trrdblclk;
memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk;
memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk;
memTimingSpec.FAWB = memSpec->tTAW / clk;
memTimingSpec.RASB = memSpec->tRAS / clk;
memTimingSpec.RCB = memSpec->tRC / clk;
memTimingSpec.RPB = memSpec->tRP / clk;
memTimingSpec.RRDB = memSpec->tRRD / clk;
memTimingSpec.RRDB_L = memSpec->tRRD / clk;
memTimingSpec.RRDB_S = memSpec->tRRD / clk;
memTimingSpec.AL = memSpec->tAL / clk;
memTimingSpec.CCD = memSpec->tCCD / clk;
memTimingSpec.CCD_L = memSpec->tCCD / clk;