Fixed wrong PRE -<> PREA test in TraceAnalyzer.
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@@ -321,7 +321,7 @@ def timing_constraint(FirstPhase, SecondPhase):
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FirstPhaseName = FirstPhase[0]
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SecondPhaseName = SecondPhase[0]
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if (FirstPhaseName == "PRE" or FirstPhaseName == "PRE_ALL"):
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if ((FirstPhaseName == "PRE" or FirstPhaseName == "PRE_ALL") and SecondPhaseName != "PRE_ALL"):
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return dramconfig.tRP
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elif (FirstPhaseName == "ACT"):
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