diff --git a/DRAMSys/traceAnalyzer/scripts/tests.py b/DRAMSys/traceAnalyzer/scripts/tests.py
index c38e1d2d..6b2877ca 100755
--- a/DRAMSys/traceAnalyzer/scripts/tests.py
+++ b/DRAMSys/traceAnalyzer/scripts/tests.py
@@ -321,7 +321,7 @@ def timing_constraint(FirstPhase, SecondPhase):
     FirstPhaseName = FirstPhase[0]
     SecondPhaseName = SecondPhase[0]
 
-    if (FirstPhaseName == "PRE" or FirstPhaseName == "PRE_ALL"):
+    if ((FirstPhaseName == "PRE" or FirstPhaseName == "PRE_ALL") and SecondPhaseName != "PRE_ALL"):
         return dramconfig.tRP
 
     elif (FirstPhaseName == "ACT"):