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Merge branch 'master' of https://git.eit.uni-kl.de/ems/astdm/dram.sys

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This commit is contained in:
Matthias Jung
2019-08-22 23:03:05 +02:00
parent a6f679b86b 7304055a22
commit d55d801a04
173 changed files with 6376 additions and 2771 deletions
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1
.gitignore vendored
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@@ -21,3 +21,4 @@ DRAMSys/analyzer/scripts/__pycache__/
*.autosave
*__pycache__*
DRAMSys/gem5/boot_linux/linux-aarch32-ael.img
DRAMSys/docs/doxygen

38
.gitlab-ci.yml
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@@ -1,3 +1,4 @@
# vim: set ts=4 sw=4 expandtab:
image: gcc
variables:
@@ -5,12 +6,10 @@ variables:
stages:
- build
- dramsys-gem5-build
- WIDEIO
- DDR3
cache:
paths:
- build/
- Coverage
build:
stage: build
@@ -22,7 +21,36 @@ build:
- cd build
- qmake ../DRAMSys/DRAMSys.pro
- make -j4
- find . -name "*.o" -type f -delete
- rm -rf ${CI_PROJECT_DIR}/coverage
- mkdir -p ${CI_PROJECT_DIR}/coverage
cache:
key: build
paths:
- build/
policy: push
artifacts:
paths:
- coverage/
coverage:
stage: Coverage
coverage: '/Total:\|(\d+\.?\d+\%)/'
script:
# delete all empty files since they produce errors
- find coverage -size 0 -type f -delete
- ls coverage/ -lah
- lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final.out
- lcov --list coverage/final.out
artifacts:
paths:
- coverage/final.out
include:
- '/DRAMSys/tests/DDR3/ci.yml'
- '/DRAMSys/tests/WIDEIO/ci.yml'
#- '/DRAMSys/tests/dramsys-gem5/ci.yml' # Should be activated again when a new gitlab runner with right dependencies is used

3
.gitmodules vendored
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@@ -5,3 +5,6 @@
path = DRAMSys/library/src/common/third_party/DRAMPower
url = https://github.com/tukl-msd/DRAMPower.git
branch = master
[submodule "DRAMSys/unitTests/googletest"]
path = DRAMSys/unitTests/googletest
url = https://github.com/google/googletest.git

15
DRAMSys/DRAMSys.pro
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@@ -11,11 +11,26 @@ $$eval(thermalsim) {
message(Thermal Simulation Feature Disabled)
}
dramsys_disable_coverage_check = $$(DRAMSYS_DISABLE_COVERAGE_CHECK)
isEmpty(dramsys_disable_coverage_check) {
message(Coverage check ENABLED)
} else {
message(Coverage check DISABLED)
}
systemc_home = $$(SYSTEMC_HOME)
isEmpty(systemc_home) {
systemc_home = /opt/systemc
}
message(SystemC home is $${systemc_home})
SUBDIRS += library
SUBDIRS += unitTests
SUBDIRS += simulator
SUBDIRS += traceAnalyzer
library.subdir = library
unitTests.subdir = unitTests
simulator.subdir = simulator
traceAnalyzer.subdir = traceAnalyzer

1228
DRAMSys/docs/doxyCfg.cfg Normal file
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94
DRAMSys/gem5/gem5.pro
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@@ -33,13 +33,30 @@ DEFINES += TIXML_USE_STL
DEFINES += SC_INCLUDE_DYNAMIC_PROCESSES
DEFINES += DRAMSYS_GEM5
dramsys_disable_coverage_check = $$(DRAMSYS_DISABLE_COVERAGE_CHECK)
isEmpty(dramsys_disable_coverage_check) {
coverage_check = true
message(Coverage check ENABLED)
} else {
coverage_check = false
message(Coverage check DISABLED)
}
unix:!macx {
QMAKE_CXXFLAGS += -std=c++11 -O0 -g
QMAKE_CXXFLAGS += -std=c++11 -O0 -g
$$eval(coverage_check) {
QMAKE_CXXFLAGS += -fprofile-arcs -ftest-coverage -fPIC -O0
QMAKE_LFLAGS += -lgcov --coverage
}
}
macx: {
CONFIG += c++11
QMAKE_CXXFLAGS += -std=c++0x -stdlib=libc++ -O0 -g
CONFIG += c++11
QMAKE_CXXFLAGS += -std=c++0x -stdlib=libc++ -O0 -g
$$eval(coverage_check) {
QMAKE_CXXFLAGS += --coverage
QMAKE_LFLAGS += --coverage
}
}
INCLUDEPATH += ../library/src/simulation/
@@ -75,23 +92,76 @@ SOURCES += $${gem5_root}/util/tlm/src/sim_control.cc
SOURCES += main.cpp
DISTFILES += ../DRAMSys.astylerc
DISTFILES += configs/singleElasticTraceReplay.ini
DISTFILES += etrace_single/config.ini
DISTFILES += etrace_single_L2/HPCG-47MB/config.ini
DISTFILES += etrace_single_L2/Pathfinder/config.ini
DISTFILES += etrace_single_L2/hpcc-linpack/config.ini
DISTFILES += etrace_single_L2/hpcc-fft/config.ini
DISTFILES += etrace_single_L2/config.ini
DISTFILES += etrace_single_L2/hpcc-dgemm/config.ini
DISTFILES += etrace_single_L2/hpcc-gups/config.ini
DISTFILES += configs/singleElasticTraceReplayWithL2.ini
DISTFILES += configs/dualElasticTraceReplay.ini
DISTFILES += configs/nvdimmp.ini
DISTFILES += configs/hello.ini
DISTFILES += configs/dualElasticTraceReplay.ini
DISTFILES += configs/singleElasticTraceReplay.ini
DISTFILES += configs/boot_linux.ini
DISTFILES += gem5_fs/stream/config.ini
DISTFILES += gem5_fs/stream/stream_1_cores.rcS
DISTFILES += gem5_fs/parsec/simmedium/fluidanimate/fluidanimate_simmedium_2.rcS
DISTFILES += gem5_fs/parsec/simmedium/fluidanimate/config.ini
DISTFILES += gem5_fs/parsec/simmedium/ferret/config.ini
DISTFILES += gem5_fs/parsec/simmedium/ferret/ferret_simmedium_2.rcS
DISTFILES += gem5_fs/parsec/simmedium/blackscholes/blackscholes_simmedium_2.rcS
DISTFILES += gem5_fs/parsec/simmedium/blackscholes/config.ini
DISTFILES += gem5_fs/parsec/simlarge/streamcluster/config.ini
DISTFILES += gem5_fs/parsec/simlarge/streamcluster/streamcluster_simlarge_2.rcS
DISTFILES += gem5_fs/parsec/simsmall/fluidanimate/fluidanimate_simsmall_2.rcS
DISTFILES += gem5_fs/parsec/simsmall/fluidanimate/config.ini
DISTFILES += gem5_fs/parsec/simsmall/bodytrack/bodytrack_simsmall_2.rcS
DISTFILES += gem5_fs/parsec/simsmall/bodytrack/config.ini
DISTFILES += gem5_fs/parsec/simsmall/ferret/config.ini
DISTFILES += gem5_fs/parsec/simsmall/ferret/ferret_simsmall_2.rcS
DISTFILES += gem5_fs/parsec/simsmall/blackscholes/config.ini
DISTFILES += gem5_fs/parsec/simsmall/blackscholes/blackscholes_simsmall_2.rcS
DISTFILES += gem5_fs/parsec/simdev/fluidanimate/config.ini
DISTFILES += gem5_fs/parsec/simdev/fluidanimate/fluidanimate_simdev_2.rcS
DISTFILES += gem5_fs/parsec/simdev/blackscholes/blackscholes_simdev_2.rcS
DISTFILES += gem5_fs/parsec/simdev/blackscholes/config.ini
DISTFILES += examples/tlm_elastic_slave.py
DISTFILES += examples/tlm_elastic_slave_mc_direct.py
DISTFILES += examples/tlm_elastic_slave_with_l2.py
DISTFILES += gem5_se/almabench/config.ini
DISTFILES += gem5_se/fldry/config.ini
DISTFILES += gem5_se/Queens/config.ini
DISTFILES += gem5_se/chomp/config.ini
DISTFILES += gem5_se/l1_cache/Queens/config.ini
DISTFILES += gem5_se/l1_cache/chomp/config.ini
DISTFILES += gem5_se/l1_cache/Puzzle/config.ini
DISTFILES += gem5_se/l1_cache/RealMM/config.ini
DISTFILES += gem5_se/l1_cache/Perm/config.ini
DISTFILES += gem5_se/l1_cache/Treesort/config.ini
DISTFILES += gem5_se/l1_cache/Bubblesort/config.ini
DISTFILES += gem5_se/l1_cache/misr/config.ini
DISTFILES += gem5_se/l1_cache/exptree/config.ini
DISTFILES += gem5_se/l1_cache/Quicksort/config.ini
DISTFILES += gem5_se/l1_cache/IntMM/config.ini
DISTFILES += gem5_se/l1_cache/Oscar/config.ini
DISTFILES += gem5_se/l1_cache/FloatMM/config.ini
DISTFILES += gem5_se/l1_cache/Towers/config.ini
DISTFILES += gem5_se/run.sh
DISTFILES += gem5_se/Puzzle/config.ini
DISTFILES += gem5_se/RealMM/config.ini
DISTFILES += gem5_se/Perm/config.ini
DISTFILES += gem5_se/Treesort/config.ini
DISTFILES += gem5_se/Bubblesort/config.ini
DISTFILES += gem5_se/misr/config.ini
DISTFILES += gem5_se/lpbench/config.ini
DISTFILES += gem5_se/8_cores/config.ini
DISTFILES += gem5_se/exptree/config.ini
DISTFILES += gem5_se/Quicksort/config.ini
DISTFILES += gem5_se/IntMM/config.ini
DISTFILES += gem5_se/Oscar/config.ini
DISTFILES += gem5_se/Perm/config.ini
DISTFILES += gem5_se/Puzzle/config.ini
DISTFILES += gem5_se/Queens/config.ini
DISTFILES += gem5_se/Quicksort/config.ini
DISTFILES += gem5_se/RealMM/config.ini
DISTFILES += gem5_se/FloatMM/config.ini
DISTFILES += gem5_se/Towers/config.ini
DISTFILES += gem5_se/Treesort/config.ini
DISTFILES += gem5_se/run.sh

275
DRAMSys/gem5/gem5_se/hello-x86/config.dot Normal file
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@@ -0,0 +1,275 @@
digraph G {
ranksep="1.3";
subgraph cluster_root {
color="#000000";
fillcolor="#bab6ae";
fontcolor="#000000";
fontname=Arial;
fontsize=14;
label="root \n: Root";
shape=Mrecord;
style="rounded, filled";
tooltip="eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000";
subgraph cluster_system {
color="#000000";
fillcolor="#e4e7eb";
fontcolor="#000000";
fontname=Arial;
fontsize=14;
label="system \n: System";
shape=Mrecord;
style="rounded, filled";
tooltip="boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=false
kernel_extras=
kvm_vm=Null
load_addr_mask=18446744073709551615
load_offset=0
mem_mode=timing
mem_ranges=0:536870911:0:0:0:0
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1";
system_system_port [color="#000000", fillcolor="#b6b8bc", fontcolor="#000000", fontname=Arial, fontsize=14, label=system_port, shape=Mrecord, style="rounded, filled"];
subgraph cluster_system_membus {
color="#000000";
fillcolor="#6f798c";
fontcolor="#000000";
fontname=Arial;
fontsize=14;
label="membus \n: SystemXBar";
shape=Mrecord;
style="rounded, filled";
tooltip="clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
point_of_unification=true
power_model=
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16";
system_membus_master [color="#000000", fillcolor="#586070", fontcolor="#000000", fontname=Arial, fontsize=14, label=master, shape=Mrecord, style="rounded, filled"];
system_membus_slave [color="#000000", fillcolor="#586070", fontcolor="#000000", fontname=Arial, fontsize=14, label=slave, shape=Mrecord, style="rounded, filled"];
subgraph cluster_system_membus_snoop_filter {
color="#000000";
fillcolor="#bab6ae";
fontcolor="#000000";
fontname=Arial;
fontsize=14;
label="snoop_filter \n: SnoopFilter";
shape=Mrecord;
style="rounded, filled";
tooltip="eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system";
}
}
subgraph cluster_system_external_memory {
color="#000000";
fillcolor="#bab6ae";
fontcolor="#000000";
fontname=Arial;
fontsize=14;
label="external_memory \n: ExternalSlave";
shape=Mrecord;
style="rounded, filled";
tooltip="addr_ranges=0:536870911:0:0:0:0
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
port_data=transactor
port_type=tlm_slave
power_model=";
system_external_memory_port [color="#000000", fillcolor="#94918b", fontcolor="#000000", fontname=Arial, fontsize=14, label=port, shape=Mrecord, style="rounded, filled"];
}
subgraph cluster_system_voltage_domain {
color="#000000";
fillcolor="#bab6ae";
fontcolor="#000000";
fontname=Arial;
fontsize=14;
label="voltage_domain \n: VoltageDomain";
shape=Mrecord;
style="rounded, filled";
tooltip="eventq_index=0
voltage=1.0";
}
subgraph cluster_system_physmem {
color="#000000";
fillcolor="#5e5958";
fontcolor="#000000";
fontname=Arial;
fontsize=14;
label="physmem \n: SimpleMemory";
shape=Mrecord;
style="rounded, filled";
tooltip="bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
range=0:134217727:0:0:0:0";
}
subgraph cluster_system_clk_domain {
color="#000000";
fillcolor="#bab6ae";
fontcolor="#000000";
fontname=Arial;
fontsize=14;
label="clk_domain \n: SrcClockDomain";
shape=Mrecord;
style="rounded, filled";
tooltip="clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain";
}
subgraph cluster_system_cpu_voltage_domain {
color="#000000";
fillcolor="#bab6ae";
fontcolor="#000000";
fontname=Arial;
fontsize=14;
label="cpu_voltage_domain \n: VoltageDomain";
shape=Mrecord;
style="rounded, filled";
tooltip="eventq_index=0
voltage=1.0";
}
subgraph cluster_system_dvfs_handler {
color="#000000";
fillcolor="#bab6ae";
fontcolor="#000000";
fontname=Arial;
fontsize=14;
label="dvfs_handler \n: DVFSHandler";
shape=Mrecord;
style="rounded, filled";
tooltip="domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000";
}
subgraph cluster_system_cpu_clk_domain {
color="#000000";
fillcolor="#bab6ae";
fontcolor="#000000";
fontname=Arial;
fontsize=14;
label="cpu_clk_domain \n: SrcClockDomain";
shape=Mrecord;
style="rounded, filled";
tooltip="clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.cpu_voltage_domain";
}
subgraph cluster_system_cpu {
color="#000000";
fillcolor="#bbc6d9";
fontcolor="#000000";
fontname=Arial;
fontsize=14;
label="cpu \n: TimingSimpleCPU";
shape=Mrecord;
style="rounded, filled";
tooltip="branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_gating_on_idle=false
power_model=
profile=0
progress_interval=0
pwr_gating_latency=300
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
wait_for_remote_gdb=false
workload=system.cpu.workload";
system_cpu_icache_port [color="#000000", fillcolor="#959ead", fontcolor="#000000", fontname=Arial, fontsize=14, label=icache_port, shape=Mrecord, style="rounded, filled"];
system_cpu_dcache_port [color="#000000", fillcolor="#959ead", fontcolor="#000000", fontname=Arial, fontsize=14, label=dcache_port, shape=Mrecord, style="rounded, filled"];
subgraph cluster_system_cpu_workload {
color="#000000";
fillcolor="#bab6ae";
fontcolor="#000000";
fontname=Arial;
fontsize=14;
label="workload \n: Process";
shape=Mrecord;
style="rounded, filled";
tooltip="cmd=tests/test-progs/hello/bin/x86/linux/hello
cwd=/media/disk2/gem5_tnt/gem5
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=tests/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
kvmInSE=false
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=0
simpoint=0
system=system
uid=100
useArchPT=false";
}
subgraph cluster_system_cpu_apic_clk_domain {
color="#000000";
fillcolor="#bab6ae";
fontcolor="#000000";
fontname=Arial;
fontsize=14;
label="apic_clk_domain \n: DerivedClockDomain";
shape=Mrecord;
style="rounded, filled";
tooltip="clk_divider=16
clk_domain=system.cpu_clk_domain
eventq_index=0";
}
subgraph cluster_system_cpu_dtb {
color="#000000";
fillcolor="#bab6ae";
fontcolor="#000000";
fontname=Arial;
fontsize=14;
label="dtb \n: X86TLB";
shape=Mrecord;
style="rounded, filled";
tooltip="eventq_index=0
size=64
walker=system.cpu.dtb.walker";
subgraph cluster_system_cpu_dtb_walker {
color="#000000";
fillcolor="#9f9c95";
fontcolor="#000000";
fontname=Arial;
fontsize=14;
label="walker \n: X86PagetableWalker";
shape=Mrecord;
style="rounded, filled";
tooltip="clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
num_squash_per_cycle=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
system=system";
system_cpu_dtb_walker_port [color="#000000", fillcolor="#7f7c77", fontcolor="#000000", fontname=Arial, fontsize=14, label=port, shape=Mrecord, style="rounded, filled"];
}
}
subgraph cluster_system_cpu_interrupts {
color="#000000";
fillcolor="#c7a793";
fontcolor="#000000";
fontname=Arial;
fontsize=14;
label="interrupts \n: X86LocalApic";
shape=Mrecord;
style="rounded, filled";
tooltip="clk_domain=system.cpu.apic_clk_domain
default_p_state=UNDEFINED
eventq_index=0
int_latency=1000
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=2305843009213693952
pio_latency=100000
power_model=
system=system";
system_cpu_interrupts_int_slave [color="#000000", fillcolor="#9f8575", fontcolor="#000000", fontname=Arial, fontsize=14, label=int_slave, shape=Mrecord, style="rounded, filled"];
system_cpu_interrupts_int_master [color="#000000", fillcolor="#9f8575", fontcolor="#000000", fontname=Arial, fontsize=14, label=int_master, shape=Mrecord, style="rounded, filled"];
system_cpu_interrupts_pio [color="#000000", fillcolor="#9f8575", fontcolor="#000000", fontname=Arial, fontsize=14, label=pio, shape=Mrecord, style="rounded, filled"];
}
subgraph cluster_system_cpu_itb {
color="#000000";
fillcolor="#bab6ae";
fontcolor="#000000";
fontname=Arial;
fontsize=14;
label="itb \n: X86TLB";
shape=Mrecord;
style="rounded, filled";
tooltip="eventq_index=0
size=64
walker=system.cpu.itb.walker";
subgraph cluster_system_cpu_itb_walker {
color="#000000";
fillcolor="#9f9c95";
fontcolor="#000000";
fontname=Arial;
fontsize=14;
label="walker \n: X86PagetableWalker";
shape=Mrecord;
style="rounded, filled";
tooltip="clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
num_squash_per_cycle=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
system=system";
system_cpu_itb_walker_port [color="#000000", fillcolor="#7f7c77", fontcolor="#000000", fontname=Arial, fontsize=14, label=port, shape=Mrecord, style="rounded, filled"];
}
}
subgraph cluster_system_cpu_isa {
color="#000000";
fillcolor="#bab6ae";
fontcolor="#000000";
fontname=Arial;
fontsize=14;
label="isa \n: X86ISA";
shape=Mrecord;
style="rounded, filled";
tooltip="eventq_index=0";
}
subgraph cluster_system_cpu_tracer {
color="#000000";
fillcolor="#bab6ae";
fontcolor="#000000";
fontname=Arial;
fontsize=14;
label="tracer \n: ExeTracer";
shape=Mrecord;
style="rounded, filled";
tooltip="eventq_index=0";
}
}
}
}
system_system_port -> system_membus_slave;
system_membus_master -> system_cpu_interrupts_pio;
system_membus_master -> system_cpu_interrupts_int_slave;
system_membus_master -> system_external_memory_port;
system_cpu_icache_port -> system_membus_slave;
system_cpu_dcache_port -> system_membus_slave;
system_cpu_dtb_walker_port -> system_membus_slave;
system_cpu_interrupts_int_master -> system_membus_slave;
system_cpu_itb_walker_port -> system_membus_slave;
}

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DRAMSys/gem5/gem5_se/hello-x86/config.dot.pdf Normal file
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DRAMSys/gem5/gem5_se/hello-x86/config.dot.svg Normal file
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@@ -0,0 +1,193 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN"
"http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
<!-- Generated by graphviz version 2.38.0 (20140413.2041)
-->
<!-- Title: G Pages: 1 -->
<svg width="1007pt" height="577pt"
viewBox="0.00 0.00 1007.00 577.00" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<g id="graph0" class="graph" transform="scale(1 1) rotate(0) translate(4 573)">
<title>G</title>
<polygon fill="white" stroke="none" points="-4,4 -4,-573 1003,-573 1003,4 -4,4"/>
<g id="clust1" class="cluster"><title>cluster_root</title>
<g id="a_clust1"><a xlink:title="eventq_index&#61;0&#10;full_system&#61;false&#10;sim_quantum&#61;0&#10;time_sync_enable&#61;false&#10;time_sync_period&#61;100000000000&#10;time_sync_spin_threshold&#61;100000000">
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<text text-anchor="middle" x="499.5" y="-545.8" font-family="Arial" font-size="14.00" fill="#000000">root </text>
<text text-anchor="middle" x="499.5" y="-530.8" font-family="Arial" font-size="14.00" fill="#000000">: Root</text>
</a>
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<g id="clust2" class="cluster"><title>cluster_system</title>
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<text text-anchor="middle" x="499.5" y="-484.8" font-family="Arial" font-size="14.00" fill="#000000">: System</text>
</a>
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</g>
<g id="clust3" class="cluster"><title>cluster_system_membus</title>
<g id="a_clust3"><a xlink:title="clk_domain&#61;system.clk_domain&#10;default_p_state&#61;UNDEFINED&#10;eventq_index&#61;0&#10;forward_latency&#61;4&#10;frontend_latency&#61;3&#10;p_state_clk_gate_bins&#61;20&#10;p_state_clk_gate_max&#61;1000000000000&#10;p_state_clk_gate_min&#61;1000&#10;point_of_coherency&#61;true&#10;point_of_unification&#61;true&#10;power_model&#61;&#10;response_latency&#61;2&#10;snoop_filter&#61;system.membus.snoop_filter&#10;snoop_response_latency&#61;4&#10;system&#61;system&#10;use_default_range&#61;false&#10;width&#61;16">
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<text text-anchor="middle" x="555" y="-230.8" font-family="Arial" font-size="14.00" fill="#000000">membus </text>
<text text-anchor="middle" x="555" y="-215.8" font-family="Arial" font-size="14.00" fill="#000000">: SystemXBar</text>
</a>
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</g>
<g id="clust5" class="cluster"><title>cluster_system_external_memory</title>
<g id="a_clust5"><a xlink:title="addr_ranges&#61;0:536870911:0:0:0:0&#10;clk_domain&#61;system.clk_domain&#10;default_p_state&#61;UNDEFINED&#10;eventq_index&#61;0&#10;p_state_clk_gate_bins&#61;20&#10;p_state_clk_gate_max&#61;1000000000000&#10;p_state_clk_gate_min&#61;1000&#10;port_data&#61;transactor&#10;port_type&#61;tlm_slave&#10;power_model&#61;">
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<text text-anchor="middle" x="591" y="-99.8" font-family="Arial" font-size="14.00" fill="#000000">external_memory </text>
<text text-anchor="middle" x="591" y="-84.8" font-family="Arial" font-size="14.00" fill="#000000">: ExternalSlave</text>
</a>
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</g>
<g id="clust12" class="cluster"><title>cluster_system_cpu</title>
<g id="a_clust12"><a xlink:title="branchPred&#61;Null&#10;checker&#61;Null&#10;clk_domain&#61;system.cpu_clk_domain&#10;cpu_id&#61;0&#10;default_p_state&#61;UNDEFINED&#10;do_checkpoint_insts&#61;true&#10;do_quiesce&#61;true&#10;do_statistics_insts&#61;true&#10;dtb&#61;system.cpu.dtb&#10;eventq_index&#61;0&#10;function_trace&#61;false&#10;function_trace_start&#61;0&#10;interrupts&#61;system.cpu.interrupts&#10;isa&#61;system.cpu.isa&#10;itb&#61;system.cpu.itb&#10;max_insts_all_threads&#61;0&#10;max_insts_any_thread&#61;0&#10;max_loads_all_threads&#61;0&#10;max_loads_any_thread&#61;0&#10;numThreads&#61;1&#10;p_state_clk_gate_bins&#61;20&#10;p_state_clk_gate_max&#61;1000000000000&#10;p_state_clk_gate_min&#61;1000&#10;power_gating_on_idle&#61;false&#10;power_model&#61;&#10;profile&#61;0&#10;progress_interval&#61;0&#10;pwr_gating_latency&#61;300&#10;simpoint_start_insts&#61;&#10;socket_id&#61;0&#10;switched_out&#61;false&#10;syscallRetryLatency&#61;10000&#10;system&#61;system&#10;tracer&#61;system.cpu.tracer&#10;wait_for_remote_gdb&#61;false&#10;workload&#61;system.cpu.workload">
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<text text-anchor="middle" x="552" y="-453.8" font-family="Arial" font-size="14.00" fill="#000000">cpu </text>
<text text-anchor="middle" x="552" y="-438.8" font-family="Arial" font-size="14.00" fill="#000000">: TimingSimpleCPU</text>
</a>
</g>
</g>
<g id="clust15" class="cluster"><title>cluster_system_cpu_dtb</title>
<g id="a_clust15"><a xlink:title="eventq_index&#61;0&#10;size&#61;64&#10;walker&#61;system.cpu.dtb.walker">
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<text text-anchor="middle" x="610" y="-407.8" font-family="Arial" font-size="14.00" fill="#000000">dtb </text>
<text text-anchor="middle" x="610" y="-392.8" font-family="Arial" font-size="14.00" fill="#000000">: X86TLB</text>
</a>
</g>
</g>
<g id="clust16" class="cluster"><title>cluster_system_cpu_dtb_walker</title>
<g id="a_clust16"><a xlink:title="clk_domain&#61;system.cpu_clk_domain&#10;default_p_state&#61;UNDEFINED&#10;eventq_index&#61;0&#10;num_squash_per_cycle&#61;4&#10;p_state_clk_gate_bins&#61;20&#10;p_state_clk_gate_max&#61;1000000000000&#10;p_state_clk_gate_min&#61;1000&#10;power_model&#61;&#10;system&#61;system">
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<text text-anchor="middle" x="610" y="-346.8" font-family="Arial" font-size="14.00" fill="#000000">: X86PagetableWalker</text>
</a>
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</g>
<g id="clust17" class="cluster"><title>cluster_system_cpu_interrupts</title>
<g id="a_clust17"><a xlink:title="clk_domain&#61;system.cpu.apic_clk_domain&#10;default_p_state&#61;UNDEFINED&#10;eventq_index&#61;0&#10;int_latency&#61;1000&#10;p_state_clk_gate_bins&#61;20&#10;p_state_clk_gate_max&#61;1000000000000&#10;p_state_clk_gate_min&#61;1000&#10;pio_addr&#61;2305843009213693952&#10;pio_latency&#61;100000&#10;power_model&#61;&#10;system&#61;system">
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<text text-anchor="middle" x="836" y="-361.8" font-family="Arial" font-size="14.00" fill="#000000">interrupts </text>
<text text-anchor="middle" x="836" y="-346.8" font-family="Arial" font-size="14.00" fill="#000000">: X86LocalApic</text>
</a>
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</g>
<g id="clust18" class="cluster"><title>cluster_system_cpu_itb</title>
<g id="a_clust18"><a xlink:title="eventq_index&#61;0&#10;size&#61;64&#10;walker&#61;system.cpu.itb.walker">
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<text text-anchor="middle" x="324" y="-392.8" font-family="Arial" font-size="14.00" fill="#000000">: X86TLB</text>
</a>
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</g>
<g id="clust19" class="cluster"><title>cluster_system_cpu_itb_walker</title>
<g id="a_clust19"><a xlink:title="clk_domain&#61;system.cpu_clk_domain&#10;default_p_state&#61;UNDEFINED&#10;eventq_index&#61;0&#10;num_squash_per_cycle&#61;4&#10;p_state_clk_gate_bins&#61;20&#10;p_state_clk_gate_max&#61;1000000000000&#10;p_state_clk_gate_min&#61;1000&#10;power_model&#61;&#10;system&#61;system">
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<text text-anchor="middle" x="324" y="-346.8" font-family="Arial" font-size="14.00" fill="#000000">: X86PagetableWalker</text>
</a>
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</g>
<!-- system_system_port -->
<g id="node1" class="node"><title>system_system_port</title>
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<text text-anchor="middle" x="72" y="-308.8" font-family="Arial" font-size="14.00" fill="#000000">system_port</text>
</g>
<!-- system_membus_slave -->
<g id="node3" class="node"><title>system_membus_slave</title>
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<text text-anchor="middle" x="516" y="-177.8" font-family="Arial" font-size="14.00" fill="#000000">slave</text>
</g>
<!-- system_system_port&#45;&gt;system_membus_slave -->
<g id="edge1" class="edge"><title>system_system_port&#45;&gt;system_membus_slave</title>
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<!-- system_membus_master -->
<g id="node2" class="node"><title>system_membus_master</title>
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<!-- system_external_memory_port -->
<g id="node4" class="node"><title>system_external_memory_port</title>
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<!-- system_membus_master&#45;&gt;system_external_memory_port -->
<g id="edge4" class="edge"><title>system_membus_master&#45;&gt;system_external_memory_port</title>
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<!-- system_cpu_interrupts_int_slave -->
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<!-- system_membus_master&#45;&gt;system_cpu_interrupts_int_slave -->
<g id="edge3" class="edge"><title>system_membus_master&#45;&gt;system_cpu_interrupts_int_slave</title>
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<!-- system_membus_master&#45;&gt;system_cpu_interrupts_pio -->
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<!-- system_cpu_icache_port&#45;&gt;system_membus_slave -->
<g id="edge5" class="edge"><title>system_cpu_icache_port&#45;&gt;system_membus_slave</title>
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<!-- system_cpu_dcache_port&#45;&gt;system_membus_slave -->
<g id="edge6" class="edge"><title>system_cpu_dcache_port&#45;&gt;system_membus_slave</title>
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<!-- system_cpu_dtb_walker_port&#45;&gt;system_membus_slave -->
<g id="edge7" class="edge"><title>system_cpu_dtb_walker_port&#45;&gt;system_membus_slave</title>
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Width:  |  Height:  |  Size: 20 KiB

282
DRAMSys/gem5/gem5_se/hello-x86/config.ini Normal file
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@@ -0,0 +1,282 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler external_memory membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=false
kernel_extras=
kvm_vm=Null
load_addr_mask=18446744073709551615
load_offset=0
mem_mode=timing
mem_ranges=0:536870911:0:0:0:0
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=apic_clk_domain dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_gating_on_idle=false
power_model=
profile=0
progress_interval=0
pwr_gating_latency=300
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.apic_clk_domain]
type=DerivedClockDomain
clk_divider=16
clk_domain=system.cpu_clk_domain
eventq_index=0
[system.cpu.dtb]
type=X86TLB
children=walker
eventq_index=0
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
num_squash_per_cycle=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
system=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=X86LocalApic
clk_domain=system.cpu.apic_clk_domain
default_p_state=UNDEFINED
eventq_index=0
int_latency=1000
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=2305843009213693952
pio_latency=100000
power_model=
system=system
int_master=system.membus.slave[5]
int_slave=system.membus.master[1]
pio=system.membus.master[0]
[system.cpu.isa]
type=X86ISA
eventq_index=0
[system.cpu.itb]
type=X86TLB
children=walker
eventq_index=0
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
num_squash_per_cycle=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
system=system
port=system.membus.slave[3]
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=Process
cmd=../../DRAMSys/gem5/gem5_se/hello-x86/hello
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=../../DRAMSys/gem5/gem5_se/hello-x86/hello
gid=100
input=cin
kvmInSE=false
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=0
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.cpu_voltage_domain
[system.cpu_voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.external_memory]
type=ExternalSlave
addr_ranges=0:536870911:0:0:0:0
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
port_data=transactor
port_type=tlm_slave
power_model=
port=system.membus.master[2]
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
point_of_unification=true
power_model=
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.external_memory.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
range=0:134217727:0:0:0:0
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0

397
DRAMSys/gem5/gem5_se/hello-x86/config.json Normal file
View File

@@ -0,0 +1,397 @@
{
"name": null,
"sim_quantum": 0,
"system": {
"kernel": "",
"mmap_using_noreserve": false,
"kernel_addr_check": false,
"membus": {
"point_of_coherency": true,
"system": "system",
"response_latency": 2,
"cxx_class": "CoherentXBar",
"forward_latency": 4,
"clk_domain": "system.clk_domain",
"point_of_unification": true,
"width": 16,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"master": {
"peer": [
"system.cpu.interrupts.pio",
"system.cpu.interrupts.int_slave",
"system.external_memory.port"
],
"role": "MASTER"
},
"type": "CoherentXBar",
"frontend_latency": 3,
"slave": {
"peer": [
"system.system_port",
"system.cpu.icache_port",
"system.cpu.dcache_port",
"system.cpu.itb.walker.port",
"system.cpu.dtb.walker.port",
"system.cpu.interrupts.int_master"
],
"role": "SLAVE"
},
"p_state_clk_gate_min": 1000,
"snoop_filter": {
"name": "snoop_filter",
"system": "system",
"max_capacity": 8388608,
"eventq_index": 0,
"cxx_class": "SnoopFilter",
"path": "system.membus.snoop_filter",
"type": "SnoopFilter",
"lookup_latency": 1
},
"power_model": [],
"path": "system.membus",
"snoop_response_latency": 4,
"name": "membus",
"p_state_clk_gate_bins": 20,
"use_default_range": false
},
"symbolfile": "",
"kvm_vm": null,
"readfile": "",
"thermal_model": null,
"cxx_class": "System",
"work_begin_cpu_id_exit": -1,
"load_offset": 0,
"work_begin_exit_count": 0,
"p_state_clk_gate_min": 1000,
"memories": [
"system.physmem"
],
"work_begin_ckpt_count": 0,
"clk_domain": {
"name": "clk_domain",
"clock": [
1000
],
"init_perf_level": 0,
"voltage_domain": "system.voltage_domain",
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.clk_domain",
"type": "SrcClockDomain",
"domain_id": -1
},
"mem_ranges": [
"0:536870911:0:0:0:0"
],
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"dvfs_handler": {
"enable": false,
"name": "dvfs_handler",
"sys_clk_domain": "system.clk_domain",
"transition_latency": 100000000,
"eventq_index": 0,
"cxx_class": "DVFSHandler",
"domains": [],
"path": "system.dvfs_handler",
"type": "DVFSHandler"
},
"work_end_exit_count": 0,
"type": "System",
"voltage_domain": {
"name": "voltage_domain",
"eventq_index": 0,
"voltage": [
1.0
],
"cxx_class": "VoltageDomain",
"path": "system.voltage_domain",
"type": "VoltageDomain"
},
"cache_line_size": 64,
"external_memory": {
"name": "external_memory",
"p_state_clk_gate_min": 1000,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"clk_domain": "system.clk_domain",
"power_model": [],
"addr_ranges": [
"0:536870911:0:0:0:0"
],
"eventq_index": 0,
"port_type": "tlm_slave",
"cxx_class": "ExternalSlave",
"p_state_clk_gate_max": 1000000000000,
"path": "system.external_memory",
"type": "ExternalSlave",
"port": {
"peer": "system.membus.master[2]",
"role": "SLAVE"
},
"port_data": "transactor"
},
"boot_osflags": "a",
"system_port": {
"peer": "system.membus.slave[0]",
"role": "MASTER"
},
"physmem": {
"range": "0:134217727:0:0:0:0",
"latency": 30000,
"name": "physmem",
"p_state_clk_gate_min": 1000,
"eventq_index": 0,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"kvm_map": true,
"clk_domain": "system.clk_domain",
"power_model": [],
"latency_var": 0,
"bandwidth": "73.000000",
"conf_table_reported": true,
"cxx_class": "SimpleMemory",
"p_state_clk_gate_max": 1000000000000,
"path": "system.physmem",
"null": false,
"type": "SimpleMemory",
"in_addr_map": true
},
"power_model": [],
"work_cpus_ckpt_count": 0,
"thermal_components": [],
"path": "system",
"cpu_clk_domain": {
"name": "cpu_clk_domain",
"clock": [
500
],
"init_perf_level": 0,
"voltage_domain": "system.cpu_voltage_domain",
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.cpu_clk_domain",
"type": "SrcClockDomain",
"domain_id": -1
},
"work_end_ckpt_count": 0,
"mem_mode": "timing",
"name": "system",
"init_param": 0,
"p_state_clk_gate_bins": 20,
"kernel_extras": [],
"load_addr_mask": 18446744073709551615,
"cpu": [
{
"do_statistics_insts": true,
"numThreads": 1,
"itb": {
"name": "itb",
"eventq_index": 0,
"cxx_class": "X86ISA::TLB",
"walker": {
"name": "walker",
"p_state_clk_gate_min": 1000,
"p_state_clk_gate_bins": 20,
"cxx_class": "X86ISA::Walker",
"clk_domain": "system.cpu_clk_domain",
"power_model": [],
"system": "system",
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"path": "system.cpu.itb.walker",
"type": "X86PagetableWalker",
"port": {
"peer": "system.membus.slave[3]",
"role": "MASTER"
},
"num_squash_per_cycle": 4
},
"path": "system.cpu.itb",
"type": "X86TLB",
"size": 64
},
"power_gating_on_idle": false,
"function_trace": false,
"do_checkpoint_insts": true,
"cxx_class": "TimingSimpleCPU",
"max_loads_all_threads": 0,
"system": "system",
"apic_clk_domain": {
"name": "apic_clk_domain",
"clk_domain": "system.cpu_clk_domain",
"eventq_index": 0,
"cxx_class": "DerivedClockDomain",
"path": "system.cpu.apic_clk_domain",
"type": "DerivedClockDomain",
"clk_divider": 16
},
"clk_domain": "system.cpu_clk_domain",
"function_trace_start": 0,
"cpu_id": 0,
"checker": null,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"do_quiesce": true,
"type": "TimingSimpleCPU",
"profile": 0,
"icache_port": {
"peer": "system.membus.slave[1]",
"role": "MASTER"
},
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1000,
"syscallRetryLatency": 10000,
"interrupts": [
{
"int_master": {
"peer": "system.membus.slave[5]",
"role": "MASTER"
},
"name": "interrupts",
"p_state_clk_gate_min": 1000,
"pio": {
"peer": "system.membus.master[0]",
"role": "SLAVE"
},
"int_slave": {
"peer": "system.membus.master[1]",
"role": "SLAVE"
},
"p_state_clk_gate_bins": 20,
"cxx_class": "X86ISA::Interrupts",
"pio_latency": 100000,
"clk_domain": "system.cpu.apic_clk_domain",
"power_model": [],
"system": "system",
"int_latency": 1000,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"path": "system.cpu.interrupts",
"pio_addr": 2305843009213693952,
"type": "X86LocalApic"
}
],
"dcache_port": {
"peer": "system.membus.slave[2]",
"role": "MASTER"
},
"socket_id": 0,
"power_model": [],
"max_insts_all_threads": 0,
"path": "system.cpu",
"pwr_gating_latency": 300,
"max_loads_any_thread": 0,
"switched_out": false,
"workload": [
{
"uid": 100,
"pid": 100,
"kvmInSE": false,
"cxx_class": "Process",
"executable": "tests/test-progs/hello/bin/x86/linux/hello",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
"maxStackSize": 67108864,
"ppid": 0,
"type": "Process",
"cwd": "/media/disk2/gem5_tnt/gem5",
"pgid": 100,
"simpoint": 0,
"euid": 100,
"input": "cin",
"path": "system.cpu.workload",
"name": "workload",
"cmd": [
"tests/test-progs/hello/bin/x86/linux/hello"
],
"errout": "cerr",
"useArchPT": false,
"egid": 100,
"output": "cout"
}
],
"name": "cpu",
"wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,
"cxx_class": "X86ISA::TLB",
"walker": {
"name": "walker",
"p_state_clk_gate_min": 1000,
"p_state_clk_gate_bins": 20,
"cxx_class": "X86ISA::Walker",
"clk_domain": "system.cpu_clk_domain",
"power_model": [],
"system": "system",
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"path": "system.cpu.dtb.walker",
"type": "X86PagetableWalker",
"port": {
"peer": "system.membus.slave[4]",
"role": "MASTER"
},
"num_squash_per_cycle": 4
},
"path": "system.cpu.dtb",
"type": "X86TLB",
"size": 64
},
"simpoint_start_insts": [],
"max_insts_any_thread": 0,
"progress_interval": 0,
"branchPred": null,
"isa": [
{
"eventq_index": 0,
"path": "system.cpu.isa",
"type": "X86ISA",
"name": "isa",
"cxx_class": "X86ISA::ISA"
}
],
"tracer": {
"eventq_index": 0,
"path": "system.cpu.tracer",
"type": "ExeTracer",
"name": "tracer",
"cxx_class": "Trace::ExeTracer"
}
}
],
"multi_thread": false,
"cpu_voltage_domain": {
"name": "cpu_voltage_domain",
"eventq_index": 0,
"voltage": [
1.0
],
"cxx_class": "VoltageDomain",
"path": "system.cpu_voltage_domain",
"type": "VoltageDomain"
},
"num_work_ids": 16,
"work_item_id": -1,
"exit_on_work_items": false
},
"time_sync_period": 100000000000,
"eventq_index": 0,
"time_sync_spin_threshold": 100000000,
"cxx_class": "Root",
"path": "root",
"time_sync_enable": false,
"type": "Root",
"full_system": false
}

BIN
DRAMSys/gem5/gem5_se/hello-x86/hello Executable file
View File

Binary file not shown.

4
DRAMSys/gem5/gem5_se/run.sh
View File

@@ -97,7 +97,9 @@ for s in $simfiles; do
cp $sf $simulation
logfile=${sfn}_${bin}.log
# LD_PRELOAD=/usr/lib/libtcmalloc.so ./${elf} ${simulation} ../../DRAMSys/gem5/gem5_se/${bin}/config.ini 1 > ${logfile} 2>&1 &
./${elf} ${simulation} ../../DRAMSys/gem5/gem5_se/${bin}/config.ini 1 > ${logfile} 2>&1 &
date >> ${logfile}
time ./${elf} ${simulation} ../../DRAMSys/gem5/gem5_se/${bin}/config.ini 1 >> ${logfile} 2>&1
date >> ${logfile}
done
done

75
DRAMSys/library/library.pro
View File

@@ -56,32 +56,44 @@ INCLUDEPATH += src/common/third_party/json/include
DEFINES += TIXML_USE_STL
DEFINES += SC_INCLUDE_DYNAMIC_PROCESSES
dramsys_disable_coverage_check = $$(DRAMSYS_DISABLE_COVERAGE_CHECK)
isEmpty(dramsys_disable_coverage_check) {
coverage_check = true
message(Coverage check ENABLED)
} else {
coverage_check = false
message(Coverage check DISABLED)
}
unix:!macx {
QMAKE_CXXFLAGS += -std=c++11 -O0 -g
QMAKE_CXXFLAGS += -std=c++11 -O0 -g
$$eval(coverage_check) {
QMAKE_CXXFLAGS += -fprofile-arcs -ftest-coverage -fPIC -O0
QMAKE_LFLAGS += -lgcov --coverage
}
}
macx: {
CONFIG += c++11
QMAKE_CXXFLAGS += -std=c++0x -stdlib=libc++ -O0 -g
QMAKE_MACOSX_DEPLOYMENT_TARGET=10.14
$$eval(coverage_check) {
QMAKE_CXXFLAGS += --coverage
QMAKE_LFLAGS += --coverage
}
}
QMAKE_CXXFLAGS += -isystem $${systemc_home}/include
SOURCES += \
src/common/third_party/tinyxml2/tinyxml2.cpp \
src/common/xmlAddressdecoder.cpp \
src/common/Utils.cpp \
src/common/TlmRecorder.cpp \
src/common/dramExtension.cpp \
src/common/DebugManager.cpp \
src/controller/core/configuration/Configuration.cpp \
src/controller/core/powerdown/PowerDownManagerTimeout.cpp \
src/controller/core/powerdown/PowerDownManagerBankwise.cpp \
src/controller/core/powerdown/PowerDownManager.cpp \
src/controller/scheduler/ThreadLoad.cpp \
src/controller/scheduler/PARBS.cpp \
src/controller/scheduler/Fr_Fcfs.cpp \
src/controller/scheduler/FrFcfs.cpp \
src/controller/scheduler/Fifo.cpp \
src/controller/scheduler/SMS.cpp \
src/controller/core/refresh/RefreshManagerBankwise.cpp \
@@ -97,12 +109,10 @@ SOURCES += \
src/controller/core/scheduling/checker/PreBChecker.cpp \
src/controller/core/scheduling/checker/ActBChecker.cpp \
src/controller/core/scheduling/ScheduledCommand.cpp \
src/controller/core/TimingCalculation.cpp \
src/controller/core/Slots.cpp \
src/controller/core/ControllerCore.cpp \
src/simulation/MemoryManager.cpp \
src/simulation/TemperatureController.cpp \
src/controller/scheduler/readwritegrouper.cpp \
src/controller/core/configuration/ConfigurationLoader.cpp \
src/controller/core/powerdown/NoPowerDown.cpp \
src/controller/Command.cpp \
@@ -122,29 +132,35 @@ SOURCES += \
src/error/ECC/Word.cpp \
src/error/eccbaseclass.cpp \
src/error/ecchamming.cpp \
src/controller/scheduler/Fr_Fcfs_read_priority.cpp \
src/controller/scheduler/Fr_Fcfs_grouper.cpp \
src/controller/scheduler/FrFcfsRp.cpp \
src/controller/scheduler/FrFcfsGrp.cpp \
src/controller/scheduler/Grp.cpp \
src/controller/RecordableController.cpp \
src/common/AddressDecoder.cpp \
src/controller/scheduler/grp.cpp \
src/common/congenAddressDecoder.cpp
src/simulation/Dram.cpp \
src/simulation/RecordableDram.cpp \
src/simulation/Arbiter.cpp \
src/common/CongenAddressDecoder.cpp \
src/common/XmlAddressDecoder.cpp \
src/controller/core/timingCalculations.cpp \
src/common/dramExtensions.cpp \
src/common/utils.cpp \
src/simulation/DramDDR3.cpp \
src/simulation/DramDDR4.cpp \
src/simulation/DramRecordable.cpp \
src/simulation/DramWideIO.cpp
HEADERS += \
src/common/third_party/tinyxml2/tinyxml2.h \
src/common/xmlAddressdecoder.h \
src/common/Utils.h \
src/common/TlmRecorder.h \
src/common/tlm2_base_protocol_checker.h \
src/common/protocol.h \
src/common/dramExtension.h \
src/common/DebugManager.h \
src/controller/core/configuration/Configuration.h \
src/controller/core/powerdown/PowerDownManagerTimeout.h \
src/controller/core/powerdown/PowerDownManagerBankwise.h \
src/controller/core/powerdown/PowerDownManager.h \
src/controller/scheduler/ThreadLoad.h \
src/controller/scheduler/PARBS.h \
src/controller/scheduler/Fr_Fcfs.h \
src/controller/scheduler/FrFcfs.h \
src/controller/scheduler/Fifo.h \
src/controller/scheduler/SMS.h \
src/controller/Controller.h \
@@ -162,9 +178,7 @@ HEADERS += \
src/controller/core/scheduling/checker/ActivateChecker.h \
src/controller/core/scheduling/checker/PreBChecker.h \
src/controller/core/scheduling/checker/ActBChecker.h \
src/controller/core/scheduling/Trigger.h \
src/controller/core/scheduling/ScheduledCommand.h \
src/controller/core/TimingCalculation.h \
src/controller/core/Slots.h \
src/controller/core/ControllerCore.h \
src/simulation/TracePlayer.h \
@@ -172,10 +186,8 @@ HEADERS += \
src/simulation/Dram.h \
src/simulation/Arbiter.h \
src/common/libDRAMPower.h \
src/controller/scheduler/readwritegrouper.h \
src/simulation/ReorderBuffer.h \
src/controller/core/configuration/MemSpec.h \
src/controller/core/configuration/thermalSimConfig.h \
src/simulation/StlPlayer.h \
src/simulation/TracePlayerListener.h \
src/simulation/TraceGenerator.h \
@@ -200,15 +212,24 @@ HEADERS += \
src/error/ECC/Word.h \
src/error/eccbaseclass.h \
src/error/ecchamming.h \
src/controller/scheduler/Fr_Fcfs_read_priority.h \
src/controller/scheduler/Fr_Fcfs_grouper.h \
src/controller/scheduler/FrFcfsRp.h \
src/controller/scheduler/FrFcfsGrp.h \
src/controller/scheduler/Grp.h \
src/simulation/IArbiter.h \
src/simulation/SimpleArbiter.h \
src/controller/RecordableController.h \
src/simulation/RecordableDram.h \
src/common/AddressDecoder.h \
src/controller/scheduler/grp.h \
src/common/congenAddressDecoder.h
src/common/CongenAddressDecoder.h \
src/common/XmlAddressDecoder.h \
src/controller/core/timingCalculations.h \
src/common/dramExtensions.h \
src/common/utils.h \
src/controller/core/configuration/TemperatureSimConfig.h \
src/simulation/DramDDR3.h \
src/simulation/DramDDR4.h \
src/simulation/DramRecordable.h \
src/simulation/DramWideIO.h
#src/common/third_party/json/include/nlohmann/json.hpp \
thermalsim = $$(THERMALSIM)

8
DRAMSys/library/resources/configs/amconfigs/rgram-rbc.xml Normal file
View File

@@ -0,0 +1,8 @@
<addressmapping>
<channel from="128" to="128" />
<row from="16" to="32" />
<bank from="13" to="15" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

2
DRAMSys/library/resources/configs/mcconfigs/fifo.xml
View File

@@ -1,7 +1,7 @@
<mcconfig>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
<Scheduler value="FIFO" />
<Scheduler value="Fifo" />
<Capsize value="5" />
<!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownMode value="NoPowerDown" />

2
DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml
View File

@@ -1,7 +1,7 @@
<mcconfig>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
<Scheduler value="FIFO_STRICT" />
<Scheduler value="FifoStrict" />
<Capsize value="5" />
<!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownMode value="NoPowerDown" />

2
DRAMSys/library/resources/configs/mcconfigs/fifo_ecc.xml
View File

@@ -1,7 +1,7 @@
<mcconfig>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
<Scheduler value="FIFO" />
<Scheduler value="Fifo" />
<Capsize value="5" />
<!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownMode value="NoPowerDown" />

2
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml
View File

@@ -1,7 +1,7 @@
<mcconfig>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
<Scheduler value="FR_FCFS" />
<Scheduler value="FrFcfs" />
<Capsize value="5" />
<!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownMode value="NoPowerDown" />

2
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml
View File

@@ -1,7 +1,7 @@
<mcconfig>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="16" />
<Scheduler value="FR_FCFS_GRP" />
<Scheduler value="FrFcfsGrp" />
<Capsize value="5" />
<!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownMode value="NoPowerDown" />

2
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rp.xml
View File

@@ -1,7 +1,7 @@
<mcconfig>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="16" />
<Scheduler value="FR_FCFS_RP" />
<Scheduler value="FrFcfsRp" />
<Capsize value="5" />
<!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownMode value="NoPowerDown" />

2
DRAMSys/library/resources/configs/mcconfigs/grp.xml
View File

@@ -1,7 +1,7 @@
<mcconfig>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="32" />
<Scheduler value="GRP" />
<Scheduler value="Grp" />
<Capsize value="5" />
<!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownMode value="NoPowerDown" />

2
DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml
View File

@@ -1,7 +1,7 @@
<mcconfig>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="16" />
<Scheduler value="FR_FCFS" />
<Scheduler value="FrFcfs" />
<Capsize value="5" />
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />

19
DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-fs.xml Normal file
View File

@@ -0,0 +1,19 @@
<simconfig>
<SimulationName value="rgr" />
<Debug value="0" />
<DatabaseRecording value="0" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="1"/>
<NumberOfDevicesOnDIMM value="4"/>
<CheckTLM2Protocol value = "0" />
<AddressOffset value = "2147483648" />
<ECCControllerMode value = "Disabled" />
<ErrorChipSeed value="42" />
<ErrorCSVFile value="" />
<StoreMode value="Store" />
<UseMalloc value="1" />
</simconfig>

33
DRAMSys/library/resources/resources.pri
View File

@@ -77,16 +77,41 @@ DISTFILES += resources/scripts/analyse_trace.pl
DISTFILES += resources/scripts/video_rendering/temperatur.job.pl
DISTFILES += resources/scripts/video_rendering/temperatur.pl
DISTFILES += resources/scripts/video_rendering/Makefile
DISTFILES += resources/scripts/DRAMSylva/LICENSE
DISTFILES += resources/scripts/DRAMSylva/README
DISTFILES += resources/scripts/DRAMSylva/DRAMSylva.patch
DISTFILES += resources/scripts/DRAMSylva/collect.sh
DISTFILES += resources/scripts/DRAMSylva/common.in
DISTFILES += resources/scripts/DRAMSylva/DRAMSylva.jobscript
DISTFILES += resources/scripts/DRAMSylva/DRAMSylva.sh
DISTFILES += resources/scripts/DRAMSylva/DRAMSylvaCSVPlot.py
DISTFILES += resources/scripts/DRAMSylva/DRAMSyrup.py
DISTFILES += resources/scripts/DRAMSylva/configs.json
DISTFILES += resources/scripts/DRAMSylva/gem5ilva.jobscript
DISTFILES += resources/scripts/DRAMSylva/gem5ilva.sh
DISTFILES += resources/scripts/DRAMSylva/gem5ilva_fs.jobscript
DISTFILES += resources/scripts/DRAMSylva/gem5ilva_fs.sh
DISTFILES += resources/scripts/DRAMSylva/LICENSE
DISTFILES += resources/scripts/DRAMSylva/README
DISTFILES += resources/scripts/DRAMSylva/configs_json/configs.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc1x.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc1x_gem5.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc2x.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc2x_gem5.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc4x.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc4x_gem5.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc1x.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc1x_gem5.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc1x_gem5_fs.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc1x_gem5_fs_nodb.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc2x.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc2x_gem5.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc4x.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc4x_gem5.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/ref.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/ref_bw.json
DISTFILES += resources/scripts/trace_gen.py
DISTFILES += resources/scripts/traceGenerationForNNTraining.pl
# Trace Files
DISTFILES += resources/traces/chstone-aes_32.stl
DISTFILES += resources/traces/test2.stl

20
DRAMSys/library/resources/simulations/rgrsim-gem5-fs.xml Normal file
View File

@@ -0,0 +1,20 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="rgrsim-gem5-fs"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="rgrsimcfg-gem5-fs.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification -->
<memspec src="rgrspec.xml"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="rgram.xml"></addressmapping>
<!-- Memory Controller Configuration -->
<mcconfig src="rgrmccfg.xml"/>
<!-- <tracesetup id="no_refresh_fr_fcfs_nbw_b16_ddr4_8b_1x"> -->
<!--
<tracesetup id="rgrsetup">
<device clkMhz="1000">1_720x1280_64-Pixelgroesse_imb3_str1_scram_ddr4_8b_same_clock.stl</device>
</tracesetup>
-->
</simulation>

6
DRAMSys/library/src/common/AddressDecoder.cpp
View File

@@ -34,8 +34,8 @@
*/
#include "AddressDecoder.h"
#include "xmlAddressdecoder.h"
#include "congenAddressDecoder.h"
#include "XmlAddressDecoder.h"
#include "CongenAddressDecoder.h"
AddressDecoder *AddressDecoder::m_pInstance = nullptr;
@@ -50,7 +50,7 @@ void AddressDecoder::createInstance(Type t)
assert(m_pInstance == nullptr);
switch (t) {
case Type::XML:
m_pInstance = new xmlAddressDecoder;
m_pInstance = new XmlAddressDecoder;
break;
case Type::CONGEN:
m_pInstance = new CongenAddressDecoder;

4
DRAMSys/library/src/common/congenAddressDecoder.cpp → DRAMSys/library/src/common/CongenAddressDecoder.cpp
View File

@@ -33,8 +33,8 @@
* Johannes Feldmann
*/
#include "congenAddressDecoder.h"
#include "Utils.h"
#include "CongenAddressDecoder.h"
#include "utils.h"
#include <fstream>

3
DRAMSys/library/src/common/congenAddressDecoder.h → DRAMSys/library/src/common/CongenAddressDecoder.h
View File

@@ -47,8 +47,7 @@ using std::vector;
using std::pair;
using std::map;
class CongenAddressDecoder
: private AddressDecoder
class CongenAddressDecoder : private AddressDecoder
{
// Friendship needed so that the AddressDecoder can access the
// constructor of this class to create the object in CreateInstance.

8
DRAMSys/library/src/common/DebugManager.h
View File

@@ -34,13 +34,13 @@
* Matthias Jung
*/
#ifndef DEBUGMANAGER_H_
#define DEBUGMANAGER_H_
#ifndef DEBUGMANAGER_H
#define DEBUGMANAGER_H
#include <systemc.h>
#include <string>
#include <set>
#include "Utils.h"
#include "utils.h"
class DebugManager
{
@@ -63,4 +63,4 @@ private:
ofstream debugFile;
};
#endif /* DEBUGMANAGER_H_ */
#endif // DEBUGMANAGER_H

10
DRAMSys/library/src/common/TlmRecorder.cpp
View File

@@ -41,8 +41,8 @@
#include "TlmRecorder.h"
#include "protocol.h"
#include "dramExtension.h"
#include "xmlAddressdecoder.h"
#include "dramExtensions.h"
#include "XmlAddressDecoder.h"
#include "../controller/core/configuration/Configuration.h"
#include "../controller/Controller.h"
@@ -325,9 +325,9 @@ void TlmRecorder::insertGeneralInfo()
sqlite3_bind_int64(insertGeneralInfoStatement, 2,
simulationTimeCoveredByRecording.value());
sqlite3_bind_int(insertGeneralInfoStatement, 3,
Configuration::getInstance().memSpec.NumberOfBanks);
Configuration::getInstance().memSpec->NumberOfBanks);
sqlite3_bind_int(insertGeneralInfoStatement, 4,
Configuration::getInstance().memSpec.clk.value());
Configuration::getInstance().memSpec->clk.value());
sqlite3_bind_text(insertGeneralInfoStatement, 5, "PS", 2, NULL);
sqlite3_bind_text(insertGeneralInfoStatement, 6, mcconfig.c_str(),
mcconfig.length(), NULL);
@@ -339,7 +339,7 @@ void TlmRecorder::insertGeneralInfo()
sqlite3_bind_int64(insertGeneralInfoStatement, 9, 0);
else
sqlite3_bind_int64(insertGeneralInfoStatement, 9,
(Configuration::getInstance().memSpec.clk *
(Configuration::getInstance().memSpec->clk *
Configuration::getInstance().WindowSize).value());
if (Configuration::getInstance().ControllerCoreRefEnablePostpone
|| Configuration::getInstance().ControllerCoreRefEnablePullIn) {

10
DRAMSys/library/src/common/TlmRecorder.h
View File

@@ -36,8 +36,8 @@
* Eder F. Zulian
*/
#ifndef TLMPHASERECORDER_H
#define TLMPHASERECORDER_H
#ifndef TLMRECORDER_H
#define TLMRECORDER_H
#include <iostream>
#include <ostream>
@@ -49,9 +49,9 @@
#include <cerrno>
#include <tlm.h>
#include <systemc.h>
#include "xmlAddressdecoder.h"
#include "XmlAddressDecoder.h"
#include "DebugManager.h"
#include "Utils.h"
#include "utils.h"
using namespace std;
@@ -151,5 +151,5 @@ private:
insertDebugMessageString, updateDataStrobeString, insertPowerString;
};
#endif
#endif // TLMRECORDER_H

20
DRAMSys/library/src/common/xmlAddressdecoder.cpp → DRAMSys/library/src/common/XmlAddressDecoder.cpp
View File

@@ -35,21 +35,21 @@
* Matthias Jung
*/
#include "xmlAddressdecoder.h"
#include "XmlAddressDecoder.h"
#include <systemc.h>
#include "Utils.h"
#include "utils.h"
#include "bitset"
#include "../controller/core/configuration/Configuration.h"
using namespace std;
using namespace tinyxml2;
xmlAddressDecoder::xmlAddressDecoder()
XmlAddressDecoder::XmlAddressDecoder()
{
addressmapping = NULL;
}
void xmlAddressDecoder::setConfiguration(std::string addressConfigURI)
void XmlAddressDecoder::setConfiguration(std::string addressConfigURI)
{
tinyxml2::XMLDocument doc;
loadXML(addressConfigURI, doc);
@@ -76,7 +76,7 @@ void xmlAddressDecoder::setConfiguration(std::string addressConfigURI)
}
DecodedAddress xmlAddressDecoder::decodeAddress(sc_dt::uint64 addr)
DecodedAddress XmlAddressDecoder::decodeAddress(sc_dt::uint64 addr)
{
DecodedAddress result;
result.channel = (addr & masks["channel"]) >> shifts["channel"];
@@ -84,15 +84,15 @@ DecodedAddress xmlAddressDecoder::decodeAddress(sc_dt::uint64 addr)
//result.bankgroup = (addr & masks["bankgroup"]) >> shifts["bankgroup"];
result.bank = (addr & masks["bank"]) >> shifts["bank"];
result.bankgroup = result.bank %
Configuration::getInstance().memSpec.NumberOfBankGroups;
result.rank = result.bank % Configuration::getInstance().memSpec.NumberOfRanks;
Configuration::getInstance().memSpec->NumberOfBankGroups;
result.rank = result.bank % Configuration::getInstance().memSpec->NumberOfRanks;
result.row = (addr & masks["row"]) >> shifts["row"];
result.column = (addr & masks["column"]) >> shifts["column"];
result.bytes = (addr & masks["bytes"]) >> shifts["bytes"];
return result;
}
sc_dt::uint64 xmlAddressDecoder::encodeAddress(DecodedAddress n)
sc_dt::uint64 XmlAddressDecoder::encodeAddress(DecodedAddress n)
{
return n.channel << shifts["channel"] |
n.rank << shifts["rank"] |
@@ -103,7 +103,7 @@ sc_dt::uint64 xmlAddressDecoder::encodeAddress(DecodedAddress n)
n.bytes << shifts["bytes"];
}
bool xmlAddressDecoder::testConfigFile(std::string url)
bool XmlAddressDecoder::testConfigFile(std::string url)
{
// Simple test if the root node has the correct name.
// This is suitable for now, but can be extended in future.
@@ -115,7 +115,7 @@ bool xmlAddressDecoder::testConfigFile(std::string url)
return (strcmp(addressMap->Name(), "addressmapping") == 0);
}
void xmlAddressDecoder::print()
void XmlAddressDecoder::print()
{
cout << headline << endl;
cout << "Address Mapping:" << endl << endl;

13
DRAMSys/library/src/common/xmlAddressdecoder.h → DRAMSys/library/src/common/XmlAddressDecoder.h
View File

@@ -35,17 +35,16 @@
* Matthias Jung
*/
#ifndef _XMLADDRESSDECODER_H
#define _XMLADDRESSDECODER_H
#ifndef XMLADDRESSDECODER_H
#define XMLADDRESSDECODER_H
#include <math.h>
#include "Utils.h"
#include "utils.h"
#include "third_party/tinyxml2/tinyxml2.h"
#include "AddressDecoder.h"
class xmlAddressDecoder
: private AddressDecoder
class XmlAddressDecoder : private AddressDecoder
{
// Friendship needed so that the AddressDecoder can access the
// constructor of this class to create the object in CreateInstance.
@@ -58,7 +57,7 @@ private:
tinyxml2::XMLElement *addressmapping;
public:
xmlAddressDecoder();
XmlAddressDecoder();
virtual DecodedAddress decodeAddress(sc_dt::uint64 addr);
virtual sc_dt::uint64 encodeAddress(DecodedAddress n);
@@ -71,4 +70,4 @@ public:
virtual void print();
};
#endif
#endif // XMLADDRESSDECODER_H

6
DRAMSys/library/src/common/dramExtension.cpp → DRAMSys/library/src/common/dramExtensions.cpp
View File

@@ -35,10 +35,10 @@
* Matthias Jung
*/
#include "dramExtension.h"
#include "dramExtensions.h"
#include "../controller/core/configuration/Configuration.h"
#include "map"
#include "Utils.h"
#include "utils.h"
using namespace tlm;
@@ -281,7 +281,7 @@ bool operator !=(const Row &lhs, const Row &rhs)
const Row Row::operator ++()
{
id = (id + 1) % Configuration::getInstance().memSpec.NumberOfRows;
id = (id + 1) % Configuration::getInstance().memSpec->NumberOfRows;
return *this;
}

54
DRAMSys/library/src/common/dramExtension.h → DRAMSys/library/src/common/dramExtensions.h
View File

@@ -34,26 +34,23 @@
* Matthias Jung
*/
#ifndef DRAMEXTENSION_H_
#define DRAMEXTENSION_H_
#ifndef DRAMEXTENSIONS_H
#define DRAMEXTENSIONS_H
#include <tlm.h>
#include <iostream>
#include <systemc.h>
class Thread
{
public:
explicit Thread(unsigned int id) :
id(id)
{
}
explicit Thread(unsigned int id) : id(id) {}
unsigned int ID() const
{
return id;
}
private:
unsigned int id;
};
@@ -61,14 +58,13 @@ private:
class Channel
{
public:
explicit Channel(unsigned int id) :
id(id)
{
}
explicit Channel(unsigned int id) : id(id) {}
unsigned int ID() const
{
return id;
}
private:
unsigned int id;
};
@@ -76,14 +72,13 @@ private:
class BankGroup
{
public:
explicit BankGroup(unsigned int id) :
id(id)
{
}
explicit BankGroup(unsigned int id) : id(id) {}
unsigned int ID() const
{
return id;
}
private:
unsigned int id;
};
@@ -91,10 +86,8 @@ private:
class Bank
{
public:
Bank(unsigned int id) :
id(id)
{
}
Bank(unsigned int id) : id(id) {}
unsigned int ID() const
{
return id;
@@ -110,7 +103,6 @@ public:
return std::to_string(id);
}
private:
unsigned int id;
};
@@ -120,14 +112,9 @@ class Row
public:
static const Row NO_ROW;
Row() :
id(0), isNoRow(true)
{
}
explicit Row(unsigned int id) :
id(id), isNoRow(false)
{
}
Row() : id(0), isNoRow(true) {}
explicit Row(unsigned int id) : id(id), isNoRow(false) {}
unsigned int ID() const
{
@@ -135,6 +122,7 @@ public:
}
const Row operator++();
private:
unsigned int id;
bool isNoRow;
@@ -145,21 +133,19 @@ private:
class Column
{
public:
explicit Column(unsigned int id) :
id(id)
{
}
explicit Column(unsigned int id) : id(id) {}
unsigned int ID() const
{
return id;
}
private:
unsigned int id;
};
class DramExtension: public tlm::tlm_extension<DramExtension>
class DramExtension : public tlm::tlm_extension<DramExtension>
{
public:
DramExtension();
@@ -251,4 +237,4 @@ bool operator!=(const Row &lhs, const Row &rhs);
bool operator==(const Column &lhs, const Column &rhs);
bool operator!=(const Column &lhs, const Column &rhs);
#endif /* DRAMEXTENSION_H_ */
#endif // DRAMEXTENSIONS_H

6
DRAMSys/library/src/common/protocol.h
View File

@@ -35,8 +35,8 @@
* Matthias Jung
*/
#ifndef EXTENDED_PHASE_DRAM
#define EXTENDED_PHASE_DRAM
#ifndef PROTOCOL_H
#define PROTOCOL_H
// DRAM Control Phases
DECLARE_EXTENDED_PHASE(BEGIN_PREB);
@@ -100,5 +100,5 @@ DECLARE_EXTENDED_PHASE(REF_TRIGGER);
DECLARE_EXTENDED_PHASE(PDN_TRIGGER);
#endif
#endif // PROTOCOL_H

2
DRAMSys/library/src/common/third_party/DRAMPower vendored

Submodule DRAMSys/library/src/common/third_party/DRAMPower updated: fa0627c4e6...746d56ea53

4
DRAMSys/library/src/common/Utils.cpp → DRAMSys/library/src/common/utils.cpp
View File

@@ -35,11 +35,11 @@
* Matthias Jung
*/
#include "Utils.h"
#include "utils.h"
#include <string>
#include <tlm.h>
#include <fstream>
#include "dramExtension.h"
#include "dramExtensions.h"
#include "../controller/Controller.h"
using namespace std;

8
DRAMSys/library/src/common/Utils.h → DRAMSys/library/src/common/utils.h
View File

@@ -35,8 +35,8 @@
* Eder F. Zulian
*/
#ifndef UTILS_COMMON_UTILS_H_
#define UTILS_COMMON_UTILS_H_
#ifndef UTILS_H
#define UTILS_H
#include <systemc.h>
#include <map>
@@ -44,7 +44,7 @@
#include <ostream>
#include <tlm.h>
#include <iomanip>
#include "dramExtension.h"
#include "dramExtensions.h"
#include "third_party/tinyxml2/tinyxml2.h"
#define DEF_SINGLETON( NAME ) \
@@ -148,5 +148,5 @@ double queryDoubleParameter(tinyxml2::XMLElement *node, std::string name);
void setUpDummy(tlm::tlm_generic_payload &payload, Bank &bank);
#endif /* UTILS_COMMON_H_ */
#endif // UTILS_H

7
DRAMSys/library/src/controller/Command.h
View File

@@ -33,13 +33,12 @@
* Janik Schlemminger
* Matthias Jung
*/
#ifndef COMMAND_H_
#define COMMAND_H_
#ifndef COMMAND_H
#define COMMAND_H
#include <string>
#include <vector>
enum class Command {
NOP,
PreB,
@@ -64,4 +63,4 @@ std::string commandToString(Command command);
const std::vector<Command> &getAllCommands();
bool commandIsIn(Command command, std::vector<Command> commands);
#endif /* COMMAND_H_ */
#endif // COMMAND_H

301
DRAMSys/library/src/controller/Controller.cpp
View File

@@ -39,22 +39,82 @@
#include "Controller.h"
#include <iostream>
Controller::Controller(sc_module_name /*name*/) :
frontendPEQ(this, &Controller::frontendPEQCallback),
dramPEQ(this, &Controller::dramPEQCallback),
controllerCorePEQ(this, &Controller::controllerCorePEQCallback),
debugManager(DebugManager::getInstance())
{
controllerCore = new ControllerCore("core", *this, numberOfPayloadsInSystem);
buildScheduler();
iSocket.register_nb_transport_bw(this, &Controller::nb_transport_bw);
tSocket.register_nb_transport_fw(this, &Controller::nb_transport_fw);
tSocket.register_transport_dbg(this, &Controller::transport_dbg);
}
Controller::~Controller()
{
// Bandwidth:
sc_time activeTime = numberOfTransactionsServed
* Configuration::getInstance().memSpec->BurstLength
/ Configuration::getInstance().memSpec->DataRate
* Configuration::getInstance().memSpec->clk;
sc_time idleTime = getIdleTime();
sc_time endTime = getEndTime();
sc_time startTime = getStartTime();
double bandwidth = (activeTime / (endTime - startTime) * 100);
double bandwidth_IDLE = ((activeTime) / (endTime - startTime - idleTime) * 100);
double maxBandwidth = (
// clk in Mhz e.g. 800 [MHz]:
(1000000 / Configuration::getInstance().memSpec->clk.to_double())
// DataRate e.g. 2
* Configuration::getInstance().memSpec->DataRate
// BusWidth e.g. 8 or 64
* Configuration::getInstance().memSpec->bitWidth
// Number of devices on a DIMM e.g. 8
* Configuration::getInstance().NumberOfDevicesOnDIMM ) / ( 1024 );
cout << name() << string(" Total Time: ")
<< (endTime - startTime).to_string()
<< endl;
cout << name() << string(" AVG BW: ")
<< std::fixed << std::setprecision(2)
<< ((bandwidth / 100)*maxBandwidth)
<< " Gibit/s (" << bandwidth << " %)"
<< endl;
cout << name() << string(" AVG BW/IDLE: ")
<< std::fixed << std::setprecision(2)
<< ((bandwidth_IDLE / 100)*maxBandwidth)
<< " Gibit/s (" << (bandwidth_IDLE) << " %)"
<< endl;
cout << name() << string(" MAX BW: ")
<< std::fixed << std::setprecision(2)
<< maxBandwidth << " Gibit/s"
<< endl;
delete controllerCore;
delete scheduler;
}
void Controller::buildScheduler()
{
string selectedScheduler = Configuration::getInstance().Scheduler;
if (selectedScheduler == "FIFO") {
if (selectedScheduler == "Fifo") {
scheduler = new Fifo(*controllerCore);
} else if (selectedScheduler == "FIFO_STRICT") {
} else if (selectedScheduler == "FifoStrict") {
scheduler = new FifoStrict(*this, *controllerCore);
} else if (selectedScheduler == "FR_FCFS") {
scheduler = new FR_FCFS(*controllerCore);
} else if (selectedScheduler == "FR_FCFS_RP") {
scheduler = new FR_FCFS_RP(*controllerCore);
} else if (selectedScheduler == "FR_FCFS_GRP") {
scheduler = new FR_FCFS_GRP(*controllerCore, this);
} else if (selectedScheduler == "GRP") {
scheduler = new GRP(*controllerCore, this);
} else if (selectedScheduler == "FrFcfs") {
scheduler = new FrFcfs(*controllerCore);
} else if (selectedScheduler == "FrFcfsRp") {
scheduler = new FrFcfsRp(*controllerCore);
} else if (selectedScheduler == "FrFcfsGrp") {
scheduler = new FrFcfsGrp(*controllerCore, this);
} else if (selectedScheduler == "Grp") {
scheduler = new Grp(*controllerCore, this);
} else if (selectedScheduler == "SMS") {
scheduler = new SMS("SMS", *controllerCore,
Configuration::getInstance().SJFProbability);
@@ -80,7 +140,8 @@ void Controller::send(const ScheduledCommand &command,
tlm_phase phase;
switch (command.getCommand()) {
switch (command.getCommand())
{
//TODO: refactor tlm recorder
case Command::Read:
phase = BEGIN_RD;
@@ -95,9 +156,9 @@ void Controller::send(const ScheduledCommand &command,
phase = BEGIN_WRA;
break;
case Command::AutoRefresh:
if (!Configuration::getInstance().BankwiseLogic) {
if (!Configuration::getInstance().BankwiseLogic)
phase = BEGIN_REFA;
} else
else
phase = BEGIN_REFB;
break;
case Command::Activate:
@@ -116,39 +177,39 @@ void Controller::send(const ScheduledCommand &command,
phase = BEGIN_PRE_ALL;
break;
case Command::PDNA:
if (!Configuration::getInstance().BankwiseLogic) {
if (!Configuration::getInstance().BankwiseLogic)
phase = BEGIN_PDNA;
} else
else
phase = BEGIN_PDNAB;
break;
case Command::PDNAX:
if (!Configuration::getInstance().BankwiseLogic) {
if (!Configuration::getInstance().BankwiseLogic)
phase = END_PDNA;
} else
else
phase = END_PDNAB;
break;
case Command::PDNP:
if (!Configuration::getInstance().BankwiseLogic) {
if (!Configuration::getInstance().BankwiseLogic)
phase = BEGIN_PDNP;
} else
else
phase = BEGIN_PDNPB;
break;
case Command::PDNPX:
if (!Configuration::getInstance().BankwiseLogic) {
if (!Configuration::getInstance().BankwiseLogic)
phase = END_PDNP;
} else
else
phase = END_PDNPB;
break;
case Command::SREF:
if (!Configuration::getInstance().BankwiseLogic) {
if (!Configuration::getInstance().BankwiseLogic)
phase = BEGIN_SREF;
} else
else
phase = BEGIN_SREFB;
break;
case Command::SREFX:
if (!Configuration::getInstance().BankwiseLogic) {
if (!Configuration::getInstance().BankwiseLogic)
phase = END_SREF;
} else
else
phase = END_SREFB;
break;
default:
@@ -187,18 +248,23 @@ void Controller::send(Trigger trigger, sc_time time,
void Controller::controllerCorePEQCallback(tlm_generic_payload &payload,
const tlm_phase &phase)
{
if (phase == REF_TRIGGER) {
if (phase == REF_TRIGGER)
{
controllerCore->triggerRefresh(payload);
} else if (phase == PDN_TRIGGER) {
}
else if (phase == PDN_TRIGGER)
{
controllerCore->powerDownManager->sleep(DramExtension::getExtension(
payload).getBank(), sc_time_stamp());
} else {
}
else
{
Bank bank = DramExtension::getBank(payload);
sendToDram(payload, phase, SC_ZERO_TIME);
if (phase == BEGIN_RD || phase == BEGIN_WR) {
if (phase == BEGIN_RD || phase == BEGIN_WR)
scheduleNextFromScheduler(DramExtension::getBank(payload));
} else if (phase == BEGIN_REFB)
else if (phase == BEGIN_REFB)
printDebugMessage("Entering REFB on bank " + to_string(bank.ID()));
else if (phase == BEGIN_REFA)
printDebugMessage("Entering REFA");
@@ -229,18 +295,20 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &payload,
{
sc_time notDelay = fwDelay;
if (phase == BEGIN_REQ) {
notDelay += Configuration::getInstance().memSpec.clk;
if (phase == BEGIN_REQ)
{
notDelay += Configuration::getInstance().memSpec->clk;
//Bandwidth IDLE
if ((getTotalNumberOfPayloadsInSystem() == 0) && idleState) {
// Bandwidth IDLE
if ((getTotalNumberOfPayloadsInSystem() == 0) && idleState)
endBandwidthIdleCollector();
}
} else if (phase == END_RESP) {
// Badnwith IDLE
if (getTotalNumberOfPayloadsInSystem() == 1) {
}
else if (phase == END_RESP)
{
// Bandwidth IDLE
// TODO: getTotalNumberOfPayloadsInSystem() == 1 && !idleState ??
if (getTotalNumberOfPayloadsInSystem() == 1)
startBandwidthIdleCollector();
}
}
printDebugMessage("[fw] " + phaseNameToString(phase) + " notification in " +
@@ -258,27 +326,37 @@ unsigned int Controller::transport_dbg(tlm::tlm_generic_payload &trans)
void Controller::frontendPEQCallback(tlm_generic_payload &payload,
const tlm_phase &phase)
{
if (phase == BEGIN_REQ) {
printDebugMessage(string("Payload in system: ") + to_string(
getTotalNumberOfPayloadsInSystem()));
if (phase == BEGIN_REQ)
{
printDebugMessage(string("Payloads in system: ") +
to_string(getTotalNumberOfPayloadsInSystem()));
payload.acquire();
payloadEntersSystem(payload);
if (getTotalNumberOfPayloadsInSystem() >
controllerCore->config.MaxNrOfTransactions) {
controllerCore->config.MaxNrOfTransactions)
{
printDebugMessage("##Backpressure: Max number of transactions in system reached");
backpressure = &payload;
return;
}
payload.set_response_status(tlm::TLM_OK_RESPONSE);
sendToFrontend(payload, END_REQ, SC_ZERO_TIME);
else
{
payload.set_response_status(tlm::TLM_OK_RESPONSE);
sendToFrontend(payload, END_REQ, SC_ZERO_TIME);
scheduler->storeRequest(&payload);
scheduleNextFromScheduler(DramExtension::getExtension(payload).getBank());
} else if (phase == PendingRequest) {
scheduler->storeRequest(&payload);
scheduleNextFromScheduler(DramExtension::getExtension(payload).getBank());
}
}
else if (phase == PendingRequest)
{
// Schedule a pending request.
scheduleNextFromScheduler(DramExtension::getExtension(payload).getBank());
} else if (phase == END_RESP) {
if (backpressure != NULL) {
}
else if (phase == END_RESP)
{
if (backpressure != NULL)
{
printDebugMessage("##Backpressure released");
backpressure->set_response_status(tlm::TLM_OK_RESPONSE);
sendToFrontend(*backpressure, END_REQ, SC_ZERO_TIME);
@@ -289,8 +367,14 @@ void Controller::frontendPEQCallback(tlm_generic_payload &payload,
}
payloadLeavesSystem(payload);
responseQueue.pop();
payload.release();
} else {
if(!responseQueue.empty())
sendToFrontend(*(responseQueue.front()), BEGIN_RESP, SC_ZERO_TIME);
}
else
{
SC_REPORT_FATAL(0,
"Front-end PEQ in controller wrapper was triggered with unknown phase");
}
@@ -299,15 +383,16 @@ void Controller::frontendPEQCallback(tlm_generic_payload &payload,
void Controller::payloadEntersSystem(tlm_generic_payload &payload)
{
Bank bank = DramExtension::getExtension(payload).getBank();
numberOfPayloadsInSystem[bank]++;
printDebugMessage(
"Payload enters system on bank " + to_string(bank.ID()) +
". Total number of payloads in Controller: "
+ to_string(getTotalNumberOfPayloadsInSystem()));
numberOfPayloadsInSystem[bank]++;
// Set Start Time for Simulation
if (startTimeSet == false) {
if (!startTimeSet)
{
printDebugMessage("Simulation Timer Start");
startTime = sc_time_stamp() - Configuration::getInstance().memSpec.clk;
startTime = sc_time_stamp() - Configuration::getInstance().memSpec->clk;
startTimeSet = true;
}
}
@@ -326,51 +411,66 @@ void Controller::payloadLeavesSystem(tlm_generic_payload &payload)
unsigned int Controller::getTotalNumberOfPayloadsInSystem()
{
unsigned int sum = 0;
for (Bank bank : controllerCore->getBanks()) {
for (Bank bank : controllerCore->getBanks())
sum += numberOfPayloadsInSystem[bank];
}
return sum;
}
void Controller::scheduleNextFromScheduler(Bank bank)
{
if (controllerCore->bankIsBusy(bank)) {
if (controllerCore->bankIsBusy(bank))
return;
}
// TODO: rescheduled always true?
bool rescheduled = true;
pair<Command, tlm::tlm_generic_payload *> nextRequest =
scheduler->getNextRequest(bank);
if (nextRequest.second != NULL) {
if (nextRequest.second != NULL)
{
schedule(nextRequest.first, *nextRequest.second);
} else {
}
else
{
gp *pendingRequest = scheduler->getPendingRequest(bank);
if (pendingRequest != NULL) {
// TODO: if path (pendingRequest != NULL) is only used by SMS scheduler
if (pendingRequest != NULL)
{
rescheduled = true;
frontendPEQ.notify(*(pendingRequest), PendingRequest,
Configuration::getInstance().memSpec.clk);
Configuration::getInstance().memSpec->clk);
}
}
// TODO: only used with FifoStrict scheduler
queue<Bank> blocked;
while (!blockedRequests.empty()) {
while (!blockedRequests.empty())
{
bank = blockedRequests.front();
blockedRequests.pop();
pair<Command, tlm::tlm_generic_payload *> nextRequest =
scheduler->getNextRequest(bank);
if (nextRequest.second != NULL) {
if (nextRequest.second != NULL)
{
schedule(nextRequest.first, *nextRequest.second);
} else {
}
else
{
gp *pendingRequest = scheduler->getPendingRequest(bank);
if (pendingRequest != NULL) {
if (pendingRequest != NULL)
{
//Pending request
if (!rescheduled) {
if (!rescheduled)
{
// TODO: never reached, rescheduled is always true
rescheduled = true;
frontendPEQ.notify(*(pendingRequest), PendingRequest,
Configuration::getInstance().memSpec.clk);
} else
Configuration::getInstance().memSpec->clk);
}
else
{
blocked.push(bank);
}
}
}
}
@@ -381,7 +481,8 @@ void Controller::schedule(Command command, gp &payload)
{
controllerCore->powerDownManager->wakeUp(DramExtension::getBank(payload),
sc_time_stamp());
if (controllerCore->scheduleRequest(command, payload)) {
if (controllerCore->scheduleRequest(command, payload))
{
printDebugMessage("\t-> Next payload was scheduled by core [" + commandToString(
command) + "] (unblocked)");
}
@@ -411,41 +512,59 @@ void Controller::dramPEQCallback(tlm_generic_payload &payload,
printDebugMessage("Received " + phaseNameToString(phase) + " on bank " +
to_string(bank.ID()) + " from DRAM");
if (phase == END_RD || phase == END_WR) {
sendToFrontend(payload, BEGIN_RESP, SC_ZERO_TIME);
} else if (phase == END_RDA || phase == END_WRA) {
sendToFrontend(payload, BEGIN_RESP, SC_ZERO_TIME);
if (phase == END_RD || phase == END_WR)
{
if(responseQueue.empty())
sendToFrontend(payload, BEGIN_RESP, SC_ZERO_TIME);
responseQueue.push(&payload);
}
else if (phase == END_RDA || phase == END_WRA)
{
if(responseQueue.empty())
sendToFrontend(payload, BEGIN_RESP, SC_ZERO_TIME);
responseQueue.push(&payload);
scheduleNextFromScheduler(bank);
} else if (phase == END_REFA) {
}
else if (phase == END_REFA)
{
printDebugMessage("Finished auto refresh on all banks ");
bool sleepy = true;
for (Bank bank : controllerCore->getBanks()) {
if (numberOfPayloadsInSystem[bank] != 0) {
for (Bank bank : controllerCore->getBanks())
{
if (numberOfPayloadsInSystem[bank] != 0)
{
sleepy = false;
scheduleNextFromScheduler(bank);
}
}
if (sleepy == true) {
if (sleepy == true)
controllerCore->powerDownManager->sleep(0, sc_time_stamp());
}
} else if (phase == END_REFB) {
}
else if (phase == END_REFB)
{
printDebugMessage("Finished auto refresh on bank " + to_string(bank.ID()));
if (numberOfPayloadsInSystem[bank] == 0) {
if (numberOfPayloadsInSystem[bank] == 0)
controllerCore->powerDownManager->sleep(bank, sc_time_stamp());
} else {
else
scheduleNextFromScheduler(bank);
}
scheduleNextFromScheduler(bank);
} else if (containsPhase(phase, {END_PREB, END_PRE, END_ACTB, END_ACT})) {
scheduleNextFromScheduler(bank);
}
else if (phase == END_PRE_ALL) {
else if (containsPhase(phase, {END_PREB, END_PRE, END_ACTB, END_ACT}))
{
scheduleNextFromScheduler(bank);
}
else if (phase == END_PRE_ALL)
{
// No need to trigger anything for a END_PRE_ALL. It is followed by a AUTO_REFRESH anyway (in our current
// scheduler implementation)
} else {
}
else
{
string str =
string("DRAM PEQ in controller wrapper was triggered with unsupported phase ")
+ phaseNameToString(phase);
@@ -458,6 +577,8 @@ void Controller::sendToDram(tlm_generic_payload &payload,
{
tlm_phase TPhase = phase;
sc_time TDelay = delay;
if (phase == BEGIN_WR || phase == BEGIN_RD || phase == BEGIN_WRA || phase == BEGIN_RDA)
numberOfTransactionsServed++;
iSocket->nb_transport_fw(payload, TPhase, TDelay);
}
@@ -505,7 +626,7 @@ void Controller::endBandwidthIdleCollector()
{
printDebugMessage("IDLE End");
idleTime += sc_time_stamp() - idleStart +
Configuration::getInstance().memSpec.clk;
Configuration::getInstance().memSpec->clk;
idleState = false;
}

51
DRAMSys/library/src/controller/Controller.h
View File

@@ -35,8 +35,8 @@
* Eder F. Zulian
*/
#ifndef CONTROLLERWRAPPER_H_
#define CONTROLLERWRAPPER_H_
#ifndef CONTROLLER_H
#define CONTROLLER_H
#include <map>
#include <string>
@@ -49,11 +49,11 @@
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include "../common/dramExtension.h"
#include "../common/dramExtensions.h"
#include "../common/DebugManager.h"
#include "../common/protocol.h"
#include "../common/TlmRecorder.h"
#include "../common/Utils.h"
#include "../common/utils.h"
#include "core/configuration/Configuration.h"
#include "core/configuration/MemSpec.h"
#include "Command.h"
@@ -62,14 +62,13 @@
#include "IController.h"
#include "core/powerdown/IPowerDownManager.h"
#include "core/scheduling/ScheduledCommand.h"
#include "core/scheduling/Trigger.h"
#include "core/TimingCalculation.h"
#include "core/timingCalculations.h"
#include "scheduler/Fifo.h"
#include "scheduler/grp.h"
#include "scheduler/Grp.h"
#include "scheduler/FifoStrict.h"
#include "scheduler/Fr_Fcfs.h"
#include "scheduler/Fr_Fcfs_read_priority.h"
#include "scheduler/Fr_Fcfs_grouper.h"
#include "scheduler/FrFcfs.h"
#include "scheduler/FrFcfsRp.h"
#include "scheduler/FrFcfsGrp.h"
#include "scheduler/SMS.h"
#include "scheduler/IScheduler.h"
@@ -78,27 +77,12 @@ using namespace tlm;
DECLARE_EXTENDED_PHASE(PendingRequest);
class Controller: public sc_module, public IController
class Controller : public sc_module, public IController
{
public:
Controller(sc_module_name /*name*/) :
frontendPEQ(this, &Controller::frontendPEQCallback), dramPEQ(this,
&Controller::dramPEQCallback), controllerCorePEQ(this,
&Controller::controllerCorePEQCallback),
debugManager(DebugManager::getInstance())
{
controllerCore = new ControllerCore("core", *this, numberOfPayloadsInSystem);
buildScheduler();
iSocket.register_nb_transport_bw(this, &Controller::nb_transport_bw);
tSocket.register_nb_transport_fw(this, &Controller::nb_transport_fw);
tSocket.register_transport_dbg(this, &Controller::transport_dbg);
}
Controller(sc_module_name);
virtual ~Controller()
{
delete controllerCore;
delete scheduler;
}
virtual ~Controller();
void terminateSimulation();
@@ -112,8 +96,9 @@ public:
virtual void send(Trigger trigger, sc_time time,
tlm_generic_payload &payload) override;
tlm_utils::simple_initiator_socket<Controller> iSocket;
tlm_utils::simple_target_socket<Controller> tSocket;
tlm_utils::simple_initiator_socket<Controller> iSocket;
unsigned int getTotalNumberOfPayloadsInSystem();
void scheduleNextFromScheduler(Bank bank) override;
@@ -155,8 +140,9 @@ protected:
//Scheduler* scheduler;
IScheduler *scheduler;
std::map<Bank, int> numberOfPayloadsInSystem;
std::vector<gp * > refreshCollisionRequets;
std::vector<gp *> refreshCollisionRequets;
tlm::tlm_generic_payload *backpressure = NULL;
std::queue<gp *> responseQueue;
tlm_utils::peq_with_cb_and_phase<Controller> frontendPEQ;
tlm_utils::peq_with_cb_and_phase<Controller> dramPEQ;
@@ -170,7 +156,8 @@ protected:
sc_time idleTime;
sc_time endTime;
sc_time startTime;
int startTimeSet = false;
bool startTimeSet = false;
unsigned long long int numberOfTransactionsServed = 0;
void startBandwidthIdleCollector();
void endBandwidthIdleCollector();
@@ -180,5 +167,5 @@ protected:
static const unsigned int controllerThreadId = INT_MAX;
};
#endif /* CONTROLLERWRAPPER_H_ */
#endif // CONTROLLER_H

16
DRAMSys/library/src/controller/ControllerState.cpp
View File

@@ -37,7 +37,7 @@
#include "ControllerState.h"
#include <algorithm>
#include "core/TimingCalculation.h"
#include "core/timingCalculations.h"
using namespace std;
@@ -51,7 +51,7 @@ const ScheduledCommand ControllerState::getLastCommand(Command command)
{
ScheduledCommand max;
for (unsigned int i = 0; i < config->memSpec.NumberOfBanks; ++i) {
for (unsigned int i = 0; i < config->memSpec->NumberOfBanks; ++i) {
ScheduledCommand current = getLastCommand(command, Bank(i));
if (current.getStart() > max.getStart())
max = current;
@@ -65,7 +65,7 @@ const ScheduledCommand ControllerState::getLastScheduledCommand()
ScheduledCommand lastCommand;
for (Command cmd : getAllCommands()) {
for (Bank bank : Configuration::getInstance().memSpec.getBanks()) {
for (Bank bank : Configuration::getInstance().memSpec->getBanks()) {
ScheduledCommand &current = lastScheduledByCommandAndBank[cmd][bank];
if (current.getStart() > lastCommand.getStart())
lastCommand = current;
@@ -154,17 +154,17 @@ void ControllerState::cleanUp(sc_time time)
vector<ScheduledCommand> tmp;
for (ScheduledCommand &command : lastDataStrobeCommands) {
if (command.getEnd() >= time
|| getDistance(command.getEnd(), time) <= config->memSpec.tDataStrobeHistory())
|| getDistance(command.getEnd(), time) <= config->memSpec->tDataStrobeHistory())
tmp.push_back(command);
}
lastDataStrobeCommands = tmp;
if (time >= config->memSpec.tActHistory())
if (time >= config->memSpec->tActHistory())
lastActivates.erase(lastActivates.begin(),
lastActivates.lower_bound(time - config->memSpec.tActHistory()));
lastActivates.lower_bound(time - config->memSpec->tActHistory()));
if (time >= config->memSpec.tActBHistory())
if (time >= config->memSpec->tActBHistory())
lastActivatesB.erase(lastActivatesB.begin(),
lastActivatesB.lower_bound(time - config->memSpec.tActBHistory()));
lastActivatesB.lower_bound(time - config->memSpec->tActBHistory()));
}
void ControllerState::printDebugMessage(std::string message)

8
DRAMSys/library/src/controller/ControllerState.h
View File

@@ -34,8 +34,8 @@
* Matthias Jung
*/
#ifndef CONTROLLER_STATE_H_
#define CONTROLLER_STATE_H_
#ifndef CONTROLLERSTATE_H
#define CONTROLLERSTATE_H
#include <systemc.h>
#include "RowBufferStates.h"
@@ -49,7 +49,7 @@ class ControllerState
{
public:
ControllerState(std::string ownerName,
Configuration *config) : bus(config->memSpec.clk), ownerName(ownerName),
Configuration *config) : bus(config->memSpec->clk), ownerName(ownerName),
config(config)
{
rowBufferStates = new RowBufferState(ownerName);
@@ -84,5 +84,5 @@ private:
void printDebugMessage(std::string message);
};
#endif /* CONTROLLER_STATE_H_ */
#endif // CONTROLLERSTATE_H

4
DRAMSys/library/src/controller/IController.h
View File

@@ -41,9 +41,9 @@
#include <queue>
#include <systemc.h>
#include "core/scheduling/ScheduledCommand.h"
#include "core/scheduling/Trigger.h"
#include "../common/dramExtension.h"
#include "../common/dramExtensions.h"
enum Trigger {REFTrigger, PDNTrigger};
// Utiliy class to pass around the Controller class to the controller Core and various schedulers, without having to propagate the template defintions
// throughout all classes

6
DRAMSys/library/src/controller/RowBufferStates.cpp
View File

@@ -37,7 +37,7 @@
#include "RowBufferStates.h"
#include "core/ControllerCore.h"
#include "../common/DebugManager.h"
#include "../common/Utils.h"
#include "../common/utils.h"
using namespace std;
@@ -76,7 +76,7 @@ void RowBufferState::closeRowBuffer(Bank bank)
bool RowBufferState::allRowBuffersAreClosed() const
{
for (unsigned int i = 0; i < Configuration::getInstance().memSpec.NumberOfBanks;
for (unsigned int i = 0; i < Configuration::getInstance().memSpec->NumberOfBanks;
++i) {
if (rowBufferIsOpen(Bank(i)))
return false;
@@ -86,7 +86,7 @@ bool RowBufferState::allRowBuffersAreClosed() const
void RowBufferState::closeAllRowBuffers()
{
for (unsigned int i = 0; i < Configuration::getInstance().memSpec.NumberOfBanks;
for (unsigned int i = 0; i < Configuration::getInstance().memSpec->NumberOfBanks;
++i) {
rowsInRowBuffers[Bank(i)] = Row::NO_ROW;
}

8
DRAMSys/library/src/controller/RowBufferStates.h
View File

@@ -34,11 +34,11 @@
* Matthias Jung
*/
#ifndef ROWBUFFERSTATES_H_
#define ROWBUFFERSTATES_H_
#ifndef ROWBUFFERSTATES_H
#define ROWBUFFERSTATES_H
#include <map>
#include "../common/dramExtension.h"
#include "../common/dramExtensions.h"
class RowBufferState
{
@@ -60,5 +60,5 @@ private:
void printDebugMessage(std::string message);
};
#endif /* BANKSTATES_H_ */
#endif // ROWBUFFERSTATES_H

82
DRAMSys/library/src/controller/core/ControllerCore.cpp
View File

@@ -49,9 +49,9 @@
#include "refresh/RefreshManagerBankwise.h"
#include "refresh/RefreshManager.h"
#include "refresh/RGR.h"
#include "../../common/dramExtension.h"
#include "../../common/Utils.h"
#include "TimingCalculation.h"
#include "../../common/dramExtensions.h"
#include "../../common/utils.h"
#include "timingCalculations.h"
#include "powerdown/PowerDownManager.h"
#include "powerdown/PowerDownManagerTimeout.h"
@@ -87,13 +87,16 @@ ControllerCore::ControllerCore(sc_module_name /*name*/,
if (config.RowGranularRef) {
refreshManager = new RGR("RGR", *this);
assert(config.getTrasb() <= config.memSpec.tRAS);
assert(config.getTrasb() >= config.memSpec.tRCD);
assert(config.getTrrdb_L() <= config.memSpec.tRRD_L);
assert(config.getTrrdb_S() <= config.memSpec.tRRD_S);
assert(config.getTrpb() <= config.memSpec.tRP);
assert(config.getTrcb() <= config.memSpec.tRC);
assert(config.getTfawb() <= config.memSpec.tNAW);
// TODO: How to use asserts with new memspec?
/*
assert(config.getTrasb() <= config.memSpec->tRAS);
assert(config.getTrasb() >= config.memSpec->tRCD);
assert(config.getTrrdb_L() <= config.memSpec->tRRD_L);
assert(config.getTrrdb_S() <= config.memSpec->tRRD_S);
assert(config.getTrpb() <= config.memSpec->tRP);
assert(config.getTrcb() <= config.memSpec->tRC);
assert(config.getTfawb() <= config.memSpec->tNAW);
*/
} else {
if (config.BankwiseLogic) {
refreshManager = new RefreshManagerBankwise("refManagerBw", *this);
@@ -138,27 +141,27 @@ ControllerCore::~ControllerCore()
void ControllerCore::triggerRefresh(tlm::tlm_generic_payload &payload)
{
/* Refresh can be disabled for tests purpose */
if (config.ControllerCoreRefDisable == false) {
if (config.ControllerCoreRefDisable == false)
{
sc_time time = sc_time_stamp();
Bank bank = DramExtension::getExtension(payload).getBank();
state->cleanUp(time);
if (!refreshManager->isInvalidated(payload, time)
&& !powerDownManager->isInSelfRefresh(bank)) {
&& !powerDownManager->isInSelfRefresh(bank))
{
printDebugMessage("Triggering refresh on bank " + to_string(bank.ID()));
powerDownManager->wakeUpForRefresh(bank,
time); //expects PDNA and PDNP to exit without delay
bool pdnpToSrefTransition = false;
if (config.PowerDownMode == EPowerDownMode::Staggered) {
pdnpToSrefTransition = state->getLastCommand(Command::PDNPX,
bank).getStart() >= time;
}
if (pdnpToSrefTransition) {
if (config.PowerDownMode == EPowerDownMode::Staggered)
pdnpToSrefTransition = (state->getLastCommand(Command::PDNPX,
bank).getStart() >= time);
if (pdnpToSrefTransition)
powerDownManager->sleep(bank, time);
} else {
else
refreshManager->scheduleRefresh(payload, time);
}
}
}
}
@@ -169,13 +172,17 @@ bool ControllerCore::scheduleRequest(Command command,
sc_time start = clkAlign(sc_time_stamp());
state->cleanUp(start);
ScheduledCommand scheduledCommand = schedule(command, start, payload);
if (config.ControllerCoreRefDisable == true) {
if (config.ControllerCoreRefDisable)
{
state->change(scheduledCommand);
controller.send(scheduledCommand, payload);
return true;
} else {
}
else
{
if (!((command == Command::Precharge || command == Command::Activate)
&& refreshManager->hasCollision(scheduledCommand))) {
&& refreshManager->hasCollision(scheduledCommand)))
{
state->change(scheduledCommand);
controller.send(scheduledCommand, payload);
return true;
@@ -189,17 +196,17 @@ ScheduledCommand ControllerCore::schedule(Command command, sc_time start,
{
ControllerCore::printDebugMessage("Scheduling command " + commandToString(
command) + " on " + DramExtension::getBank(payload).toString());
ICommandChecker &checker = getCommandChecker(command);
sc_time executionTime = getExecutionTime(command, payload);
ScheduledCommand scheduledCommand(command, start, executionTime,
DramExtension::getExtension(payload));
checker.delayToSatisfyConstraints(scheduledCommand);
getCommandChecker(command).delayToSatisfyConstraints(scheduledCommand);
return scheduledCommand;
}
bool ControllerCore::hasPendingRequests()
{
for (Bank bank : getBanks()) {
for (Bank bank : getBanks())
{
if (numberOfPayloads[bank] != 0)
return true;
}
@@ -217,22 +224,31 @@ bool ControllerCore::bankIsBusy(Bank bank)
ScheduledCommand lastScheduledCommand = state->getLastScheduledCommand(bank);
if (lastScheduledCommand.isNoCommand())
{
return false;
else if (lastScheduledCommand.commandIsIn( { Command::Write, Command::Read })) {
}
else if (lastScheduledCommand.commandIsIn({Command::Write, Command::Read}))
{
// Read and writes can overlap, so the bank should not be busy during a rd/wr
return (time < lastScheduledCommand.getStart());
}
else if (lastScheduledCommand.commandIsIn( { Command::WriteA, Command::ReadA, Command::PreB, Command::Precharge, Command::PrechargeAll, Command::ActB, Command::Activate })) {
else if (lastScheduledCommand.commandIsIn({Command::WriteA, Command::ReadA, Command::PreB,
Command::Precharge, Command::PrechargeAll,
Command::ActB, Command::Activate}))
{
return (time < lastScheduledCommand.getEnd());
}
else if (lastScheduledCommand.getCommand() == Command::AutoRefresh) {
else if (lastScheduledCommand.getCommand() == Command::AutoRefresh)
{
return (time < lastScheduledCommand.getEnd());
} else if (lastScheduledCommand.commandIsIn( { Command::SREFX, Command::PDNPX, Command::PDNAX, Command::SREF, Command::PDNP,
Command::PDNA
})) {
}
else if (lastScheduledCommand.commandIsIn({Command::SREFX, Command::PDNPX, Command::PDNAX,
Command::SREF, Command::PDNP, Command::PDNA}))
{
return false;
}
else {
else
{
SC_REPORT_FATAL("Core", "Last command unkown");
return false;
}
@@ -243,7 +259,7 @@ const std::vector<Bank> &ControllerCore::getBanks()
static std::vector<Bank> banks;
if (banks.size() == 0) {
for (unsigned int i = 0; i < config.memSpec.NumberOfBanks; i++) {
for (unsigned int i = 0; i < config.memSpec->NumberOfBanks; i++) {
banks.push_back(Bank(i));
}
}

6
DRAMSys/library/src/controller/core/ControllerCore.h
View File

@@ -34,8 +34,8 @@
* Matthias Jung
*/
#ifndef CONTROLLER_H_
#define CONTROLLER_H_
#ifndef CONTROLLERCORE_H
#define CONTROLLERCORE_H
#include <tlm.h>
#include <map>
@@ -88,5 +88,5 @@ private:
void printDebugMessage(string message);
};
#endif /* CONTROLLER_H_ */
#endif // CONTROLLERCORE_H

2
DRAMSys/library/src/controller/core/Slots.cpp
View File

@@ -35,7 +35,7 @@
*/
#include "Slots.h"
#include "TimingCalculation.h"
#include "timingCalculations.h"
Slots::Slots(sc_time clk) :

8
DRAMSys/library/src/controller/core/Slots.h
View File

@@ -34,13 +34,13 @@
* Matthias Jung
*/
#ifndef SLOTS_H_
#define SLOTS_H_
#ifndef SLOTS_H
#define SLOTS_H
#include <systemc.h>
#include <set>
#include "scheduling/ScheduledCommand.h"
class Slots
{
public:
@@ -60,4 +60,4 @@ private:
};
#endif /* SLOTS_H_ */
#endif // SLOTS_H

28
DRAMSys/library/src/controller/core/configuration/Configuration.cpp
View File

@@ -40,7 +40,7 @@
#include "Configuration.h"
#include "ConfigurationLoader.h"
#include "../../../common/xmlAddressdecoder.h"
#include "../../../common/XmlAddressDecoder.h"
using namespace std;
@@ -349,10 +349,10 @@ void Configuration::setParameters(std::map<std::string, std::string>
std::uint64_t Configuration::getSimMemSizeInBytes()
{
// 1. Get number of banks, rows, columns and data width in bits for one die (or chip)
std::uint64_t banks = memSpec.NumberOfBanks;
std::uint64_t rows = memSpec.NumberOfRows;
std::uint64_t columns = memSpec.NumberOfColumns;
std::uint64_t bitWidth = memSpec.bitWidth;
std::uint64_t banks = memSpec->NumberOfBanks;
std::uint64_t rows = memSpec->NumberOfRows;
std::uint64_t columns = memSpec->NumberOfColumns;
std::uint64_t bitWidth = memSpec->bitWidth;
// 2. Calculate size of one DRAM chip in bits
std::uint64_t chipBitSize = banks * rows * columns * bitWidth;
// 3. Calculate size of one DRAM chip in bytes
@@ -381,7 +381,7 @@ std::uint64_t Configuration::getSimMemSizeInBytes()
// The bus width is given in bits, e.g., 64-bit data bus, 128-bit data bus, etc.
unsigned int Configuration::getDataBusWidth()
{
unsigned int dataBusWidth = memSpec.bitWidth * NumberOfDevicesOnDIMM;
unsigned int dataBusWidth = memSpec->bitWidth * NumberOfDevicesOnDIMM;
assert(dataBusWidth > 0);
return dataBusWidth;
}
@@ -390,7 +390,7 @@ unsigned int Configuration::getDataBusWidth()
unsigned int Configuration::getBytesPerBurst()
{
// First multiply to get the number of bits in a burst, then divide by 8 to get the value in bytes. The order is important. Think on a single x4 device.
unsigned int bytesPerBurst = (memSpec.BurstLength * getDataBusWidth()) / 8;
unsigned int bytesPerBurst = (memSpec->BurstLength * getDataBusWidth()) / 8;
assert(bytesPerBurst > 0);
if (NumberOfDevicesOnDIMM > 1) {
@@ -399,7 +399,7 @@ unsigned int Configuration::getBytesPerBurst()
// or burst element has N bytes. N = 2^(# bits for byte offset)).
unsigned int burstElementSizeInBytes =
AddressDecoder::getInstance().amount["bytes"];
assert(bytesPerBurst == (burstElementSizeInBytes * memSpec.BurstLength));
assert(bytesPerBurst == (burstElementSizeInBytes * memSpec->BurstLength));
}
return bytesPerBurst;
@@ -407,27 +407,27 @@ unsigned int Configuration::getBytesPerBurst()
sc_time Configuration::getTrasb()
{
return trasbclk * memSpec.clk;
return trasbclk * memSpec->clk;
}
sc_time Configuration::getTrrdb_L()
{
return trrdblclk * memSpec.clk;
return trrdblclk * memSpec->clk;
}
sc_time Configuration::getTrrdb_S()
{
return trrdbsclk * memSpec.clk;
return trrdbsclk * memSpec->clk;
}
sc_time Configuration::getTrpb()
{
return trpbclk * memSpec.clk;
return trpbclk * memSpec->clk;
}
sc_time Configuration::getTrcb()
{
return trcbclk * memSpec.clk;
return trcbclk * memSpec->clk;
}
sc_time Configuration::getTfawb()
{
return tfawbclk * memSpec.clk;
return tfawbclk * memSpec->clk;
}
bool Configuration::getRGRBank(unsigned int w)
{

17
DRAMSys/library/src/controller/core/configuration/Configuration.h
View File

@@ -36,15 +36,15 @@
* Felipe S. Prado
*/
#ifndef CONFIGURATION_H_
#define CONFIGURATION_H_
#ifndef CONFIGURATION_H
#define CONFIGURATION_H
#include <systemc.h>
#include <string>
#include <cstdint>
#include "MemSpec.h"
#include "thermalSimConfig.h"
#include "../../../common/Utils.h"
#include "TemperatureSimConfig.h"
#include "../../../common/utils.h"
#include "../../../error/eccbaseclass.h"
@@ -54,7 +54,8 @@ enum class EPowerDownMode {NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF};
enum class ECCControllerMode {Disabled, Hamming};
struct Configuration {
struct Configuration
{
static std::string memspecUri;
static std::string mcconfigUri;
std::string pathToResources;
@@ -71,7 +72,7 @@ struct Configuration {
unsigned int Capsize = 5;
sc_time getPowerDownTimeout()
{
return powerDownTimeoutInClk * memSpec.clk;
return powerDownTimeoutInClk * memSpec->clk;
}
EPowerDownMode PowerDownMode = EPowerDownMode::Staggered;
bool ReadWriteGrouping = false;
@@ -138,7 +139,7 @@ struct Configuration {
unsigned long long int AddressOffset = 0;
// MemSpec (from DRAM-Power XML)
MemSpec memSpec;
MemSpec *memSpec;
void setParameter(std::string name, std::string value);
void setParameters(std::map<std::string, std::string> parameterMap);
@@ -163,5 +164,5 @@ private:
unsigned int powerDownTimeoutInClk = 3;
};
#endif /* CONFIGURATION_H_ */
#endif // CONFIGURATION_H

571
DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp
View File

@@ -32,11 +32,12 @@
* Authors:
* Janik Schlemminger
* Matthias Jung
* Lukas Steiner
*/
#include "ConfigurationLoader.h"
#include "MemSpec.h"
#include "../TimingCalculation.h"
#include "../timingCalculations.h"
using namespace tinyxml2;
using namespace std;
@@ -101,34 +102,6 @@ void ConfigurationLoader::loadConfigFromUri(Configuration &config,
loadConfig(config, e);
}
void ConfigurationLoader::loadMemSpec(Configuration &config, string memspecUri)
{
tinyxml2::XMLDocument doc;
config.memspecUri = memspecUri;
loadXML(memspecUri, doc);
XMLElement *memspec = doc.FirstChildElement("memspec");
loadMemSpec(config, memspec);
}
void ConfigurationLoader::loadMemSpec(Configuration &config,
XMLElement *memspec)
{
config.memSpec.MemoryId = queryStringParameter(memspec, "memoryId");
config.memSpec.MemoryType = queryStringParameter(memspec, "memoryType");
if (config.memSpec.MemoryType == "DDR4") {
loadDDR4(config, memspec);
} else if (config.memSpec.MemoryType == "DDR3") {
loadDDR3(config, memspec);
} else if (config.memSpec.MemoryType == "LPDDR4") {
loadLPDDR4(config, memspec);
} else if (config.memSpec.MemoryType == "WIDEIO_SDR") {
loadWideIO(config, memspec);
} else {
reportFatal("ConfigurationLoader", "Unsupported DRAM type");
}
}
void ConfigurationLoader::loadMCConfig(Configuration &config,
string mcconfigUri)
{
@@ -155,236 +128,278 @@ void ConfigurationLoader::loadMCConfig(Configuration &config,
}
void ConfigurationLoader::loadMemSpec(Configuration &config, string memspecUri)
{
tinyxml2::XMLDocument doc;
config.memspecUri = memspecUri;
loadXML(memspecUri, doc);
XMLElement *memspec = doc.FirstChildElement("memspec");
loadMemSpec(config, memspec);
}
void ConfigurationLoader::loadMemSpec(Configuration &config,
XMLElement *memspec)
{
string memoryType = queryStringParameter(memspec, "memoryType");
if (memoryType == "DDR4") {
Configuration::getInstance().memSpec =
new MemSpecDDR4;
loadDDR4(config, memspec);
} else if (memoryType == "DDR3") {
Configuration::getInstance().memSpec =
new MemSpecDDR3;
loadDDR3(config, memspec);
} else if (memoryType == "LPDDR4") {
Configuration::getInstance().memSpec =
new MemSpecLPDDR4;
loadLPDDR4(config, memspec);
} else if (memoryType == "WIDEIO_SDR") {
Configuration::getInstance().memSpec =
new MemSpecWideIO;
loadWideIO(config, memspec);
} else {
reportFatal("ConfigurationLoader", "Unsupported DRAM type");
}
loadCommons(config, memspec);
}
void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *memspec)
{
config.memSpec->MemoryId = queryStringParameter(memspec, "memoryId");
config.memSpec->MemoryType = queryStringParameter(memspec, "memoryType");
}
void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *memspec)
{
//MemArchitecture
XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec");
config.memSpec.NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks");
config.memSpec.NumberOfBankGroups = 1;
config.memSpec.NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
config.memSpec.BurstLength = queryUIntParameter(architecture, "burstLength");
config.memSpec.nActivate = 4;
config.memSpec.DataRate = queryUIntParameter(architecture, "dataRate");
config.memSpec.NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
config.memSpec.NumberOfColumns = queryUIntParameter(architecture,
config.memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks");
config.memSpec->NumberOfBankGroups = 1;
config.memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
config.memSpec->BurstLength = queryUIntParameter(architecture, "burstLength");
config.memSpec->nActivate = 4;
config.memSpec->DataRate = queryUIntParameter(architecture, "dataRate");
config.memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
config.memSpec->NumberOfColumns = queryUIntParameter(architecture,
"nbrOfColumns");
config.memSpec.bitWidth = queryUIntParameter(architecture, "width");
config.memSpec.DLL = true;
config.memSpec.termination = true;
config.memSpec->bitWidth = queryUIntParameter(architecture, "width");
config.memSpec->DLL = true;
config.memSpec->termination = true;
//MemTimings
XMLElement *timings = memspec->FirstChildElement("memtimingspec");
config.memSpec.clkMHz = queryDoubleParameter(timings, "clkMhz");
config.memSpec.clk = FrequencyToClk(config.memSpec.clkMHz);
sc_time clk = config.memSpec.clk;
config.memSpec.tRP = clk * queryUIntParameter(timings, "RP");
config.memSpec.tRAS = clk * queryUIntParameter(timings, "RAS");
config.memSpec.tRC = clk * queryUIntParameter(timings, "RC");
config.memSpec.tRTP = clk * queryUIntParameter(timings, "RTP");
config.memSpec.tRRD_S = clk * queryUIntParameter(timings, "RRD");
config.memSpec.tRRD_L = clk * queryUIntParameter(timings, "RRD");
config.memSpec.tCCD_S = clk * queryUIntParameter(timings, "CCD");
config.memSpec.tCCD_L = clk * queryUIntParameter(timings, "CCD");
config.memSpec.tRCD = clk * queryUIntParameter(timings, "RCD");
config.memSpec.tNAW = clk * queryUIntParameter(timings, "FAW");
config.memSpec.tRL = clk * queryUIntParameter(timings, "RL");
config.memSpec.tWL = clk * queryUIntParameter(timings, "WL");
config.memSpec.tWR = clk * queryUIntParameter(timings, "WR");
config.memSpec.tWTR_S = clk * queryUIntParameter(timings, "WTR");
config.memSpec.tWTR_L = clk * queryUIntParameter(timings, "WTR");
config.memSpec.tCKESR = clk * queryUIntParameter(timings, "CKESR");
config.memSpec.tCKE = clk * queryUIntParameter(timings, "CKE");
config.memSpec.tXP = clk * queryUIntParameter(timings, "XP");
config.memSpec.tXPDLL = clk * queryUIntParameter(timings, "XPDLL");
config.memSpec.tXSR = clk * queryUIntParameter(timings, "XS");
config.memSpec.tXSRDLL = clk * queryUIntParameter(timings, "XSDLL");
config.memSpec.tAL = clk * queryUIntParameter(timings, "AL");
config.memSpec.tRFC = clk * queryUIntParameter(timings, "RFC");
config.memSpec.tREFI = clk * queryUIntParameter(timings, "REFI");
config.memSpec.tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
config.memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz");
config.memSpec->clk = FrequencyToClk(config.memSpec->clkMHz);
sc_time clk = config.memSpec->clk;
config.memSpec->tRP = clk * queryUIntParameter(timings, "RP");
config.memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
config.memSpec->tRC = clk * queryUIntParameter(timings, "RC");
config.memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD");
config.memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD");
config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD");
config.memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD");
config.memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
config.memSpec->tNAW = clk * queryUIntParameter(timings, "FAW");
config.memSpec->tRL = clk * queryUIntParameter(timings, "RL");
config.memSpec->tWL = clk * queryUIntParameter(timings, "WL");
config.memSpec->tWR = clk * queryUIntParameter(timings, "WR");
config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR");
config.memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR");
config.memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
config.memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
config.memSpec->tXP = clk * queryUIntParameter(timings, "XP");
config.memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL");
config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS");
config.memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XSDLL");
config.memSpec->tAL = clk * queryUIntParameter(timings, "AL");
config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
config.memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
config.memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
config.memSpec.refreshTimings.clear();
for (unsigned int i = 0; i < config.memSpec.NumberOfBanks; ++i) {
config.memSpec.refreshTimings[Bank(i)] = RefreshTiming(config.memSpec.tRFC,
config.memSpec.tREFI);
config.memSpec->refreshTimings.clear();
for (unsigned int i = 0; i < config.memSpec->NumberOfBanks; ++i) {
config.memSpec->refreshTimings[Bank(i)] = RefreshTiming(config.memSpec->tRFC,
config.memSpec->tREFI);
}
// Currents and Volatages: TODO Check if this is correct.
XMLElement *powers = memspec->FirstChildElement("mempowerspec");
config.memSpec.iDD0 = queryDoubleParameter(powers, "idd0");
config.memSpec.iDD02 = 0;
config.memSpec.iDD2P0 = queryDoubleParameter(powers, "idd2p0");
config.memSpec.iDD2P1 = queryDoubleParameter(powers, "idd2p1");
config.memSpec.iDD2N = queryDoubleParameter(powers, "idd2n");
config.memSpec.iDD3P0 = queryDoubleParameter(powers, "idd3p0");
config.memSpec.iDD3P1 = queryDoubleParameter(powers, "idd3p1");
config.memSpec.iDD3N = queryDoubleParameter(powers, "idd3n");
config.memSpec.iDD4R = queryDoubleParameter(powers, "idd4r");
config.memSpec.iDD4W = queryDoubleParameter(powers, "idd4w");
config.memSpec.iDD5 = queryDoubleParameter(powers, "idd5");
config.memSpec.iDD6 = queryDoubleParameter(powers, "idd6");
config.memSpec.iDD62 = 0;
config.memSpec.vDD = queryDoubleParameter(powers, "vdd");
config.memSpec.vDD2 = 0;
config.memSpec->iDD0 = queryDoubleParameter(powers, "idd0");
config.memSpec->iDD02 = 0;
config.memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0");
config.memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1");
config.memSpec->iDD2N = queryDoubleParameter(powers, "idd2n");
config.memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0");
config.memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p1");
config.memSpec->iDD3N = queryDoubleParameter(powers, "idd3n");
config.memSpec->iDD4R = queryDoubleParameter(powers, "idd4r");
config.memSpec->iDD4W = queryDoubleParameter(powers, "idd4w");
config.memSpec->iDD5 = queryDoubleParameter(powers, "idd5");
config.memSpec->iDD6 = queryDoubleParameter(powers, "idd6");
config.memSpec->iDD62 = 0;
config.memSpec->vDD = queryDoubleParameter(powers, "vdd");
config.memSpec->vDD2 = 0;
}
void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *memspec)
{
//MemArchitecture
XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec");
config.memSpec.NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks");
config.memSpec.NumberOfBankGroups = queryUIntParameter(architecture,
config.memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks");
config.memSpec->NumberOfBankGroups = queryUIntParameter(architecture,
"nbrOfBankGroups");
config.memSpec.NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
config.memSpec.BurstLength = queryUIntParameter(architecture, "burstLength");
config.memSpec.nActivate = 4;
config.memSpec.DataRate = queryUIntParameter(architecture, "dataRate");
config.memSpec.NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
config.memSpec.NumberOfColumns = queryUIntParameter(architecture,
config.memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
config.memSpec->BurstLength = queryUIntParameter(architecture, "burstLength");
config.memSpec->nActivate = 4;
config.memSpec->DataRate = queryUIntParameter(architecture, "dataRate");
config.memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
config.memSpec->NumberOfColumns = queryUIntParameter(architecture,
"nbrOfColumns");
config.memSpec.bitWidth = queryUIntParameter(architecture, "width");
config.memSpec.DLL = true;
config.memSpec.termination = true;
config.memSpec->bitWidth = queryUIntParameter(architecture, "width");
config.memSpec->DLL = true;
config.memSpec->termination = true;
//MemTimings
XMLElement *timings = memspec->FirstChildElement("memtimingspec");
config.memSpec.clkMHz = queryDoubleParameter(timings, "clkMhz");
config.memSpec.clk = FrequencyToClk(config.memSpec.clkMHz);
sc_time clk = config.memSpec.clk;
config.memSpec.tRP = clk * queryUIntParameter(timings, "RP");
config.memSpec.tRAS = clk * queryUIntParameter(timings, "RAS");
config.memSpec.tRC = clk * queryUIntParameter(timings, "RC");
config.memSpec.tRTP = clk * queryUIntParameter(timings, "RTP");
config.memSpec.tRRD_S = clk * queryUIntParameter(timings, "RRD_S");
config.memSpec.tRRD_L = clk * queryUIntParameter(timings, "RRD_L");
config.memSpec.tCCD_S = clk * queryUIntParameter(timings, "CCD_S");
config.memSpec.tCCD_L = clk * queryUIntParameter(timings, "CCD_L");
config.memSpec.tRCD = clk * queryUIntParameter(timings, "RCD");
config.memSpec.tNAW = clk * queryUIntParameter(timings, "FAW");
config.memSpec.tRL = clk * queryUIntParameter(timings, "RL");
config.memSpec.tWL = clk * queryUIntParameter(timings, "WL");
config.memSpec.tWR = clk * queryUIntParameter(timings, "WR");
config.memSpec.tWTR_S = clk * queryUIntParameter(timings, "WTR_S");
config.memSpec.tWTR_L = clk * queryUIntParameter(timings, "WTR_L");
config.memSpec.tCKESR = clk * queryUIntParameter(timings, "CKESR");
config.memSpec.tCKE = clk * queryUIntParameter(timings, "CKE");
config.memSpec.tXP = clk * queryUIntParameter(timings, "XP");
config.memSpec.tXPDLL = clk * queryUIntParameter(timings, "XPDLL");
config.memSpec.tXSR = clk * queryUIntParameter(timings, "XS");
config.memSpec.tXSRDLL = clk * queryUIntParameter(timings, "XSDLL");
config.memSpec.tAL = clk * queryUIntParameter(timings, "AL");
config.memSpec.tRFC = clk * queryUIntParameter(timings, "RFC");
config.memSpec.tRFC2 = clk * queryUIntParameter(timings, "RFC2");
config.memSpec.tRFC4 = clk * queryUIntParameter(timings, "RFC4");
config.memSpec.tREFI = clk * queryUIntParameter(timings, "REFI");
config.memSpec.tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
config.memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz");
config.memSpec->clk = FrequencyToClk(config.memSpec->clkMHz);
sc_time clk = config.memSpec->clk;
config.memSpec->tRP = clk * queryUIntParameter(timings, "RP");
config.memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
config.memSpec->tRC = clk * queryUIntParameter(timings, "RC");
config.memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD_S");
config.memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD_L");
config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD_S");
config.memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD_L");
config.memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
config.memSpec->tNAW = clk * queryUIntParameter(timings, "FAW");
config.memSpec->tRL = clk * queryUIntParameter(timings, "RL");
config.memSpec->tWL = clk * queryUIntParameter(timings, "WL");
config.memSpec->tWR = clk * queryUIntParameter(timings, "WR");
config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR_S");
config.memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR_L");
config.memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
config.memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
config.memSpec->tXP = clk * queryUIntParameter(timings, "XP");
config.memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL");
config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS");
config.memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XSDLL");
config.memSpec->tAL = clk * queryUIntParameter(timings, "AL");
config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
config.memSpec->tRFC2 = clk * queryUIntParameter(timings, "RFC2");
config.memSpec->tRFC4 = clk * queryUIntParameter(timings, "RFC4");
config.memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
config.memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
config.memSpec.refreshTimings.clear();
for (unsigned int i = 0; i < config.memSpec.NumberOfBanks; ++i) {
config.memSpec.refreshTimings[Bank(i)] = RefreshTiming(config.memSpec.tRFC,
config.memSpec.tRFC2,
config.memSpec.tRFC4,
config.memSpec.tREFI);
config.memSpec->refreshTimings.clear();
for (unsigned int i = 0; i < config.memSpec->NumberOfBanks; ++i) {
config.memSpec->refreshTimings[Bank(i)] = RefreshTiming(config.memSpec->tRFC,
config.memSpec->tRFC2,
config.memSpec->tRFC4,
config.memSpec->tREFI);
}
// Currents and Volatages:
XMLElement *powers = memspec->FirstChildElement("mempowerspec");
config.memSpec.iDD0 = queryDoubleParameter(powers, "idd0");
config.memSpec.iDD02 = queryDoubleParameter(powers, "idd02");
config.memSpec.iDD2P0 = queryDoubleParameter(powers, "idd2p0");
config.memSpec.iDD2P1 = queryDoubleParameter(powers, "idd2p1");
config.memSpec.iDD2N = queryDoubleParameter(powers, "idd2n");
config.memSpec.iDD3P0 = queryDoubleParameter(powers, "idd3p0");
config.memSpec.iDD3P1 = queryDoubleParameter(powers, "idd3p1");
config.memSpec.iDD3N = queryDoubleParameter(powers, "idd3n");
config.memSpec.iDD4R = queryDoubleParameter(powers, "idd4r");
config.memSpec.iDD4W = queryDoubleParameter(powers, "idd4w");
config.memSpec.iDD5 = queryDoubleParameter(powers, "idd5");
config.memSpec.iDD6 = queryDoubleParameter(powers, "idd6");
config.memSpec.iDD62 = queryDoubleParameter(powers, "idd62");
config.memSpec.vDD = queryDoubleParameter(powers, "vdd");
config.memSpec.vDD2 = queryDoubleParameter(powers, "vdd2");
config.memSpec->iDD0 = queryDoubleParameter(powers, "idd0");
config.memSpec->iDD02 = queryDoubleParameter(powers, "idd02");
config.memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0");
config.memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1");
config.memSpec->iDD2N = queryDoubleParameter(powers, "idd2n");
config.memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0");
config.memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p1");
config.memSpec->iDD3N = queryDoubleParameter(powers, "idd3n");
config.memSpec->iDD4R = queryDoubleParameter(powers, "idd4r");
config.memSpec->iDD4W = queryDoubleParameter(powers, "idd4w");
config.memSpec->iDD5 = queryDoubleParameter(powers, "idd5");
config.memSpec->iDD6 = queryDoubleParameter(powers, "idd6");
config.memSpec->iDD62 = queryDoubleParameter(powers, "idd62");
config.memSpec->vDD = queryDoubleParameter(powers, "vdd");
config.memSpec->vDD2 = queryDoubleParameter(powers, "vdd2");
}
// TODO: fix this for LPDDR4
// TODO: change timings for LPDDR4
void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *memspec)
{
//MemArchitecture:
XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec");
config.memSpec.NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks");
config.memSpec.NumberOfBankGroups = 1;
config.memSpec.NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
config.memSpec.BurstLength = queryUIntParameter(architecture, "burstLength");
config.memSpec.nActivate = 4;
config.memSpec.DataRate = queryUIntParameter(architecture, "dataRate");
config.memSpec.NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
config.memSpec.NumberOfColumns = queryUIntParameter(architecture,
config.memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks");
config.memSpec->NumberOfBankGroups = 1;
config.memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
config.memSpec->BurstLength = queryUIntParameter(architecture, "burstLength");
config.memSpec->nActivate = 4;
config.memSpec->DataRate = queryUIntParameter(architecture, "dataRate");
config.memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
config.memSpec->NumberOfColumns = queryUIntParameter(architecture,
"nbrOfColumns");
config.memSpec.bitWidth = queryUIntParameter(architecture, "width");
config.memSpec.DLL = false; // TODO: Correct?
config.memSpec.termination = true; // TODO: Correct?
config.memSpec->bitWidth = queryUIntParameter(architecture, "width");
config.memSpec->DLL = false; // TODO: Correct?
config.memSpec->termination = true; // TODO: Correct?
//MemTimings
XMLElement *timings = memspec->FirstChildElement("memtimingspec");
config.memSpec.clkMHz = queryDoubleParameter(timings, "clkMhz");
config.memSpec.clk = FrequencyToClk(config.memSpec.clkMHz);
sc_time clk = config.memSpec.clk;
config.memSpec.tRP = clk * queryUIntParameter(timings, "RPPB");
config.memSpec.tRPAB = clk * queryUIntParameter(timings, "RPAB");
config.memSpec.tRAS = clk * queryUIntParameter(timings, "RAS");
config.memSpec.tRC = clk * queryUIntParameter(timings, "RC");
config.memSpec.tRTP = clk * queryUIntParameter(timings, "RTP");
config.memSpec.tRRD_S = clk * queryUIntParameter(timings, "RRD");
config.memSpec.tRRD_L = clk * queryUIntParameter(timings, "RRD");
config.memSpec.tCCD_S = clk * queryUIntParameter(timings, "CCD");
config.memSpec.tCCD_L = clk * queryUIntParameter(timings, "CCD");
config.memSpec.tRCD = clk * queryUIntParameter(timings, "RCD");
config.memSpec.tNAW = clk * queryUIntParameter(timings, "FAW");
config.memSpec.tRL = clk * queryUIntParameter(timings, "RL");
config.memSpec.tWL = clk * queryUIntParameter(timings, "WL");
config.memSpec.tWR = clk * queryUIntParameter(timings, "WR");
config.memSpec.tWTR_S = clk * queryUIntParameter(timings, "WTR");
config.memSpec.tWTR_L = clk * queryUIntParameter(timings, "WTR");
config.memSpec.tCKESR = clk * queryUIntParameter(timings, "CKESR");
config.memSpec.tCKE = clk * queryUIntParameter(timings, "CKE");
config.memSpec.tXP = clk * queryUIntParameter(timings, "XP");
config.memSpec.tXPDLL = clk * queryUIntParameter(timings, "XP");
config.memSpec.tXSR = clk * queryUIntParameter(timings, "XS");
config.memSpec.tXSRDLL = clk * queryUIntParameter(timings, "XS");
config.memSpec.tAL = clk * queryUIntParameter(timings, "AL");
config.memSpec.tRFC = clk * queryUIntParameter(timings, "RFCAB");
// TODO: config.memSpec.tRFCPB = clk * queryUIntParameter(timings, "RFCPB");
config.memSpec.tREFI = clk * queryUIntParameter(timings, "REFIAB");
// TODO: config.memSpec.tREFIPB = clk * queryUIntParameter(timings, "RFCPB");
config.memSpec.tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
config.memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz");
config.memSpec->clk = FrequencyToClk(config.memSpec->clkMHz);
sc_time clk = config.memSpec->clk;
config.memSpec->tRP = clk * queryUIntParameter(timings, "RPPB");
config.memSpec->tRPAB = clk * queryUIntParameter(timings, "RPAB");
config.memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
config.memSpec->tRC = clk * queryUIntParameter(timings, "RC");
config.memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD");
config.memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD");
config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD");
config.memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD");
config.memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
config.memSpec->tNAW = clk * queryUIntParameter(timings, "FAW");
config.memSpec->tRL = clk * queryUIntParameter(timings, "RL");
config.memSpec->tWL = clk * queryUIntParameter(timings, "WL");
config.memSpec->tWR = clk * queryUIntParameter(timings, "WR");
config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR");
config.memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR");
config.memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
config.memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
config.memSpec->tXP = clk * queryUIntParameter(timings, "XP");
config.memSpec->tXPDLL = clk * queryUIntParameter(timings, "XP");
config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS");
config.memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XS");
config.memSpec->tAL = clk * queryUIntParameter(timings, "AL");
config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFCAB");
// TODO: config.memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB");
config.memSpec->tREFI = clk * queryUIntParameter(timings, "REFIAB");
// TODO: config.memSpec->tREFIPB = clk * queryUIntParameter(timings, "RFCPB");
config.memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
config.memSpec.refreshTimings.clear();
for (unsigned int i = 0; i < config.memSpec.NumberOfBanks; ++i) {
config.memSpec.refreshTimings[Bank(i)] = RefreshTiming(config.memSpec.tRFC,
config.memSpec.tREFI);
config.memSpec->refreshTimings.clear();
for (unsigned int i = 0; i < config.memSpec->NumberOfBanks; ++i) {
config.memSpec->refreshTimings[Bank(i)] = RefreshTiming(config.memSpec->tRFC,
config.memSpec->tREFI);
}
// Currents and Volatages:
XMLElement *powers = memspec->FirstChildElement("mempowerspec");
config.memSpec.iDD0 = queryDoubleParameter(powers, "idd0");
config.memSpec.iDD02 = queryDoubleParameter(powers, "idd02");
config.memSpec.iDD2P0 = queryDoubleParameter(powers, "idd2p");
config.memSpec.iDD2P1 = queryDoubleParameter(powers, "idd2p2");
config.memSpec.iDD2N = queryDoubleParameter(powers, "idd2n");
config.memSpec.iDD3P0 = queryDoubleParameter(powers, "idd3p");
config.memSpec.iDD3P1 = queryDoubleParameter(powers, "idd3p2");
config.memSpec.iDD3N = queryDoubleParameter(powers, "idd3n");
config.memSpec.iDD4R = queryDoubleParameter(powers, "idd4r");
config.memSpec.iDD4W = queryDoubleParameter(powers, "idd4w");
config.memSpec.iDD5 = queryDoubleParameter(powers, "idd5");
config.memSpec.iDD6 = queryDoubleParameter(powers, "idd6");
config.memSpec.iDD62 = queryDoubleParameter(powers, "idd62");
config.memSpec.vDD = queryDoubleParameter(powers, "vdd");
config.memSpec.vDD2 = queryDoubleParameter(powers, "vdd2");
config.memSpec->iDD0 = queryDoubleParameter(powers, "idd0");
config.memSpec->iDD02 = queryDoubleParameter(powers, "idd02");
config.memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p");
config.memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p2");
config.memSpec->iDD2N = queryDoubleParameter(powers, "idd2n");
config.memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p");
config.memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p2");
config.memSpec->iDD3N = queryDoubleParameter(powers, "idd3n");
config.memSpec->iDD4R = queryDoubleParameter(powers, "idd4r");
config.memSpec->iDD4W = queryDoubleParameter(powers, "idd4w");
config.memSpec->iDD5 = queryDoubleParameter(powers, "idd5");
config.memSpec->iDD6 = queryDoubleParameter(powers, "idd6");
config.memSpec->iDD62 = queryDoubleParameter(powers, "idd62");
config.memSpec->vDD = queryDoubleParameter(powers, "vdd");
config.memSpec->vDD2 = queryDoubleParameter(powers, "vdd2");
}
void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec)
@@ -392,79 +407,79 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec)
//MemSpecification
XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec");
config.memSpec.NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks");
config.memSpec.NumberOfBankGroups = 1;
config.memSpec.NumberOfRanks = 1;
config.memSpec.BurstLength = queryUIntParameter(architecture, "burstLength");
config.memSpec.nActivate = 2;
config.memSpec.DataRate = queryUIntParameter(architecture, "dataRate");
config.memSpec.NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
config.memSpec.NumberOfColumns = queryUIntParameter(architecture,
config.memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks");
config.memSpec->NumberOfBankGroups = 1;
config.memSpec->NumberOfRanks = 1;
config.memSpec->BurstLength = queryUIntParameter(architecture, "burstLength");
config.memSpec->nActivate = 2;
config.memSpec->DataRate = queryUIntParameter(architecture, "dataRate");
config.memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
config.memSpec->NumberOfColumns = queryUIntParameter(architecture,
"nbrOfColumns");
config.memSpec.bitWidth = queryUIntParameter(architecture, "width");
config.memSpec.DLL = false;
config.memSpec.termination = false;
config.memSpec->bitWidth = queryUIntParameter(architecture, "width");
config.memSpec->DLL = false;
config.memSpec->termination = false;
//MemTimings
XMLElement *timings = memspec->FirstChildElement("memtimingspec");
config.memSpec.clkMHz = queryDoubleParameter(timings, "clkMhz");
config.memSpec.clk = FrequencyToClk(config.memSpec.clkMHz);
sc_time clk = config.memSpec.clk;
config.memSpec.tRP = clk * queryUIntParameter(timings, "RP");
config.memSpec.tRAS = clk * queryUIntParameter(timings, "RAS");
config.memSpec.tRC = clk * queryUIntParameter(timings, "RC");
config.memSpec.tRRD_S = clk * queryUIntParameter(timings, "RRD");
config.memSpec.tRRD_L = config.memSpec.tRRD_S;
config.memSpec.tCCD_S = clk * queryUIntParameter(timings, "CCD");
config.memSpec.tCCD_L = config.memSpec.tCCD_S;
config.memSpec.tRCD = clk * queryUIntParameter(timings, "RCD");
config.memSpec.tNAW = clk * queryUIntParameter(timings, "TAW");
config.memSpec.tRL = clk * queryUIntParameter(timings, "RL");
config.memSpec.tWL = clk * queryUIntParameter(timings, "WL");
config.memSpec.tWR = clk * queryUIntParameter(timings, "WR");
config.memSpec.tWTR_S = clk * queryUIntParameter(timings, "WTR");
config.memSpec.tWTR_L = config.memSpec.tWTR_S;
config.memSpec.tRTP = clk * queryUIntParameter(timings, "RTP");
config.memSpec.tCKESR = clk * queryUIntParameter(timings, "CKESR");
config.memSpec.tCKE = clk * queryUIntParameter(timings, "CKE");
config.memSpec.tXP = clk * queryUIntParameter(timings, "XP");
config.memSpec.tXPDLL = config.memSpec.tXP;
config.memSpec.tXSR = clk * queryUIntParameter(timings, "XS");
config.memSpec.tXSRDLL = config.memSpec.tXSR;
config.memSpec.tAL = clk * queryUIntParameter(timings, "AL");
config.memSpec.tRFC = clk * queryUIntParameter(timings, "RFC");
config.memSpec.tREFI = clk * queryUIntParameter(timings, "REFI");
config.memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz");
config.memSpec->clk = FrequencyToClk(config.memSpec->clkMHz);
sc_time clk = config.memSpec->clk;
config.memSpec->tRP = clk * queryUIntParameter(timings, "RP");
config.memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
config.memSpec->tRC = clk * queryUIntParameter(timings, "RC");
config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD");
config.memSpec->tRRD_L = config.memSpec->tRRD_S;
config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD");
config.memSpec->tCCD_L = config.memSpec->tCCD_S;
config.memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
config.memSpec->tNAW = clk * queryUIntParameter(timings, "TAW");
config.memSpec->tRL = clk * queryUIntParameter(timings, "RL");
config.memSpec->tWL = clk * queryUIntParameter(timings, "WL");
config.memSpec->tWR = clk * queryUIntParameter(timings, "WR");
config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR");
config.memSpec->tWTR_L = config.memSpec->tWTR_S;
config.memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
config.memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
config.memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
config.memSpec->tXP = clk * queryUIntParameter(timings, "XP");
config.memSpec->tXPDLL = config.memSpec->tXP;
config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS");
config.memSpec->tXSRDLL = config.memSpec->tXSR;
config.memSpec->tAL = clk * queryUIntParameter(timings, "AL");
config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
config.memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
config.memSpec.refreshTimings.clear();
for (unsigned int i = 0; i < config.memSpec.NumberOfBanks; ++i) {
config.memSpec.refreshTimings[Bank(i)] = RefreshTiming(config.memSpec.tRFC,
config.memSpec.tREFI);
config.memSpec->refreshTimings.clear();
for (unsigned int i = 0; i < config.memSpec->NumberOfBanks; ++i) {
config.memSpec->refreshTimings[Bank(i)] = RefreshTiming(config.memSpec->tRFC,
config.memSpec->tREFI);
}
// Currents and Volatages:
XMLElement *powers = memspec->FirstChildElement("mempowerspec");
config.memSpec.iDD0 = queryDoubleParameter(powers, "idd0");
config.memSpec.iDD02 = queryDoubleParameter(powers, "idd02");
config.memSpec.iDD2P0 = queryDoubleParameter(powers, "idd2p0");
config.memSpec.iDD2P02 = queryDoubleParameter(powers, "idd2p02");
config.memSpec.iDD2P1 = queryDoubleParameter(powers, "idd2p1");
config.memSpec.iDD2P12 = queryDoubleParameter(powers, "idd2p12");
config.memSpec.iDD2N = queryDoubleParameter(powers, "idd2n");
config.memSpec.iDD2N2 = queryDoubleParameter(powers, "idd2n2");
config.memSpec.iDD3P0 = queryDoubleParameter(powers, "idd3p0");
config.memSpec.iDD3P02 = queryDoubleParameter(powers, "idd3p02");
config.memSpec.iDD3P1 = queryDoubleParameter(powers, "idd3p1");
config.memSpec.iDD3P12 = queryDoubleParameter(powers, "idd3p12");
config.memSpec.iDD3N = queryDoubleParameter(powers, "idd3n");
config.memSpec.iDD3N2 = queryDoubleParameter(powers, "idd3n2");
config.memSpec.iDD4R = queryDoubleParameter(powers, "idd4r");
config.memSpec.iDD4R2 = queryDoubleParameter(powers, "idd4r2");
config.memSpec.iDD4W = queryDoubleParameter(powers, "idd4w");
config.memSpec.iDD4W2 = queryDoubleParameter(powers, "idd4w2");
config.memSpec.iDD5 = queryDoubleParameter(powers, "idd5");
config.memSpec.iDD52 = queryDoubleParameter(powers, "idd52");
config.memSpec.iDD6 = queryDoubleParameter(powers, "idd6");
config.memSpec.iDD62 = queryDoubleParameter(powers, "idd62");
config.memSpec.vDD = queryDoubleParameter(powers, "vdd");
config.memSpec.vDD2 = queryDoubleParameter(powers, "vdd2");
config.memSpec->iDD0 = queryDoubleParameter(powers, "idd0");
config.memSpec->iDD02 = queryDoubleParameter(powers, "idd02");
config.memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0");
config.memSpec->iDD2P02 = queryDoubleParameter(powers, "idd2p02");
config.memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1");
config.memSpec->iDD2P12 = queryDoubleParameter(powers, "idd2p12");
config.memSpec->iDD2N = queryDoubleParameter(powers, "idd2n");
config.memSpec->iDD2N2 = queryDoubleParameter(powers, "idd2n2");
config.memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0");
config.memSpec->iDD3P02 = queryDoubleParameter(powers, "idd3p02");
config.memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p1");
config.memSpec->iDD3P12 = queryDoubleParameter(powers, "idd3p12");
config.memSpec->iDD3N = queryDoubleParameter(powers, "idd3n");
config.memSpec->iDD3N2 = queryDoubleParameter(powers, "idd3n2");
config.memSpec->iDD4R = queryDoubleParameter(powers, "idd4r");
config.memSpec->iDD4R2 = queryDoubleParameter(powers, "idd4r2");
config.memSpec->iDD4W = queryDoubleParameter(powers, "idd4w");
config.memSpec->iDD4W2 = queryDoubleParameter(powers, "idd4w2");
config.memSpec->iDD5 = queryDoubleParameter(powers, "idd5");
config.memSpec->iDD52 = queryDoubleParameter(powers, "idd52");
config.memSpec->iDD6 = queryDoubleParameter(powers, "idd6");
config.memSpec->iDD62 = queryDoubleParameter(powers, "idd62");
config.memSpec->vDD = queryDoubleParameter(powers, "vdd");
config.memSpec->vDD2 = queryDoubleParameter(powers, "vdd2");
}

14
DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.h
View File

@@ -32,14 +32,15 @@
* Authors:
* Janik Schlemminger
* Matthias Jung
* Lukas Steiner
*/
#ifndef CONFIGURATIONLOADER_H_
#define CONFIGURATIONLOADER_H_
#ifndef CONFIGURATIONLOADER_H
#define CONFIGURATIONLOADER_H
#include <string>
#include "../../../common/third_party/tinyxml2/tinyxml2.h"
#include "../../../common/Utils.h"
#include "../../../common/utils.h"
#include "Configuration.h"
class ConfigurationLoader
@@ -65,8 +66,9 @@ private:
static void loadConfig(Configuration &config, tinyxml2::XMLElement *configNode);
static void loadConfigFromUri(Configuration &config, std::string uri,
std::string first_element);
//specific loader
// Loads common config of DRAMs
static void loadCommons(Configuration &config, tinyxml2::XMLElement *memspec);
// Load specific config
static void loadDDR3(Configuration &config, tinyxml2::XMLElement *memspec);
static void loadDDR4(Configuration &config, tinyxml2::XMLElement *memspec);
static void loadLPDDR4(Configuration &config, tinyxml2::XMLElement *memspec);
@@ -74,4 +76,4 @@ private:
};
#endif /* CONFIGURATIONLOADER_H_ */
#endif // CONFIGURATIONLOADER_H

69
DRAMSys/library/src/controller/core/configuration/MemSpec.h
View File

@@ -32,17 +32,18 @@
* Authors:
* Janik Schlemminger
* Matthias Jung
* Lukas Steiner
*/
#ifndef MemSpec_H_
#define MemSpec_H_
#ifndef MEMSPEC_H
#define MEMSPEC_H
#include <systemc.h>
#include <map>
#include "../../../common/dramExtension.h"
#include "../../../common/dramExtensions.h"
struct RefreshTiming {
struct RefreshTiming
{
RefreshTiming() {}
RefreshTiming(sc_time tRFC, sc_time tREFI) : tRFC(tRFC), tRFC2(SC_ZERO_TIME),
tRFC4(SC_ZERO_TIME), tREFI(tREFI) {}
@@ -54,12 +55,8 @@ struct RefreshTiming {
sc_time tREFI;
};
struct MemSpec {
MemSpec()
{
//default DDR4
}
struct MemSpec
{
const std::vector<Bank> &getBanks() const
{
static std::vector<Bank> banks;
@@ -90,24 +87,31 @@ struct MemSpec {
// Memspec Variables:
double clkMHz;
sc_time clk;
sc_time tRP; //precharge-time (pre -> act same bank)
sc_time tRP; //precharge-time (pre -> act same bank
sc_time tRTP; //Read to precharge
sc_time tRCD; //act -> read/write
sc_time tRL; //read latency (read command start to data strobe)
sc_time tWL; //write latency
sc_time tWR; //write recovery (write to precharge)
sc_time tCKESR; //min time in sref
sc_time tCKE; //min time in pdna or pdnp
sc_time tRFC; //min ref->act delay 1X mode
sc_time tRFC2; //min ref->act delay 2X mode
sc_time tRFC4; //min ref->act delay 4X mode
sc_time tREFI; //auto refresh must be issued at an average periodic interval tREFI
// TODO: move to specific memspecs
sc_time tRPAB; //precharge-all time only for LPDDR4
sc_time tRAS; //active-time (act -> pre same bank)
sc_time tRC; //RAS-cycle-time (min time bw 2 succesive ACT to same bank)
sc_time tCCD_S; //max(bl, tCCD) is relevant for rd->rd
sc_time tCCD_L;
sc_time tRTP; //Read to precharge
sc_time tRRD_S; //min time bw 2 succesive ACT to different banks (different bank group)
sc_time tRRD_L; //.. (same bank group)
sc_time tRCD; //act -> read/write
sc_time tNAW; //n activate window
sc_time tRL; //read latency (read command start to data strobe)
sc_time tWL; //write latency
sc_time tWR; //write recovery (write to precharge)
sc_time tWTR_S; //write to read (different bank group)
sc_time tWTR_L; //.. (same bank group)
sc_time tCKESR; //min time in sref
sc_time tCKE; //min time in pdna or pdnp
sc_time tXP; //min delay to row access command after pdnpx pdnax
sc_time tXPDLL; //min delay to row access command after pdnpx pdnax for dll commands
sc_time tXSR; //min delay to row access command after srefx
@@ -115,11 +119,6 @@ struct MemSpec {
sc_time tAL; //additive delay (delayed execution in dram)
sc_time tDQSCK;
sc_time tRFC; //min ref->act delay 1X mode
sc_time tRFC2; //min ref->act delay 2X mode
sc_time tRFC4; //min ref->act delay 4X mode
sc_time tREFI; //auto refresh must be issued at an average periodic interval tREFI
// Currents and Voltages:
double iDD0;
double iDD02;
@@ -165,5 +164,25 @@ struct MemSpec {
}
};
#endif /* MemSpec_H_ */
struct MemSpecDDR3 : public MemSpec
{
};
struct MemSpecDDR4 : public MemSpec
{
};
struct MemSpecWideIO : public MemSpec
{
};
struct MemSpecLPDDR4 : public MemSpec
{
};
#endif // MEMSPEC_H

12
DRAMSys/library/src/controller/core/configuration/thermalSimConfig.h → DRAMSys/library/src/controller/core/configuration/TemperatureSimConfig.h
View File

@@ -34,8 +34,8 @@
* Matthias Jung
*/
#ifndef THERMALSIM_CONFIG_H
#define THERMALSIM_CONFIG_H
#ifndef TEMPERATURESIMCONFIG_H
#define TEMPERATURESIMCONFIG_H
#include <systemc.h>
#include <iostream>
@@ -43,10 +43,10 @@
#include "../../../common/DebugManager.h"
#include "../../../common/third_party/tinyxml2/tinyxml2.h"
#include "../../../common/Utils.h"
struct TemperatureSimConfig {
#include "../../../common/utils.h"
struct TemperatureSimConfig
{
// Temperature Scale
std::string TemperatureScale;
std::string pathToResources;
@@ -132,5 +132,5 @@ struct TemperatureSimConfig {
}
};
#endif /* THERMALSIM_CONFIG_H */
#endif // TEMPERATURESIMCONFIG_H

8
DRAMSys/library/src/controller/core/powerdown/IPowerDownManager.h
View File

@@ -34,11 +34,11 @@
* Matthias Jung
*/
#ifndef IPOWERDOWNMANAGER_H_
#define IPOWERDOWNMANAGER_H_
#ifndef IPOWERDOWNMANAGER_H
#define IPOWERDOWNMANAGER_H
#include <systemc.h>
#include "../../../common/dramExtension.h"
#include "../../../common/dramExtensions.h"
#include "../../Command.h"
@@ -126,4 +126,4 @@ inline std::string powerDownStateToString(PowerDownState powerDownState)
}
#endif /* IPOWERDOWNMANAGER_H_ */
#endif // IPOWERDOWNMANAGER_H

4
DRAMSys/library/src/controller/core/powerdown/NoPowerDown.h
View File

@@ -40,12 +40,12 @@
#include "PowerDownManager.h"
#include <systemc.h>
#include "../../../common/dramExtension.h"
#include "../../../common/dramExtensions.h"
#include "../scheduling/ScheduledCommand.h"
class NoPowerDown: public IPowerDownManager
class NoPowerDown : public IPowerDownManager
{
public:
NoPowerDown() {}

4
DRAMSys/library/src/controller/core/powerdown/PowerDownManager.cpp
View File

@@ -39,10 +39,10 @@
#include <string>
#include "PowerDownManager.h"
#include "../ControllerCore.h"
#include "../TimingCalculation.h"
#include "../timingCalculations.h"
#include "../../../common/DebugManager.h"
#include <algorithm>
#include "../../../common/Utils.h"
#include "../../../common/utils.h"
using namespace tlm;
using namespace std;

6
DRAMSys/library/src/controller/core/powerdown/PowerDownManager.h
View File

@@ -34,8 +34,8 @@
* Matthias Jung
*/
#ifndef POWERDOWNMANAGER_H_
#define POWERDOWNMANAGER_H_
#ifndef POWERDOWNMANAGER_H
#define POWERDOWNMANAGER_H
#include "PowerDownManagerBankwise.h"
@@ -68,4 +68,4 @@ protected:
};
#endif /* POWERDOWNMANAGER_H_ */
#endif // POWERDOWNMANAGER_H

4
DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.cpp
View File

@@ -36,9 +36,9 @@
#include "PowerDownManager.h"
#include "../ControllerCore.h"
#include "../../../common/Utils.h"
#include "../../../common/utils.h"
#include "../../../common/DebugManager.h"
#include "../TimingCalculation.h"
#include "../timingCalculations.h"
using namespace tlm;

8
DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.h
View File

@@ -34,15 +34,15 @@
* Matthias Jung
*/
#ifndef POWERDOWNMANAGERBANKWISE_H_
#define POWERDOWNMANAGERBANKWISE_H_
#ifndef POWERDOWNMANAGERBANKWISE_H
#define POWERDOWNMANAGERBANKWISE_H
#include <systemc.h>
#include <tlm.h>
#include <map>
#include <string>
#include "../../Command.h"
#include "../../../common/dramExtension.h"
#include "../../../common/dramExtensions.h"
#include "../scheduling/ScheduledCommand.h"
#include "IPowerDownManager.h"
@@ -82,5 +82,5 @@ protected:
void printDebugMessage(std::string message);
};
#endif /* POWERDOWNMANAGERBANKWISE_H_ */
#endif // POWERDOWNMANAGERBANKWISE_H

4
DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.cpp
View File

@@ -38,9 +38,9 @@
#include "PowerDownManagerTimeout.h"
#include "../ControllerCore.h"
#include "../../../common/Utils.h"
#include "../../../common/utils.h"
#include "../../../common/DebugManager.h"
#include "../TimingCalculation.h"
#include "../timingCalculations.h"
using namespace tlm;

8
DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.h
View File

@@ -36,12 +36,12 @@
* Felipe S. Prado
*/
#ifndef POWERDOWNMANAGERTIMEOUT_H_
#define POWERDOWNMANAGERTIMEOUT_H_
#ifndef POWERDOWNMANAGERTIMEOUT_H
#define POWERDOWNMANAGERTIMEOUT_H
#include "PowerDownManager.h"
#include <systemc.h>
#include "../../../common/dramExtension.h"
#include "../../../common/dramExtensions.h"
#include "../scheduling/ScheduledCommand.h"
#include <map>
@@ -60,4 +60,4 @@ public:
#endif /* POWERDOWNMANAGERTIMEOUT_H_ */
#endif // POWERDOWNMANAGERTIMEOUT_H

4
DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp
View File

@@ -38,9 +38,9 @@
#include "PowerDownManagerTimeoutBankwise.h"
#include "../ControllerCore.h"
#include "../../../common/Utils.h"
#include "../../../common/utils.h"
#include "../../../common/DebugManager.h"
#include "../TimingCalculation.h"
#include "../timingCalculations.h"
using namespace tlm;

8
DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.h
View File

@@ -36,12 +36,12 @@
* Felipe S. Prado
*/
#ifndef POWERDOWNMANAGERTIMEOUTBANKWISE_H_
#define POWERDOWNMANAGERTIMEOUTBANKWISE_H_
#ifndef POWERDOWNMANAGERTIMEOUTBANKWISE_H
#define POWERDOWNMANAGERTIMEOUTBANKWISE_H
#include "PowerDownManager.h"
#include <systemc.h>
#include "../../../common/dramExtension.h"
#include "../../../common/dramExtensions.h"
#include "../scheduling/ScheduledCommand.h"
#include <map>
@@ -60,4 +60,4 @@ public:
#endif /* POWERDOWNMANAGERTIMEOUTBANKWISE_H_ */
#endif // POWERDOWNMANAGERTIMEOUTBANKWISE_H

6
DRAMSys/library/src/controller/core/refresh/IRefreshManager.h
View File

@@ -35,8 +35,8 @@
* Matthias Jung
*/
#ifndef IREFRESHMANAGER_H_
#define IREFRESHMANAGER_H_
#ifndef IREFRESHMANAGER_H
#define IREFRESHMANAGER_H
#include <systemc.h>
#include "../scheduling/ScheduledCommand.h"
@@ -62,5 +62,5 @@ public:
virtual bool isInvalidated(tlm::tlm_generic_payload &payload, sc_time time) = 0;
};
#endif /* IREFRESHMANAGER_H_ */
#endif // IREFRESHMANAGER_H

12
DRAMSys/library/src/controller/core/refresh/RGR.cpp
View File

@@ -36,8 +36,8 @@
#include "RGR.h"
#include "../ControllerCore.h"
#include "../TimingCalculation.h"
#include "../../../common/Utils.h"
#include "../timingCalculations.h"
#include "../../../common/utils.h"
#define TRUE 1
#define FALSE !(TRUE)
@@ -46,19 +46,19 @@
using namespace std;
RGR::RGR(sc_module_name, ControllerCore &ctrlcore) : ccore(ctrlcore),
timing(ctrlcore.config.memSpec.refreshTimings[ccore.getBanks()[0]])
timing(ctrlcore.config.memSpec->refreshTimings[ccore.getBanks()[0]])
{
fmb = ccore.config.ControllerCoreRefForceMaxPostponeBurst;
bwl = ccore.config.BankwiseLogic;
ri = ccore.config.getRowInc();
auto nr = ccore.config.memSpec.NumberOfRows;
auto nr = ccore.config.memSpec->NumberOfRows;
auto nar = ccore.config.getNumAR();
auto m = ccore.config.getRefMode();
rpr = (nr / m) / nar;
assert(rpr > 0);
tREFIx = timing.tREFI / m;
trp = ccore.config.getTrpb();
trcd = ccore.config.memSpec.tRCD;
trcd = ccore.config.memSpec->tRCD;
postponeEnabled = ccore.config.ControllerCoreRefEnablePostpone;
pullInEnabled = ccore.config.ControllerCoreRefEnablePullIn;
maxpostpone = ccore.config.ControllerCoreRefMaxPostponed * m;
@@ -73,7 +73,7 @@ RGR::RGR(sc_module_name, ControllerCore &ctrlcore) : ccore(ctrlcore),
}
#if INITIAL_DISPLACEMENT == TRUE
if (bwl) {
auto nbs = ccore.config.memSpec.NumberOfBanks;
auto nbs = ccore.config.memSpec->NumberOfBanks;
for (Bank b : ccore.getBanks()) {
nextPlannedRefreshs[b] = b.ID() * tREFIx / nbs;
}

12
DRAMSys/library/src/controller/core/refresh/RGR.h
View File

@@ -32,12 +32,15 @@
* Author: Éder F. Zulian
*/
#ifndef RGR_MANAGER_H_
#define RGR_MANAGER_H_
#include "../../../common/dramExtension.h"
#ifndef RGR_H
#define RGR_H
#include "../../../common/dramExtensions.h"
#include "../configuration/MemSpec.h"
#include "IRefreshManager.h"
class ControllerCore;
class RGR : public IRefreshManager, public sc_module
{
public:
@@ -73,5 +76,6 @@ private:
void planNextRefresh(Bank b, sc_time t, bool align);
void printDebugMessage(std::string message);
};
#endif /* RGR_MANAGER_H_ */
#endif // RGR_H

12
DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp
View File

@@ -39,14 +39,14 @@
#include "RefreshManager.h"
#include "../ControllerCore.h"
#include "../TimingCalculation.h"
#include "../../../common/Utils.h"
#include "../timingCalculations.h"
#include "../../../common/utils.h"
using namespace tlm;
RefreshManager::RefreshManager(sc_module_name,
ControllerCore &controller) : controllerCore(controller),
timing(controller.config.memSpec.refreshTimings[Bank(0)])
timing(controller.config.memSpec->refreshTimings[Bank(0)])
{
auto m = controllerCore.config.getRefMode();
tREFIx = timing.tREFI / m;
@@ -159,7 +159,7 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload &payload,
pre = doRefresh(payload, time);
nrt = tRFCx;
if (pre)
nrt += controllerCore.config.memSpec.tRP;
nrt += controllerCore.config.memSpec->tRP;
nextRefTiming = nrt;
nextState = ST_PULLIN;
} else {
@@ -175,7 +175,7 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload &payload,
pre = doRefresh(payload, time);
nrt = tRFCx;
if (pre)
nrt += controllerCore.config.memSpec.tRP;
nrt += controllerCore.config.memSpec->tRP;
nextRefTiming = nrt;
nextState = ST_PULLIN;
} else {
@@ -220,7 +220,7 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload &payload,
} else {
nrt = tRFCx;
if (pre)
nrt += controllerCore.config.memSpec.tRP;
nrt += controllerCore.config.memSpec->tRP;
nextRefTiming = nrt;
nextState = ST_BURST;
}

6
DRAMSys/library/src/controller/core/refresh/RefreshManager.h
View File

@@ -35,8 +35,8 @@
* Éder F. Zulian
*/
#ifndef REFRESHMANAGER_H_
#define REFRESHMANAGER_H_
#ifndef REFRESHMANAGER_H
#define REFRESHMANAGER_H
#include "IRefreshManager.h"
#include "../configuration/MemSpec.h"
@@ -78,5 +78,5 @@ private:
void printDebugMessage(std::string message);
};
#endif /* REFRESHMANAGER_H_ */
#endif // REFRESHMANAGER_H

12
DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp
View File

@@ -37,14 +37,14 @@
#include "RefreshManagerBankwise.h"
#include "../ControllerCore.h"
#include "../TimingCalculation.h"
#include "../../../common/Utils.h"
#include "../timingCalculations.h"
#include "../../../common/utils.h"
using namespace std;
RefreshManagerBankwise::RefreshManagerBankwise(sc_module_name,
ControllerCore &controller) : controllerCore(controller),
timing(controller.config.memSpec.refreshTimings[Bank(0)])
timing(controller.config.memSpec->refreshTimings[Bank(0)])
{
auto m = controllerCore.config.getRefMode();
tREFIx = timing.tREFI / m;
@@ -146,7 +146,7 @@ void RefreshManagerBankwise::scheduleRefresh(tlm::tlm_generic_payload &payload,
pre = doRefresh(payload, time);
nrt = tRFCx;
if (pre)
nrt += controllerCore.config.memSpec.tRP;
nrt += controllerCore.config.memSpec->tRP;
nextRefTiming = nrt;
nextState[bank] = ST_PULLIN;
} else {
@@ -162,7 +162,7 @@ void RefreshManagerBankwise::scheduleRefresh(tlm::tlm_generic_payload &payload,
pre = doRefresh(payload, time);
nrt = tRFCx;
if (pre)
nrt += controllerCore.config.memSpec.tRP;
nrt += controllerCore.config.memSpec->tRP;
nextRefTiming = nrt;
nextState[bank] = ST_PULLIN;
} else {
@@ -208,7 +208,7 @@ void RefreshManagerBankwise::scheduleRefresh(tlm::tlm_generic_payload &payload,
} else {
nrt = tRFCx;
if (pre)
nrt += controllerCore.config.memSpec.tRP;
nrt += controllerCore.config.memSpec->tRP;
nextRefTiming = nrt;
nextState[bank] = ST_BURST;
}

6
DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.h
View File

@@ -35,8 +35,8 @@
* Éder F. Zulian
*/
#ifndef BANKWISEREFRESHMANAGER_H_
#define BANKWISEREFRESHMANAGER_H_
#ifndef REFRESHMANAGERBANKWISE_H
#define REFRESHMANAGERBANKWISE_H
//#include "../../../common/dramExtension.h"
#include "IRefreshManager.h"
@@ -79,5 +79,5 @@ private:
void printDebugMessage(std::string message);
};
#endif /* BANKWISEREFRESHMANAGER_H_ */
#endif // REFRESHMANAGERBANKWISE_H

14
DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp
View File

@@ -35,8 +35,8 @@
*/
#include "ScheduledCommand.h"
#include "../TimingCalculation.h"
#include "../../../common/Utils.h"
#include "../timingCalculations.h"
#include "../../../common/utils.h"
#include "../configuration/Configuration.h"
bool ScheduledCommand::isNoCommand() const
@@ -127,13 +127,13 @@ TimeInterval ScheduledCommand::getIntervalOnDataStrobe() const
|| getCommand() == Command::Write
|| getCommand() == Command::WriteA);
MemSpec &timings = Configuration::getInstance().memSpec;
MemSpec *timings = Configuration::getInstance().memSpec;
if (getCommand() == Command::Read || getCommand() == Command::ReadA) {
return TimeInterval(getStart() + timings.tRL,
getStart() + timings.tRL + getReadAccessTime());
return TimeInterval(getStart() + timings->tRL,
getStart() + timings->tRL + getReadAccessTime());
} else {
return TimeInterval(getStart() + timings.tWL - timings.clk / 2,
getStart() + timings.tWL + getWriteAccessTime() - timings.clk / 2);
return TimeInterval(getStart() + timings->tWL - timings->clk / 2,
getStart() + timings->tWL + getWriteAccessTime() - timings->clk / 2);
}
}

10
DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.h
View File

@@ -34,14 +34,14 @@
* Matthias Jung
*/
#ifndef SCHEDULEDCOMMAND_H_
#define SCHEDULEDCOMMAND_H_
#ifndef SCHEDULEDCOMMAND_H
#define SCHEDULEDCOMMAND_H
#include <systemc.h>
#include <tlm.h>
#include "../../Command.h"
#include "../../../common/dramExtension.h"
#include "../../../common/Utils.h"
#include "../../../common/dramExtensions.h"
#include "../../../common/utils.h"
class ScheduledCommand
{
@@ -98,5 +98,5 @@ private:
DramExtension extension;
};
#endif /* SCHEDULEDCOMMAND_H_ */
#endif // SCHEDULEDCOMMAND_H

34
DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp
View File

@@ -36,10 +36,10 @@
#include <algorithm>
#include <set>
#include "ActBChecker.h"
#include "../../TimingCalculation.h"
#include "../../timingCalculations.h"
#include "../../../../common/DebugManager.h"
#include "../../../Command.h"
#include "../../../../common/Utils.h"
#include "../../../../common/utils.h"
using namespace std;
@@ -53,27 +53,27 @@ void ActBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const
Configuration::getInstance().getTrpb());
} else if (lcb.getCommand() == Command::Precharge
|| lcb.getCommand() == Command::PrechargeAll) {
cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec.tRP);
cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tRP);
} else if (lcb.getCommand() == Command::ReadA) {
cmd.establishMinDistanceFromStart(lcb.getStart(),
config.memSpec.tRTP + config.memSpec.tRP);
config.memSpec->tRTP + config.memSpec->tRP);
} else if (lcb.getCommand() == Command::WriteA) {
cmd.establishMinDistanceFromStart(lcb.getStart(),
config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR +
config.memSpec.tRP);
config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR +
config.memSpec->tRP);
} else if (lcb.getCommand() == Command::AutoRefresh) {
auto m = Configuration::getInstance().getRefMode();
if (m == 4)
cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec.tRFC4);
cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tRFC4);
else if (m == 2)
cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec.tRFC2);
cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tRFC2);
else
cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec.tRFC);
cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tRFC);
} else if (lcb.getCommand() == Command::PDNPX
|| lcb.getCommand() == Command::PDNAX) {
cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec.tXP);
cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tXP);
} else if (lcb.getCommand() == Command::SREFX) {
cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec.tXSR);
cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tXSR);
} else {
reportFatal("ActB Checker",
"ActB can not follow " + commandToString(lcb.getCommand()));
@@ -81,13 +81,13 @@ void ActBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const
}
ScheduledCommand lc;
if ((lc = state.getLastCommand(Command::PrechargeAll)).isValidCommand()) {
cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec.tRP);
cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec->tRP);
}
delay_to_satisfy_activateToActivate_sameBank(cmd);
while (!(state.bus.isFree(cmd.getStart())
&& satsfies_activateToActivate_differentBank(cmd)
&& satisfies_nActivateWindow(cmd))) {
cmd.delayStart(config.memSpec.clk);
cmd.delayStart(config.memSpec->clk);
}
}
@@ -97,7 +97,7 @@ void ActBChecker::delay_to_satisfy_activateToActivate_sameBank(
ScheduledCommand lastActOnBank = state.getLastCommand(Command::Activate,
cmd.getBank());
if (lastActOnBank.isValidCommand()) {
cmd.establishMinDistanceFromStart(lastActOnBank.getStart(), config.memSpec.tRC);
cmd.establishMinDistanceFromStart(lastActOnBank.getStart(), config.memSpec->tRC);
}
ScheduledCommand lastActBOnBank = state.getLastCommand(Command::ActB,
cmd.getBank());
@@ -121,7 +121,7 @@ bool ActBChecker::satsfies_activateToActivate_differentBank(
}
for (auto act : state.lastActivates) {
sc_time t = act.first, tRRD = (cmd.getBankGroup() == act.second.getBankGroup() ?
config.memSpec.tRRD_L : config.memSpec.tRRD_S);
config.memSpec->tRRD_L : config.memSpec->tRRD_S);
if ((t < cmd.getStart() && cmd.getStart() - t < tRRD) || (cmd.getStart() <= t
&& t - cmd.getStart() < tRRD)) {
return false;
@@ -132,11 +132,11 @@ bool ActBChecker::satsfies_activateToActivate_differentBank(
bool ActBChecker::satisfies_nActivateWindow(ScheduledCommand &cmd) const
{
if (state.lastActivatesB.size() >= config.memSpec.nActivate) {
if (state.lastActivatesB.size() >= config.memSpec->nActivate) {
map<sc_time, ScheduledCommand>lastActivates = state.lastActivatesB;
lastActivates.emplace(cmd.getStart(), cmd);
auto upper = lastActivates.begin();
advance(upper, config.memSpec.nActivate);
advance(upper, config.memSpec->nActivate);
auto lower = lastActivates.begin();
while (upper != lastActivates.end()) {
if (upper->first - lower->first < Configuration::getInstance().getTfawb()) {

12
DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.h
View File

@@ -31,13 +31,16 @@
*
* Author: Éder F. Zulian
*/
#ifndef ACTB_CHECKER_H_
#define ACTB_CHECKER_H_
#ifndef ACTBCHECKER_H
#define ACTBCHECKER_H
#include <map>
#include "ICommandChecker.h"
#include "../../configuration/Configuration.h"
#include "../../../ControllerState.h"
class ActBChecker: public ICommandChecker
class ActBChecker : public ICommandChecker
{
public:
ActBChecker(const Configuration &config,
@@ -53,4 +56,5 @@ private:
bool satsfies_activateToActivate_differentBank(ScheduledCommand &command) const;
bool satisfies_nActivateWindow(ScheduledCommand &command) const;
};
#endif /* ACTB_CHECKER_H_ */
#endif // ACTBCHECKER_H

42
DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp
View File

@@ -38,10 +38,10 @@
#include <algorithm>
#include <set>
#include "ActivateChecker.h"
#include "../../TimingCalculation.h"
#include "../../timingCalculations.h"
#include "../../../../common/DebugManager.h"
#include "../../../Command.h"
#include "../../../../common/Utils.h"
#include "../../../../common/utils.h"
using namespace std;
@@ -56,38 +56,32 @@ void ActivateChecker::delayToSatisfyConstraints(ScheduledCommand &command) const
|| lastCommandOnBank.getCommand() == Command::Precharge
|| lastCommandOnBank.getCommand() == Command::PrechargeAll) {
command.establishMinDistanceFromStart(lastCommandOnBank.getStart(),
config.memSpec.tRP);
config.memSpec->tRP);
} else if (lastCommandOnBank.getCommand() == Command::ReadA) {
command.establishMinDistanceFromStart(lastCommandOnBank.getStart(),
config.memSpec.tRTP + config.memSpec.tRP);
config.memSpec->tRTP + config.memSpec->tRP);
} else if (lastCommandOnBank.getCommand() == Command::WriteA) {
command.establishMinDistanceFromStart(lastCommandOnBank.getStart(),
config.memSpec.tRP);
} else if (lastCommandOnBank.getCommand() == Command::ReadA) {
command.establishMinDistanceFromStart(lastCommandOnBank.getStart(),
config.memSpec.tRTP + config.memSpec.tRP);
} else if (lastCommandOnBank.getCommand() == Command::WriteA) {
command.establishMinDistanceFromStart(lastCommandOnBank.getStart(),
config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR +
config.memSpec.tRP);
config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR +
config.memSpec->tRP);
} else if (lastCommandOnBank.getCommand() == Command::AutoRefresh) {
auto m = Configuration::getInstance().getRefMode();
if (m == 4)
command.establishMinDistanceFromStart(lastCommandOnBank.getStart(),
config.memSpec.tRFC4);
config.memSpec->tRFC4);
else if (m == 2)
command.establishMinDistanceFromStart(lastCommandOnBank.getStart(),
config.memSpec.tRFC2);
config.memSpec->tRFC2);
else
command.establishMinDistanceFromStart(lastCommandOnBank.getStart(),
config.memSpec.tRFC);
config.memSpec->tRFC);
} else if (lastCommandOnBank.getCommand() == Command::PDNPX
|| lastCommandOnBank.getCommand() == Command::PDNAX) {
command.establishMinDistanceFromStart(lastCommandOnBank.getStart(),
config.memSpec.tXP);
config.memSpec->tXP);
} else if (lastCommandOnBank.getCommand() == Command::SREFX) {
command.establishMinDistanceFromStart(lastCommandOnBank.getStart(),
config.memSpec.tXSR);
config.memSpec->tXSR);
} else
reportFatal("Activate Checker",
"Activate can not follow " + commandToString(lastCommandOnBank.getCommand()));
@@ -98,7 +92,7 @@ void ActivateChecker::delayToSatisfyConstraints(ScheduledCommand &command) const
while (!(state.bus.isFree(command.getStart())
&& satsfies_activateToActivate_differentBank(command)
&& satisfies_nActivateWindow(command))) {
command.delayStart(config.memSpec.clk);
command.delayStart(config.memSpec->clk);
}
}
@@ -110,14 +104,14 @@ void ActivateChecker::delay_to_satisfy_activateToActivate_sameBank(
command.getBank());
if (lastActivateOnBank.isValidCommand()) {
command.establishMinDistanceFromStart(lastActivateOnBank.getStart(),
config.memSpec.tRC);
config.memSpec->tRC);
}
ScheduledCommand lastActBOnBank = state.getLastCommand(Command::ActB,
command.getBank());
if (lastActBOnBank.isValidCommand()) {
command.establishMinDistanceFromStart(lastActivateOnBank.getStart(),
config.memSpec.tRC);
config.memSpec->tRC);
}
}
@@ -127,7 +121,7 @@ bool ActivateChecker::satsfies_activateToActivate_differentBank(
for (auto act : state.lastActivates) {
sc_time time = act.first;
sc_time tRRD = (command.getBankGroup() == act.second.getBankGroup()) ?
config.memSpec.tRRD_L : config.memSpec.tRRD_S;
config.memSpec->tRRD_L : config.memSpec->tRRD_S;
if ((time < command.getStart() && command.getStart() - time < tRRD)
|| (command.getStart() <= time && time - command.getStart() < tRRD))
@@ -143,15 +137,15 @@ bool ActivateChecker::satisfies_nActivateWindow(ScheduledCommand &command) const
* command in a copied set (not necessarily the last in time),
* and check if the n-act constraint holds for the whole set.
*/
if (state.lastActivates.size() >= config.memSpec.nActivate) {
if (state.lastActivates.size() >= config.memSpec->nActivate) {
map<sc_time, ScheduledCommand> lastActivates = state.lastActivates;
lastActivates.emplace(command.getStart(), command);
auto upper = lastActivates.begin();
advance(upper, config.memSpec.nActivate);
advance(upper, config.memSpec->nActivate);
auto lower = lastActivates.begin();
while (upper != lastActivates.end()) {
if (upper->first - lower->first < config.memSpec.tNAW)
if (upper->first - lower->first < config.memSpec->tNAW)
return false;
++upper;
++lower;

6
DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.h
View File

@@ -34,8 +34,8 @@
* Matthias Jung
*/
#ifndef ACTIVATESCHEDULER_H_
#define ACTIVATESCHEDULER_H_
#ifndef ACTIVATECHECKER_H
#define ACTIVATECHECKER_H
#include <map>
#include "ICommandChecker.h"
@@ -61,4 +61,4 @@ private:
bool satisfies_nActivateWindow(ScheduledCommand &command) const;
};
#endif /* ACTIVATESCHEDULER_H_ */
#endif // ACTIVATECHECKER_H

6
DRAMSys/library/src/controller/core/scheduling/checker/ICommandChecker.h
View File

@@ -34,8 +34,8 @@
* Matthias Jung
*/
#ifndef ICOMMANDSCHEDULER_H_
#define ICOMMANDSCHEDULER_H_
#ifndef ICOMMANDCHECKER_H
#define ICOMMANDCHECKER_H
#include <systemc.h>
#include "../ScheduledCommand.h"
@@ -50,4 +50,4 @@ public:
#endif /* ICOMMANDSCHEDULER_H_ */
#endif // ICOMMANDCHECKER_H

54
DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp
View File

@@ -36,7 +36,7 @@
*/
#include "PowerDownChecker.h"
#include "../../TimingCalculation.h"
#include "../../timingCalculations.h"
sc_time PowerDownChecker::getTimeConstraintToEnterPowerDown(Command lastCmd,
Command pdnCmd) const
@@ -47,26 +47,26 @@ sc_time PowerDownChecker::getTimeConstraintToEnterPowerDown(Command lastCmd,
sc_time constraint;
if (lastCmd == Command::Read || lastCmd == Command::ReadA) {
constraint = config.memSpec.tRL + getReadAccessTime() + config.memSpec.clk;
constraint = config.memSpec->tRL + getReadAccessTime() + config.memSpec->clk;
} else if (lastCmd == Command::Write) {
constraint = config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR;
constraint = config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR;
} else if (lastCmd == Command::WriteA) {
constraint = config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR +
config.memSpec.clk;
constraint = config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR +
config.memSpec->clk;
} else if (lastCmd == Command::AutoRefresh) {
auto m = Configuration::getInstance().getRefMode();
if (m == 4)
constraint = config.memSpec.tRFC4;
constraint = config.memSpec->tRFC4;
else if (m == 2)
constraint = config.memSpec.tRFC2;
constraint = config.memSpec->tRFC2;
else
constraint = config.memSpec.tRFC;
constraint = config.memSpec->tRFC;
} else if (lastCmd == Command::PDNPX || lastCmd == Command::PDNAX) {
constraint = config.memSpec.tXP;
constraint = config.memSpec->tXP;
} else if (lastCmd == Command::SREFX) {
constraint = config.memSpec.tXSR;
constraint = config.memSpec->tXSR;
} else if (lastCmd == Command::Precharge || lastCmd == Command::PrechargeAll) {
constraint = config.memSpec.tRP;
constraint = config.memSpec->tRP;
} else {
reportFatal("Powerdown checker",
commandToString(pdnCmd) + " can not follow " + commandToString(lastCmd));
@@ -93,33 +93,41 @@ const
// PDNP - Precharge Power Down
// SREF - Self Refresh
// Get the last scheduled command on this bank
ScheduledCommand lastSchedCmdOnBank = state.getLastScheduledCommand(bank);
// Get the last scheduled command
ScheduledCommand lastSchedCmd;
if(Configuration::getInstance().BankwiseLogic)
{
lastSchedCmd = state.getLastScheduledCommand(bank);
}
else
{
lastSchedCmd = state.getLastScheduledCommand();
}
if (lastSchedCmdOnBank.isValidCommand()) {
// Get the start time for the last scheduled command on this bank
sc_time lastSchedCmdOnBankStart = lastSchedCmdOnBank.getStart();
// Get the last command on this bank itself
Command lastCmdBank = lastSchedCmdOnBank.getCommand();
if (lastSchedCmd.isValidCommand()) {
// Get the start time for the last scheduled command
sc_time lastSchedCmdStart = lastSchedCmd.getStart();
// Get the last command
Command lastCmd = lastSchedCmd.getCommand();
timeConstraint = getTimeConstraintToEnterPowerDown(lastCmdBank, pdnCmd);
timeConstraint = getTimeConstraintToEnterPowerDown(lastCmd, pdnCmd);
command.establishMinDistanceFromStart(lastSchedCmdOnBankStart, timeConstraint);
command.establishMinDistanceFromStart(lastSchedCmdStart, timeConstraint);
}
} else if (pdnCmd == Command::PDNAX) {
// Leaving Active Power Down
timeConstraint = config.memSpec.tCKE;
timeConstraint = config.memSpec->tCKE;
command.establishMinDistanceFromStart(state.getLastCommand(Command::PDNA,
bank).getStart(), timeConstraint);
} else if (pdnCmd == Command::PDNPX) {
// Leaving Precharge Power Down
timeConstraint = config.memSpec.tCKE;
timeConstraint = config.memSpec->tCKE;
command.establishMinDistanceFromStart(state.getLastCommand(Command::PDNP,
bank).getStart(), timeConstraint);
} else if (pdnCmd == Command::SREFX) {
// Leaving Self Refresh
timeConstraint = config.memSpec.tCKESR;
timeConstraint = config.memSpec->tCKESR;
command.establishMinDistanceFromStart(state.getLastCommand(Command::SREF,
bank).getStart(), timeConstraint);
}

6
DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.h
View File

@@ -34,8 +34,8 @@
* Matthias Jung
*/
#ifndef POWERDOWNCHECKER_H_
#define POWERDOWNCHECKER_H_
#ifndef POWERDOWNCHECKER_H
#define POWERDOWNCHECKER_H
#include <systemc>
@@ -60,5 +60,5 @@ private:
Command pdnCmd) const;
};
#endif /* POWERDOWNCHECKER_H_ */
#endif // POWERDOWNCHECKER_H

22
DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp
View File

@@ -33,8 +33,8 @@
*/
#include "PreBChecker.h"
#include "../../TimingCalculation.h"
void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd)const
#include "../../timingCalculations.h"
void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const
{
sc_assert(cmd.getCommand() == Command::PreB);
ScheduledCommand lastCmd = state.getLastScheduledCommand(cmd.getBank());
@@ -43,21 +43,21 @@ void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd)const
cmd.establishMinDistanceFromStart(lastCmd.getStart(),
Configuration::getInstance().getTrpb());
} else if (lastCmd.getCommand() == Command::Precharge) {
cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec.tRP);
cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRP);
} else if (lastCmd.getCommand() == Command::PrechargeAll) {
cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec.tRP);
cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRP);
} else if (lastCmd.getCommand() == Command::ActB) {
cmd.establishMinDistanceFromStart(lastCmd.getStart(),
config.memSpec.tRCD); // XXX: trcd is less than the NEW! trasb! ok!
config.memSpec->tRCD); // XXX: trcd is less than the NEW! trasb! ok!
} else if (lastCmd.getCommand() == Command::Activate) {
cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec.tRCD);
cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRCD);
} else if (lastCmd.getCommand() == Command::Read) {
cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec.tRTP);
cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRTP);
} else if (lastCmd.getCommand() == Command::Write) {
cmd.establishMinDistanceFromStart(lastCmd.getStart(),
config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR);
config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR);
} else if (lastCmd.getCommand() == Command::PDNAX) {
cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec.tXP);
cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tXP);
} else {
reportFatal("PreB Checker",
"PreB can not follow " + commandToString(lastCmd.getCommand()));
@@ -65,11 +65,11 @@ void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd)const
}
ScheduledCommand lc;
if ((lc = state.getLastCommand(Command::PrechargeAll)).isValidCommand()) {
cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec.tRP);
cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec->tRP);
}
if ((lc = state.getLastCommand(Command::Activate,
cmd.getBank())).isValidCommand()) {
cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec.tRAS);
cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec->tRAS);
}
if ((lc = state.getLastCommand(Command::ActB,
cmd.getBank())).isValidCommand()) {

10
DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.h
View File

@@ -31,11 +31,14 @@
*
* Author: Éder F. Zulian
*/
#ifndef PREB_CHECKER_H_
#define PREB_CHECKER_H_
#ifndef PREBCHECKER_H
#define PREBCHECKER_H
#include "ICommandChecker.h"
#include "../../configuration/Configuration.h"
#include "../../../ControllerState.h"
class PreBChecker: public ICommandChecker
{
public:
@@ -48,4 +51,5 @@ private:
const Configuration &config;
ControllerState &state;
};
#endif /* PREB_CHECKER_H_ */
#endif // PREBCHECKER_H

30
DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp
View File

@@ -36,7 +36,7 @@
*/
#include "PrechargeAllChecker.h"
#include "../../TimingCalculation.h"
#include "../../timingCalculations.h"
void PrechargeAllChecker::delayToSatisfyConstraints(ScheduledCommand &command)
@@ -45,48 +45,48 @@ const
sc_assert(command.getCommand() == Command::PrechargeAll);
// Consider all banks for the constraints, since precharge all command is supposed to happen at the same time on all banks
for (unsigned int bank = 0; bank < config.memSpec.NumberOfBanks; ++bank) {
for (unsigned int bank = 0; bank < config.memSpec->NumberOfBanks; ++bank) {
ScheduledCommand lastCommand = state.getLastScheduledCommand(Bank(bank));
if (lastCommand.isValidCommand()) {
if (lastCommand.getCommand() == Command::Precharge
|| lastCommand.getCommand() == Command::PreB) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec.tRP);
config.memSpec->tRP);
} else if (lastCommand.getCommand() == Command::Activate
|| lastCommand.getCommand() == Command::ActB) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec.tRCD);
config.memSpec->tRCD);
} else if (lastCommand.getCommand() == Command::Read) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec.tRTP);
config.memSpec->tRTP);
} else if (lastCommand.getCommand() == Command::ReadA) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec.tRTP + config.memSpec.tRP);
config.memSpec->tRTP + config.memSpec->tRP);
} else if (lastCommand.getCommand() == Command::Write) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR);
config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR);
} else if (lastCommand.getCommand() == Command::WriteA) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR +
config.memSpec.tRP);
config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR +
config.memSpec->tRP);
} else if (lastCommand.getCommand() == Command::AutoRefresh) {
auto m = Configuration::getInstance().getRefMode();
if (m == 4)
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec.tRFC4);
config.memSpec->tRFC4);
else if (m == 2)
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec.tRFC2);
config.memSpec->tRFC2);
else
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec.tRFC);
config.memSpec->tRFC);
} else if (lastCommand.getCommand() == Command::PDNAX
|| lastCommand.getCommand() == Command::PDNPX) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec.tXP);
config.memSpec->tXP);
} else if (lastCommand.getCommand() == Command::SREFX) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec.tXSR);
config.memSpec->tXSR);
} else
reportFatal("Precharge All Checker",
"Precharge All can not follow " + commandToString(lastCommand.getCommand()));
@@ -97,7 +97,7 @@ const
command.getBank());
if (lastActivate.isValidCommand()) {
command.establishMinDistanceFromStart(lastActivate.getStart(),
config.memSpec.tRAS);
config.memSpec->tRAS);
}
state.bus.moveCommandToNextFreeSlot(command);

7
DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.h
View File

@@ -34,14 +34,13 @@
* Matthias Jung
*/
#ifndef PRECHARGEALLCHECKER_H_
#define PRECHARGEALLCHECKER_H_
#ifndef PRECHARGEALLCHECKER_H
#define PRECHARGEALLCHECKER_H
#include "ICommandChecker.h"
#include "../../configuration/Configuration.h"
#include "../../../ControllerState.h"
class PrechargeAllChecker: public ICommandChecker
{
public:
@@ -62,4 +61,4 @@ private:
};
#endif /* PRECHARGEALLCHECKER_H_ */
#endif // PRECHARGEALLCHECKER_H

14
DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp
View File

@@ -35,7 +35,7 @@
*/
#include "PrechargeChecker.h"
#include "../../TimingCalculation.h"
#include "../../timingCalculations.h"
void PrechargeChecker::delayToSatisfyConstraints(ScheduledCommand &command)
@@ -52,23 +52,23 @@ const
if (lastCommand.getCommand() == Command::Precharge
|| lastCommand.getCommand() == Command::PreB) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec.tRP);
config.memSpec->tRP);
} else if (lastCommand.getCommand() == Command::Activate
|| lastCommand.getCommand() == Command::ActB) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec.tRCD);
config.memSpec->tRCD);
}
else if (lastCommand.getCommand() == Command::Read) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec.tRTP);
config.memSpec->tRTP);
} else if (lastCommand.getCommand() == Command::Write) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR);
config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR);
} else if (lastCommand.getCommand() == Command::PDNAX) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec.tXP);
config.memSpec->tXP);
} else
reportFatal("Precharge Checker",
"Precharge can not follow " + commandToString(lastCommand.getCommand()));
@@ -78,7 +78,7 @@ const
command.getBank());
if (lastActivate.isValidCommand()) {
command.establishMinDistanceFromStart(lastActivate.getStart(),
config.memSpec.tRAS);
config.memSpec->tRAS);
}
state.bus.moveCommandToNextFreeSlot(command);

7
DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.h
View File

@@ -34,14 +34,13 @@
* Matthias Jung
*/
#ifndef PRECHARGECHECKER_H_
#define PRECHARGECHECKER_H_
#ifndef PRECHARGECHECKER_H
#define PRECHARGECHECKER_H
#include "ICommandChecker.h"
#include "../../configuration/Configuration.h"
#include "../../../ControllerState.h"
class PrechargeChecker: public ICommandChecker
{
public:
@@ -57,4 +56,4 @@ private:
};
#endif /* PRECHARGECHECKER_H_ */
#endif // PRECHARGECHECKER_

24
DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp
View File

@@ -35,8 +35,8 @@
*/
#include "ReadChecker.h"
#include "../../TimingCalculation.h"
#include "../../../../common/Utils.h"
#include "../../timingCalculations.h"
#include "../../../../common/utils.h"
#include "WriteChecker.h"
using namespace std;
@@ -52,7 +52,7 @@ void ReadChecker::delayToSatisfyConstraints(ScheduledCommand &command) const
if (lastCommand.getCommand() == Command::Activate
|| lastCommand.getCommand() == Command::ActB) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec.tRCD);
config.memSpec->tRCD);
} else if (lastCommand.getCommand() == Command::Read) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
ReadChecker::readToRead(lastCommand, command));
@@ -62,14 +62,14 @@ void ReadChecker::delayToSatisfyConstraints(ScheduledCommand &command) const
} else if (lastCommand.getCommand() == Command::PDNPX
|| lastCommand.getCommand() == Command::PDNAX) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec.tXP);
config.memSpec->tXP);
} else
reportFatal("Read Checker",
"Read can not follow " + commandToString(lastCommand.getCommand()));
}
while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe(command)) {
command.delayStart(config.memSpec.clk);
command.delayStart(config.memSpec->clk);
}
}
@@ -112,7 +112,7 @@ void ReadChecker::delayToSatisfyDLL(ScheduledCommand &read) const
read.getBank());
if (lastSREFX.isValidCommand())
read.establishMinDistanceFromStart(lastSREFX.getStart(),
config.memSpec.tXSRDLL);
config.memSpec->tXSRDLL);
}
sc_time ReadChecker::readToRead(ScheduledCommand &firstRead,
@@ -123,9 +123,9 @@ sc_time ReadChecker::readToRead(ScheduledCommand &firstRead,
sc_assert(secondRead.getCommand() == Command::Read
|| secondRead.getCommand() == Command::ReadA);
MemSpec &config = Configuration::getInstance().memSpec;
MemSpec *config = Configuration::getInstance().memSpec;
sc_time tCCD = (firstRead.getBankGroup() == secondRead.getBankGroup()) ?
config.tCCD_L : config.tCCD_S;
config->tCCD_L : config->tCCD_S;
return max(tCCD, getReadAccessTime());
}
@@ -137,9 +137,9 @@ sc_time ReadChecker::writeToRead(ScheduledCommand &write,
sc_assert(write.getCommand() == Command::Write
|| write.getCommand() == Command::WriteA);
MemSpec &config = Configuration::getInstance().memSpec;
sc_time tWTR = (write.getBankGroup() == read.getBankGroup()) ? config.tWTR_L :
config.tWTR_S;
return config.tWL + getWriteAccessTime() + tWTR;
MemSpec *config = Configuration::getInstance().memSpec;
sc_time tWTR = (write.getBankGroup() == read.getBankGroup()) ? config->tWTR_L :
config->tWTR_S;
return config->tWL + getWriteAccessTime() + tWTR;
}

6
DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.h
View File

@@ -34,8 +34,8 @@
* Matthias Jung
*/
#ifndef READCHECKER_H_
#define READCHECKER_H_
#ifndef READCHECKER_H
#define READCHECKER_H
#include "ICommandChecker.h"
#include "../../configuration/Configuration.h"
@@ -65,5 +65,5 @@ private:
ScheduledCommand &strobeCommand) const;
};
#endif /* READCHECKER_H_ */
#endif // READCHECKER_H

30
DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp
View File

@@ -36,7 +36,7 @@
*/
#include "RefreshChecker.h"
#include "../../TimingCalculation.h"
#include "../../timingCalculations.h"
void RefreshChecker::delayToSatisfyConstraints(ScheduledCommand &command) const
{
@@ -50,53 +50,53 @@ void RefreshChecker::delayToSatisfyConstraints(ScheduledCommand &command) const
if (lastCommandOnBank.getCommand() == Command::Precharge
|| lastCommandOnBank.getCommand() == Command::PrechargeAll) {
command.establishMinDistanceFromStart(lastCommandOnBank.getStart(),
config.memSpec.tRP);
config.memSpec->tRP);
} else if (lastCommandOnBank.getCommand() == Command::ReadA) {
command.establishMinDistanceFromStart(lastCommandOnBank.getStart(),
config.memSpec.tRTP + config.memSpec.tRP);
config.memSpec->tRTP + config.memSpec->tRP);
} else if (lastCommandOnBank.getCommand() == Command::WriteA) {
command.establishMinDistanceFromStart(lastCommandOnBank.getStart(),
config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR +
config.memSpec.tRP);
config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR +
config.memSpec->tRP);
} else if (lastCommandOnBank.getCommand() == Command::PDNPX
|| lastCommandOnBank.getCommand() == Command::PDNAX) {
command.establishMinDistanceFromStart(lastCommandOnBank.getStart(),
config.memSpec.tXP);
config.memSpec->tXP);
} else if (lastCommandOnBank.getCommand() == Command::SREFX) {
command.establishMinDistanceFromStart(lastCommandOnBank.getStart(),
config.memSpec.tXSR);
config.memSpec->tXSR);
} else if (lastCommandOnBank.getCommand() == Command::AutoRefresh) {
} else
reportFatal("Refresh Checker",
"Refresh can not follow " + commandToString(lastCommandOnBank.getCommand()));
}
} else {
for (unsigned int bank = 0; bank < config.memSpec.NumberOfBanks; ++bank) {
for (unsigned int bank = 0; bank < config.memSpec->NumberOfBanks; ++bank) {
ScheduledCommand lastCommand = state.getLastScheduledCommand(Bank(bank));
if (lastCommand.isValidCommand()) {
if (lastCommand.getCommand() == Command::Precharge
|| lastCommand.getCommand() == Command::PrechargeAll
|| lastCommand.getCommand() == Command::PreB) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec.tRP);
config.memSpec->tRP);
} else if (lastCommand.getCommand() == Command::Activate
|| lastCommand.getCommand() == Command::ActB) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec.tRCD);
config.memSpec->tRCD);
} else if (lastCommand.getCommand() == Command::ReadA) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec.tRTP + config.memSpec.tRP);
config.memSpec->tRTP + config.memSpec->tRP);
} else if (lastCommand.getCommand() == Command::WriteA) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR +
config.memSpec.tRP);
config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR +
config.memSpec->tRP);
} else if (lastCommand.getCommand() == Command::PDNAX
|| lastCommand.getCommand() == Command::PDNPX) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec.tXP);
config.memSpec->tXP);
} else if (lastCommand.getCommand() == Command::SREFX) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec.tXSR);
config.memSpec->tXSR);
} else if (lastCommand.getCommand() == Command::AutoRefresh) {
} else
reportFatal("Refresh Checker",

9
DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.h
View File

@@ -34,16 +34,15 @@
* Matthias Jung
*/
#ifndef REFRESHCHECKER_H_
#define REFRESHCHECKER_H_
#ifndef REFRESHCHECKER_H
#define REFRESHCHECKER_H
#include "ICommandChecker.h"
#include "../../../ControllerState.h"
#include "../../configuration/Configuration.h"
#include <systemc>
class RefreshChecker: public ICommandChecker
class RefreshChecker : public ICommandChecker
{
public:
RefreshChecker(const Configuration &config, ControllerState &state) :
@@ -64,4 +63,4 @@ private:
};
#endif /* REFRESHCHECKER_H_ */
#endif // REFRESHCHECKER_H

18
DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp
View File

@@ -35,8 +35,8 @@
*/
#include "WriteChecker.h"
#include "../../TimingCalculation.h"
#include "../../../../common/Utils.h"
#include "../../timingCalculations.h"
#include "../../../../common/utils.h"
#include "ReadChecker.h"
using namespace std;
@@ -52,7 +52,7 @@ void WriteChecker::delayToSatisfyConstraints(ScheduledCommand &command) const
if (lastCommand.getCommand() == Command::Activate
|| lastCommand.getCommand() == Command::ActB) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec.tRCD);
config.memSpec->tRCD);
} else if (lastCommand.getCommand() == Command::Read) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
WriteChecker::readToWrite(lastCommand, command));
@@ -62,14 +62,14 @@ void WriteChecker::delayToSatisfyConstraints(ScheduledCommand &command) const
} else if (lastCommand.getCommand() == Command::PDNPX
|| lastCommand.getCommand() == Command::PDNAX) {
command.establishMinDistanceFromStart(lastCommand.getStart(),
config.memSpec.tXP);
config.memSpec->tXP);
} else
reportFatal("Write Checker",
"Write can not follow " + commandToString(lastCommand.getCommand()));
}
while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe(command)) {
command.delayStart(config.memSpec.clk);
command.delayStart(config.memSpec->clk);
}
}
@@ -114,9 +114,9 @@ sc_time WriteChecker::writeToWrite(ScheduledCommand &firstWrite,
sc_assert(secondWrite.getCommand() == Command::Write
|| secondWrite.getCommand() == Command::WriteA);
MemSpec &config = Configuration::getInstance().memSpec;
MemSpec *config = Configuration::getInstance().memSpec;
sc_time tCCD = (firstWrite.getBankGroup() == secondWrite.getBankGroup()) ?
config.tCCD_L : config.tCCD_S;
config->tCCD_L : config->tCCD_S;
return max(tCCD, getWriteAccessTime());
}
@@ -128,7 +128,7 @@ sc_time WriteChecker::readToWrite(ScheduledCommand &read __attribute__((
sc_assert(write.getCommand() == Command::Write
|| write.getCommand() == Command::WriteA);
MemSpec &config = Configuration::getInstance().memSpec;
return config.tRL + getReadAccessTime() - config.tWL + config.clk * 2;
MemSpec *config = Configuration::getInstance().memSpec;
return config->tRL + getReadAccessTime() - config->tWL + config->clk * 2;
}

9
DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.h
View File

@@ -34,15 +34,14 @@
* Matthias Jung
*/
#ifndef WRITECHECKER_H_
#define WRITECHECKER_H_
#ifndef WRITECHECKER_H
#define WRITECHECKER_H
#include "ICommandChecker.h"
#include "../../configuration/Configuration.h"
#include "../../../ControllerState.h"
class WriteChecker: public ICommandChecker
class WriteChecker : public ICommandChecker
{
public:
WriteChecker(const Configuration &config,
@@ -64,4 +63,4 @@ private:
};
#endif /* WRITECHECKER_H_ */
#endif // WRITECHECKER_H

50
DRAMSys/library/src/controller/core/TimingCalculation.cpp → DRAMSys/library/src/controller/core/timingCalculations.cpp
View File

@@ -34,12 +34,12 @@
* Matthias Jung
*/
#include "TimingCalculation.h"
#include "timingCalculations.h"
#include "configuration/MemSpec.h"
#include "ControllerCore.h"
#include "../../common/DebugManager.h"
#include "configuration/Configuration.h"
#include "../../common/Utils.h"
#include "../../common/utils.h"
@@ -59,7 +59,7 @@ const sc_time FrequencyToClk(double frequencyMhz)
const sc_time clkAlign(sc_time time, Alignment alignment)
{
sc_time clk = Configuration::getInstance().memSpec.clk;
sc_time clk = Configuration::getInstance().memSpec->clk;
if (alignment == UP)
return ceil(time / clk) * clk;
else
@@ -69,39 +69,39 @@ const sc_time clkAlign(sc_time time, Alignment alignment)
// Returns the execution time for commands that have a fixed execution time
sc_time getExecutionTime(Command command, tlm::tlm_generic_payload &payload)
{
MemSpec &config = Configuration::getInstance().memSpec;
MemSpec *config = Configuration::getInstance().memSpec;
if (command == Command::PreB) {
return Configuration::getInstance().getTrpb();
} else if (command == Command::Precharge || command == Command::PrechargeAll) {
return config.tRP;
return config->tRP;
} else if (command == Command::ActB) {
return config.tRCD;
return config->tRCD;
} else if (command == Command::Activate) {
return config.tRCD;
return config->tRCD;
} else if (command == Command::Read) {
return config.tRL + getReadAccessTime();
return config->tRL + getReadAccessTime();
} else if (command == Command::ReadA) {
return config.tRTP + config.tRP;
return config->tRTP + config->tRP;
} else if (command == Command::Write) {
return config.tWL + getWriteAccessTime();
return config->tWL + getWriteAccessTime();
} else if (command == Command::WriteA) {
return config.tWL + getWriteAccessTime() + config.tWR + config.tRP;
return config->tWL + getWriteAccessTime() + config->tWR + config->tRP;
} else if (command == Command::PrechargeAll) {
return config.tRP;
return config->tRP;
} else if (command == Command::AutoRefresh) {
if (Configuration::getInstance().getRefMode() == 4)
return getElementFromMap(config.refreshTimings,
return getElementFromMap(config->refreshTimings,
DramExtension::getExtension(payload).getBank()).tRFC4;
else if (Configuration::getInstance().getRefMode() == 2)
return getElementFromMap(config.refreshTimings,
return getElementFromMap(config->refreshTimings,
DramExtension::getExtension(payload).getBank()).tRFC2;
else
return getElementFromMap(config.refreshTimings,
return getElementFromMap(config->refreshTimings,
DramExtension::getExtension(payload).getBank()).tRFC;
} else if (command == Command::PDNAX || command == Command::PDNPX
|| command == Command::SREFX) {
return config.clk;
return config->clk;
} else {
SC_REPORT_FATAL("getExecutionTime",
"command not known or command doesn't have a fixed execution time");
@@ -112,11 +112,11 @@ sc_time getExecutionTime(Command command, tlm::tlm_generic_payload &payload)
// Returns the minimum execution time for commands that have a variable execution time
sc_time getMinExecutionTimeForPowerDownCmd(Command command)
{
MemSpec &config = Configuration::getInstance().memSpec;
MemSpec *config = Configuration::getInstance().memSpec;
if (command == Command::PDNA || command == Command::PDNP) {
return config.tCKE;
return config->tCKE;
} else if (command == Command::SREF) {
return config.tCKESR;
return config->tCKESR;
} else {
SC_REPORT_FATAL("getMinimalExecutionTime",
"command is not know or command has a fixed execution time");
@@ -133,19 +133,19 @@ bool isClkAligned(sc_time time, sc_time clk)
sc_time getReadAccessTime()
{
Configuration &config = Configuration::getInstance();
return (config.memSpec.BurstLength / config.memSpec.DataRate) *
config.memSpec.clk;
return (config.memSpec->BurstLength / config.memSpec->DataRate) *
config.memSpec->clk;
}
sc_time getWriteAccessTime()
{
Configuration &config = Configuration::getInstance();
if (config.memSpec.DataRate == 1) {
return config.memSpec.clk * (config.memSpec.BurstLength);
if (config.memSpec->DataRate == 1) {
return config.memSpec->clk * (config.memSpec->BurstLength);
} else {
return config.memSpec.clk * (config.memSpec.BurstLength /
config.memSpec.DataRate);
return config.memSpec->clk * (config.memSpec->BurstLength /
config.memSpec->DataRate);
}
}

9
DRAMSys/library/src/controller/core/TimingCalculation.h → DRAMSys/library/src/controller/core/timingCalculations.h
View File

@@ -34,15 +34,14 @@
* Matthias Jung
*/
#ifndef UTILS_H_
#define UTILS_H_
#ifndef TIMINGCALCULATIONS_H
#define TIMINGCALCULATIONS_H
#include <systemc.h>
#include <tlm.h>
#include "../../common/dramExtension.h"
#include "../../common/dramExtensions.h"
#include "../Command.h"
sc_time getMinExecutionTimeForPowerDownCmd(Command command);
sc_time getExecutionTime(Command command, tlm::tlm_generic_payload &payload);
@@ -56,4 +55,4 @@ const sc_time clkAlign(sc_time time, Alignment alignment = UP);
bool isClkAligned(sc_time time, sc_time clk);
const sc_time FrequencyToClk(double frequencyMhz);
#endif /* UTILS_H_ */
#endif // TIMINGCALCULATIONS_H

23
DRAMSys/library/src/controller/scheduler/Fifo.cpp
View File

@@ -36,27 +36,30 @@
#include "Fifo.h"
using namespace std;
void Fifo::storeRequest(gp *payload)
{
buffer[DramExtension::getExtension(payload).getBank()].emplace_back(payload);
Bank bank = DramExtension::getExtension(payload).getBank();
buffer[bank].emplace_back(payload);
}
pair<Command, tlm::tlm_generic_payload *> Fifo::getNextRequest(Bank bank)
std::pair<Command, tlm::tlm_generic_payload *> Fifo::getNextRequest(Bank bank)
{
if (!buffer[bank].empty()) {
if (!buffer[bank].empty())
{
gp *payload = buffer[bank].front();
Command command = IScheduler::getNextCommand(*payload);
Command command = IScheduler::getNextCommand(payload);
if (command == Command::Read || command == Command::ReadA
|| command == Command::Write || command == Command::WriteA) {
|| command == Command::Write || command == Command::WriteA)
{
buffer[bank].pop_front();
}
return pair<Command, tlm::tlm_generic_payload *>(command, payload);
return std::pair<Command, tlm::tlm_generic_payload *>(command, payload);
}
else
{
return std::pair<Command, tlm::tlm_generic_payload *>(Command::NOP, NULL);
}
return pair<Command, tlm::tlm_generic_payload *>(Command::NOP, NULL);
}
gp *Fifo::getPendingRequest(Bank /*bank*/)

17
DRAMSys/library/src/controller/scheduler/Fifo.h
View File

@@ -34,15 +34,16 @@
* Matthias Jung
*/
#ifndef FIFO_H_
#define FIFO_H_
#ifndef FIFO_H
#define FIFO_H
#include <deque>
#include <map>
#include <utility>
#include "../core/ControllerCore.h"
#include "../Command.h"
#include "IScheduler.h"
#include <deque>
#include <map>
#include <utility>
class Fifo : public IScheduler
{
@@ -51,12 +52,12 @@ public:
virtual ~Fifo() {}
void storeRequest(gp *payload) override;
std::pair<Command, tlm::tlm_generic_payload *> getNextRequest(
Bank bank) override;
std::pair<Command, tlm::tlm_generic_payload *>
getNextRequest(Bank bank) override;
virtual gp *getPendingRequest(Bank bank) override;
private:
std::map<Bank, std::deque<gp *>> buffer;
};
#endif /* FIFO_H_ */
#endif // FIFO_H

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