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Bugfix for triggering controllerMethod() multiple times at the same time.

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This commit is contained in:
Lukas Steiner
2019-10-15 20:26:49 +02:00
parent 2aa5d125c7
commit a3fa363a87
12 changed files with 31 additions and 21 deletions
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4
DRAMSys/library/src/common/TlmRecorder.cpp
View File

@@ -205,8 +205,8 @@ void TlmRecorder::Transaction::insertPhase(string name, sc_time begin)
void TlmRecorder::Transaction::setPhaseEnd(string name, sc_time end)
{
// Find the latest recorder phase for that transaction with a matching name and update it
// Note: Transaction have the same phase multiple times (e.g. PRE->ACT->REF->ACT->RD) only update the latest
// one that has been recorder
// Note: Transactions might have the same phase multiple times (e.g. PRE->ACT->REF->ACT->RD)
// only update the latest one that has been recorded
for (int i = recordedPhases.size() - 1; i >= 0; i--) {
Phase &data = recordedPhases[i];
if (data.name == name) {

12
DRAMSys/library/src/controller/BankMachine.cpp
View File

@@ -112,6 +112,8 @@ BankMachineOpen::BankMachineOpen(SchedulerIF *scheduler, CheckerIF *checker, Ban
sc_time BankMachineOpen::start()
{
timeToSchedule = sc_max_time();
if (blocked)
return sc_max_time() - sc_time_stamp();
else if (currentPayload == nullptr)
@@ -120,7 +122,6 @@ sc_time BankMachineOpen::start()
if (currentPayload == nullptr)
return sc_max_time() - sc_time_stamp();
}
sc_time delay;
DramExtension extension = DramExtension::getExtension(currentPayload);
if (currentState == BmState::Precharged) // row miss
@@ -162,6 +163,8 @@ BankMachineClosed::BankMachineClosed(SchedulerIF *scheduler, CheckerIF *checker,
sc_time BankMachineClosed::start()
{
timeToSchedule = sc_max_time();
if (blocked)
return sc_max_time() - sc_time_stamp();
else if (currentPayload == nullptr)
@@ -170,7 +173,6 @@ sc_time BankMachineClosed::start()
if (currentPayload == nullptr)
return sc_max_time() - sc_time_stamp();
}
sc_time delay;
DramExtension extension = DramExtension::getExtension(currentPayload);
if (currentState == BmState::Precharged) // row miss
@@ -212,6 +214,8 @@ BankMachineOpenAdaptive::BankMachineOpenAdaptive(SchedulerIF *scheduler, Checker
sc_time BankMachineOpenAdaptive::start()
{
timeToSchedule = sc_max_time();
if (blocked)
return sc_max_time() - sc_time_stamp();
else if (currentPayload == nullptr)
@@ -220,7 +224,6 @@ sc_time BankMachineOpenAdaptive::start()
if (currentPayload == nullptr)
return sc_max_time() - sc_time_stamp();
}
sc_time delay;
DramExtension extension = DramExtension::getExtension(currentPayload);
if (currentState == BmState::Precharged) // row miss
@@ -280,6 +283,8 @@ BankMachineClosedAdaptive::BankMachineClosedAdaptive(SchedulerIF *scheduler, Che
sc_time BankMachineClosedAdaptive::start()
{
timeToSchedule = sc_max_time();
if (blocked)
return sc_max_time() - sc_time_stamp();
else if (currentPayload == nullptr)
@@ -288,7 +293,6 @@ sc_time BankMachineClosedAdaptive::start()
if (currentPayload == nullptr)
return sc_max_time() - sc_time_stamp();
}
sc_time delay;
DramExtension extension = DramExtension::getExtension(currentPayload);
if (currentState == BmState::Precharged) // row miss

2
DRAMSys/library/src/controller/BankMachine.h
View File

@@ -80,7 +80,7 @@ protected:
Row nextRow;
BmState currentState = BmState::Precharged;
Row currentRow;
sc_time timeToSchedule = SC_ZERO_TIME;
sc_time timeToSchedule = sc_max_time();
Rank rank = Rank(0);
BankGroup bankgroup = BankGroup(0);
Bank bank;

9
DRAMSys/library/src/controller/Controller.cpp
View File

@@ -124,7 +124,10 @@ Controller::Controller(sc_module_name name) :
}
if (config.ControllerCoreRefDisable)
refreshManagers.push_back(new RefreshManagerDummy());
{
for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++)
refreshManagers.push_back(new RefreshManagerDummy());
}
else if (config.BankwiseLogic)
{
for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++)
@@ -307,8 +310,9 @@ void Controller::releasePayload()
payloadToRelease->release();
numberOfPayloads--;
payloadToRelease = nullptr;
timeToRelease = sc_max_time();
numberOfTransactionsServed++;
if (numberOfPayloads == 0)
startBandwidthIdleCollector();
}
@@ -327,6 +331,7 @@ void Controller::acquirePayload()
payloadToAcquire->set_response_status(TLM_OK_RESPONSE);
sendToFrontend(payloadToAcquire, END_REQ);
payloadToAcquire = nullptr;
timeToAcquire = sc_max_time();
}
void Controller::sendToFrontend(tlm_generic_payload *payload, tlm_phase phase)

4
DRAMSys/library/src/controller/Controller.h
View File

@@ -75,9 +75,9 @@ private:
unsigned numberOfPayloads = 0;
unsigned maxNumberOfPayloads;
tlm_generic_payload *payloadToAcquire = nullptr;
sc_time timeToAcquire = SC_ZERO_TIME;
sc_time timeToAcquire = sc_max_time();
tlm_generic_payload *payloadToRelease = nullptr;
sc_time timeToRelease = SC_ZERO_TIME;
sc_time timeToRelease = sc_max_time();
std::queue<std::pair<sc_time, tlm_generic_payload *>> responseQueue;
std::vector<BankMachine *> bankMachines;

3
DRAMSys/library/src/controller/refresh/RefreshManager.cpp
View File

@@ -61,7 +61,8 @@ std::pair<Command, tlm_generic_payload *> RefreshManager::getNextCommand()
sc_time RefreshManager::start()
{
timeToSchedule = SC_ZERO_TIME;
timeToSchedule = sc_max_time();
if (sc_time_stamp() >= timeForNextTrigger)
{
if (sc_time_stamp() >= timeForNextTrigger + memSpec->getRefreshIntervalAB())

4
DRAMSys/library/src/controller/refresh/RefreshManager.h
View File

@@ -56,8 +56,8 @@ private:
const MemSpec *memSpec;
std::vector<BankMachine *> bankMachines;
tlm_generic_payload refreshPayload;
sc_time timeForNextTrigger;
sc_time timeToSchedule = SC_ZERO_TIME;
sc_time timeForNextTrigger = sc_max_time();
sc_time timeToSchedule = sc_max_time();
Rank rank;
CheckerIF *checker;
Command nextCommand;

3
DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp
View File

@@ -68,7 +68,8 @@ std::pair<Command, tlm_generic_payload *> RefreshManagerBankwise::getNextCommand
sc_time RefreshManagerBankwise::start()
{
timeToSchedule = SC_ZERO_TIME;
timeToSchedule = sc_max_time();
if (sc_time_stamp() >= timeForNextTrigger)
{
if (sc_time_stamp() >= timeForNextTrigger + memSpec->getRefreshIntervalPB())

4
DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h
View File

@@ -58,8 +58,8 @@ private:
const MemSpec *memSpec;
std::vector<BankMachine *> bankMachines;
std::vector<tlm_generic_payload> refreshPayloads;
sc_time timeForNextTrigger;
sc_time timeToSchedule = SC_ZERO_TIME;
sc_time timeForNextTrigger = sc_max_time();
sc_time timeToSchedule = sc_max_time();
Rank rank;
CheckerIF *checker;
Command nextCommand;

1
DRAMSys/library/src/simulation/StlPlayer.h
View File

@@ -89,6 +89,7 @@ public:
}
// Allocate a generic payload for this request.
gp *payload = this->allocatePayload();
payload->acquire();
unsigned char *data = payload->get_data_ptr();
// Trace files MUST provide timestamp, command and address for every

2
DRAMSys/library/src/simulation/TraceGenerator.h
View File

@@ -64,7 +64,7 @@ public:
}
gp *payload = this->allocatePayload();
payload->acquire();
unsigned char *dataElement = new unsigned
char[16]; // TODO: column / burst breite

4
DRAMSys/library/src/simulation/TracePlayer.cpp
View File

@@ -77,16 +77,14 @@ void TracePlayer::peqCallback(tlm_generic_payload &payload,
const tlm_phase &phase)
{
if (phase == BEGIN_REQ) {
payload.acquire();
sendToTarget(payload, phase, SC_ZERO_TIME);
transactionsSent++;
PRINTDEBUGMESSAGE(name(), "Performing request #" + std::to_string(transactionsSent));
} else if (phase == END_REQ) {
nextPayload();
} else if (phase == BEGIN_RESP) {
sendToTarget(payload, END_RESP, SC_ZERO_TIME);
payload.release();
sendToTarget(payload, END_RESP, SC_ZERO_TIME);
if (Configuration::getInstance().SimulationProgressBar)
listener->transactionFinished();