derek/DRAMSys
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Removed unused commands and extended protocol phases.

Browse Source
This commit is contained in:
Lukas Steiner (2)
2019-08-20 09:51:55 +02:00
parent cbeaef32de
commit baa976dac4
7 changed files with 12 additions and 109 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
DRAMSys/library/src/common/TlmRecorder.cpp
View File

@@ -249,10 +249,6 @@ void TlmRecorder::setUpTransactionTerminatingPhases()
// Refresh Bank
transactionTerminatingPhases.push_back(static_cast<const tlm::tlm_phase>
(END_REFB));
transactionTerminatingPhases.push_back(static_cast<const tlm::tlm_phase>
(END_ACTB));
transactionTerminatingPhases.push_back(static_cast<const tlm::tlm_phase>
(END_PREB));
// Phases for Power Down
transactionTerminatingPhases.push_back(static_cast<const tlm::tlm_phase>

17
DRAMSys/library/src/common/protocol.h
View File

@@ -39,17 +39,11 @@
#define PROTOCOL_H
// DRAM Control Phases
DECLARE_EXTENDED_PHASE(BEGIN_PREB);
DECLARE_EXTENDED_PHASE(END_PREB);
DECLARE_EXTENDED_PHASE(BEGIN_PRE);
DECLARE_EXTENDED_PHASE(END_PRE);
DECLARE_EXTENDED_PHASE(BEGIN_PRE_ALL);
DECLARE_EXTENDED_PHASE(END_PRE_ALL);
DECLARE_EXTENDED_PHASE(BEGIN_ACTB);
DECLARE_EXTENDED_PHASE(END_ACTB);
DECLARE_EXTENDED_PHASE(BEGIN_PREA);
DECLARE_EXTENDED_PHASE(END_PREA);
DECLARE_EXTENDED_PHASE(BEGIN_ACT);
DECLARE_EXTENDED_PHASE(END_ACT);
@@ -60,7 +54,6 @@ DECLARE_EXTENDED_PHASE(END_REFA);
DECLARE_EXTENDED_PHASE(BEGIN_REFB);
DECLARE_EXTENDED_PHASE(END_REFB);
// Phases for Read and Write
DECLARE_EXTENDED_PHASE(BEGIN_WR);
DECLARE_EXTENDED_PHASE(END_WR);
@@ -94,11 +87,5 @@ DECLARE_EXTENDED_PHASE(END_PDNAB);
DECLARE_EXTENDED_PHASE(BEGIN_SREFB);
DECLARE_EXTENDED_PHASE(END_SREFB);
//Triggers
DECLARE_EXTENDED_PHASE(REF_TRIGGER);
DECLARE_EXTENDED_PHASE(PDN_TRIGGER);
#endif // PROTOCOL_H

10
DRAMSys/library/src/controller/Command.cpp
View File

@@ -54,15 +54,9 @@ std::string commandToString(Command command)
case Command::WRA:
return "WRA";
break;
case Command::PREB:
return "PREB";
break;
case Command::PRE:
return "PRE";
break;
case Command::ACTB:
return "ACTB";
break;
case Command::ACT:
return "ACT";
break;
@@ -108,10 +102,8 @@ std::string commandToString(Command command)
const std::vector<Command> &getAllCommands()
{
static std::vector<Command> allCommands( { Command::PREB,
Command::PRE,
static std::vector<Command> allCommands( { Command::PRE,
Command::PREA,
Command::ACTB,
Command::ACT,
Command::RD,
Command::WR,

5
DRAMSys/library/src/controller/Command.h
View File

@@ -39,12 +39,11 @@
#include <string>
#include <vector>
enum class Command {
enum class Command
{
NOP,
PREB,
PRE,
PREA,
ACTB,
ACT,
RD,
WR,

2
DRAMSys/library/src/controller/ControllerNew.cpp
View File

@@ -269,7 +269,7 @@ void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload)
else if (command == Command::WR)
phase = BEGIN_WR;
else if (command == Command::PREA)
phase = BEGIN_PRE_ALL;
phase = BEGIN_PREA;
else if (command == Command::REFA)
phase = BEGIN_REFA;
else if (command == Command::REFB)

40
DRAMSys/library/src/simulation/Dram.cpp
View File

@@ -108,27 +108,17 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,
// This is only needed for power simulation:
unsigned long long cycle = sc_time_stamp().value() / memSpec->clk.value();
if (phase == BEGIN_PREB)
{
DRAMPower->doCommand(MemCommand::PREB, bank, cycle);
sendToController(payload, END_PREB, delay + memSpec->getExecutionTime(Command::PREB));
}
else if (phase == BEGIN_PRE)
if (phase == BEGIN_PRE)
{
DRAMPower->doCommand(MemCommand::PRE, bank, cycle);
sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::PRE));
}
else if (phase == BEGIN_PRE_ALL)
else if (phase == BEGIN_PREA)
{
DRAMPower->doCommand(MemCommand::PREA, bank, cycle);
sendToController(payload, END_PRE_ALL,
sendToController(payload, END_PREA,
delay + memSpec->getExecutionTime(Command::PREA));
}
else if (phase == BEGIN_ACTB)
{
DRAMPower->doCommand(MemCommand::ACTB, bank, cycle);
sendToController(payload, END_ACTB, delay + memSpec->getExecutionTime(Command::ACTB));
}
else if (phase == BEGIN_ACT)
{
DRAMPower->doCommand(MemCommand::ACT, bank, cycle);
@@ -199,14 +189,6 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,
{
DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle);
}
else if (phase == BEGIN_PDNAB)
{
SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported");
}
else if (phase == END_PDNAB)
{
SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported");
}
else if (phase == BEGIN_PDNP)
{
DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle);
@@ -215,14 +197,6 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,
{
DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle);
}
else if (phase == BEGIN_PDNPB)
{
SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported");
}
else if (phase == END_PDNPB)
{
SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported");
}
else if (phase == BEGIN_SREF)
{
DRAMPower->doCommand(MemCommand::SREN, bank, cycle);
@@ -231,14 +205,6 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,
{
DRAMPower->doCommand(MemCommand::SREX, bank, cycle);
}
else if (phase == BEGIN_SREFB)
{
SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported");
}
else if (phase == END_SREFB)
{
SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported");
}
else
{
SC_REPORT_FATAL("DRAM", "DRAM PEQ was called with unknown phase");

43
DRAMSys/library/src/simulation/DramWideIO.cpp
View File

@@ -183,30 +183,17 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload,
// This is only needed for power simulation:
unsigned long long cycle = sc_time_stamp().value() / memSpec->clk.value();
if (phase == BEGIN_PREB)
{
DRAMPower->doCommand(MemCommand::PREB, bank, cycle);
sendToController(payload, END_PREB, delay + memSpec->getExecutionTime(Command::PREB));
}
else if (phase == BEGIN_PRE)
if (phase == BEGIN_PRE)
{
DRAMPower->doCommand(MemCommand::PRE, bank, cycle);
sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::PRE));
}
else if (phase == BEGIN_PRE_ALL)
else if (phase == BEGIN_PREA)
{
DRAMPower->doCommand(MemCommand::PREA, bank, cycle);
sendToController(payload, END_PRE_ALL,
sendToController(payload, END_PREA,
delay + memSpec->getExecutionTime(Command::PREA));
}
else if (phase == BEGIN_ACTB)
{
DRAMPower->doCommand(MemCommand::ACTB, bank, cycle);
sendToController(payload, END_ACTB, delay + memSpec->getExecutionTime(Command::ACTB));
unsigned int row = DramExtension::getExtension(payload).getRow().ID();
if (StoreMode == StorageMode::ErrorModel)
ememory[bank]->activate(row);
}
else if (phase == BEGIN_ACT)
{
DRAMPower->doCommand(MemCommand::ACT, bank, cycle);
@@ -301,14 +288,6 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload,
{
DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle);
}
else if (phase == BEGIN_PDNAB)
{
SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported");
}
else if (phase == END_PDNAB)
{
SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported");
}
else if (phase == BEGIN_PDNP)
{
DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle);
@@ -317,14 +296,6 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload,
{
DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle);
}
else if (phase == BEGIN_PDNPB)
{
SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported");
}
else if (phase == END_PDNPB)
{
SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported");
}
else if (phase == BEGIN_SREF)
{
DRAMPower->doCommand(MemCommand::SREN, bank, cycle);
@@ -333,14 +304,6 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload,
{
DRAMPower->doCommand(MemCommand::SREX, bank, cycle);
}
else if (phase == BEGIN_SREFB)
{
SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported");
}
else if (phase == END_SREFB)
{
SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported");
}
else
{
SC_REPORT_FATAL("DRAM", "DRAM PEQ was called with unknown phase");