From baa976dac400cd9ba838fa4b2c383c02258955c5 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 20 Aug 2019 09:51:55 +0200 Subject: [PATCH] Removed unused commands and extended protocol phases. --- DRAMSys/library/src/common/TlmRecorder.cpp | 4 -- DRAMSys/library/src/common/protocol.h | 17 +------- DRAMSys/library/src/controller/Command.cpp | 10 +---- DRAMSys/library/src/controller/Command.h | 5 +-- .../library/src/controller/ControllerNew.cpp | 2 +- DRAMSys/library/src/simulation/Dram.cpp | 40 ++--------------- DRAMSys/library/src/simulation/DramWideIO.cpp | 43 ++----------------- 7 files changed, 12 insertions(+), 109 deletions(-) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index fe9b056e..af1327e5 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -249,10 +249,6 @@ void TlmRecorder::setUpTransactionTerminatingPhases() // Refresh Bank transactionTerminatingPhases.push_back(static_cast (END_REFB)); - transactionTerminatingPhases.push_back(static_cast - (END_ACTB)); - transactionTerminatingPhases.push_back(static_cast - (END_PREB)); // Phases for Power Down transactionTerminatingPhases.push_back(static_cast diff --git a/DRAMSys/library/src/common/protocol.h b/DRAMSys/library/src/common/protocol.h index 06af9c30..986ef847 100644 --- a/DRAMSys/library/src/common/protocol.h +++ b/DRAMSys/library/src/common/protocol.h @@ -39,17 +39,11 @@ #define PROTOCOL_H // DRAM Control Phases -DECLARE_EXTENDED_PHASE(BEGIN_PREB); -DECLARE_EXTENDED_PHASE(END_PREB); - DECLARE_EXTENDED_PHASE(BEGIN_PRE); DECLARE_EXTENDED_PHASE(END_PRE); -DECLARE_EXTENDED_PHASE(BEGIN_PRE_ALL); -DECLARE_EXTENDED_PHASE(END_PRE_ALL); - -DECLARE_EXTENDED_PHASE(BEGIN_ACTB); -DECLARE_EXTENDED_PHASE(END_ACTB); +DECLARE_EXTENDED_PHASE(BEGIN_PREA); +DECLARE_EXTENDED_PHASE(END_PREA); DECLARE_EXTENDED_PHASE(BEGIN_ACT); DECLARE_EXTENDED_PHASE(END_ACT); @@ -60,7 +54,6 @@ DECLARE_EXTENDED_PHASE(END_REFA); DECLARE_EXTENDED_PHASE(BEGIN_REFB); DECLARE_EXTENDED_PHASE(END_REFB); - // Phases for Read and Write DECLARE_EXTENDED_PHASE(BEGIN_WR); DECLARE_EXTENDED_PHASE(END_WR); @@ -94,11 +87,5 @@ DECLARE_EXTENDED_PHASE(END_PDNAB); DECLARE_EXTENDED_PHASE(BEGIN_SREFB); DECLARE_EXTENDED_PHASE(END_SREFB); - -//Triggers -DECLARE_EXTENDED_PHASE(REF_TRIGGER); -DECLARE_EXTENDED_PHASE(PDN_TRIGGER); - - #endif // PROTOCOL_H diff --git a/DRAMSys/library/src/controller/Command.cpp b/DRAMSys/library/src/controller/Command.cpp index bfef86c0..6259afe8 100644 --- a/DRAMSys/library/src/controller/Command.cpp +++ b/DRAMSys/library/src/controller/Command.cpp @@ -54,15 +54,9 @@ std::string commandToString(Command command) case Command::WRA: return "WRA"; break; - case Command::PREB: - return "PREB"; - break; case Command::PRE: return "PRE"; break; - case Command::ACTB: - return "ACTB"; - break; case Command::ACT: return "ACT"; break; @@ -108,10 +102,8 @@ std::string commandToString(Command command) const std::vector &getAllCommands() { - static std::vector allCommands( { Command::PREB, - Command::PRE, + static std::vector allCommands( { Command::PRE, Command::PREA, - Command::ACTB, Command::ACT, Command::RD, Command::WR, diff --git a/DRAMSys/library/src/controller/Command.h b/DRAMSys/library/src/controller/Command.h index c51c2a67..5ffa8c8c 100644 --- a/DRAMSys/library/src/controller/Command.h +++ b/DRAMSys/library/src/controller/Command.h @@ -39,12 +39,11 @@ #include #include -enum class Command { +enum class Command +{ NOP, - PREB, PRE, PREA, - ACTB, ACT, RD, WR, diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index e20139a0..4e7290b4 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -269,7 +269,7 @@ void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload) else if (command == Command::WR) phase = BEGIN_WR; else if (command == Command::PREA) - phase = BEGIN_PRE_ALL; + phase = BEGIN_PREA; else if (command == Command::REFA) phase = BEGIN_REFA; else if (command == Command::REFB) diff --git a/DRAMSys/library/src/simulation/Dram.cpp b/DRAMSys/library/src/simulation/Dram.cpp index 77dac5ca..092221c3 100644 --- a/DRAMSys/library/src/simulation/Dram.cpp +++ b/DRAMSys/library/src/simulation/Dram.cpp @@ -108,27 +108,17 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, // This is only needed for power simulation: unsigned long long cycle = sc_time_stamp().value() / memSpec->clk.value(); - if (phase == BEGIN_PREB) - { - DRAMPower->doCommand(MemCommand::PREB, bank, cycle); - sendToController(payload, END_PREB, delay + memSpec->getExecutionTime(Command::PREB)); - } - else if (phase == BEGIN_PRE) + if (phase == BEGIN_PRE) { DRAMPower->doCommand(MemCommand::PRE, bank, cycle); sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::PRE)); } - else if (phase == BEGIN_PRE_ALL) + else if (phase == BEGIN_PREA) { DRAMPower->doCommand(MemCommand::PREA, bank, cycle); - sendToController(payload, END_PRE_ALL, + sendToController(payload, END_PREA, delay + memSpec->getExecutionTime(Command::PREA)); } - else if (phase == BEGIN_ACTB) - { - DRAMPower->doCommand(MemCommand::ACTB, bank, cycle); - sendToController(payload, END_ACTB, delay + memSpec->getExecutionTime(Command::ACTB)); - } else if (phase == BEGIN_ACT) { DRAMPower->doCommand(MemCommand::ACT, bank, cycle); @@ -199,14 +189,6 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, { DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle); } - else if (phase == BEGIN_PDNAB) - { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } - else if (phase == END_PDNAB) - { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } else if (phase == BEGIN_PDNP) { DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle); @@ -215,14 +197,6 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, { DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle); } - else if (phase == BEGIN_PDNPB) - { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } - else if (phase == END_PDNPB) - { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } else if (phase == BEGIN_SREF) { DRAMPower->doCommand(MemCommand::SREN, bank, cycle); @@ -231,14 +205,6 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, { DRAMPower->doCommand(MemCommand::SREX, bank, cycle); } - else if (phase == BEGIN_SREFB) - { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } - else if (phase == END_SREFB) - { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } else { SC_REPORT_FATAL("DRAM", "DRAM PEQ was called with unknown phase"); diff --git a/DRAMSys/library/src/simulation/DramWideIO.cpp b/DRAMSys/library/src/simulation/DramWideIO.cpp index 896f32e8..37c4efa0 100644 --- a/DRAMSys/library/src/simulation/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/DramWideIO.cpp @@ -183,30 +183,17 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, // This is only needed for power simulation: unsigned long long cycle = sc_time_stamp().value() / memSpec->clk.value(); - if (phase == BEGIN_PREB) - { - DRAMPower->doCommand(MemCommand::PREB, bank, cycle); - sendToController(payload, END_PREB, delay + memSpec->getExecutionTime(Command::PREB)); - } - else if (phase == BEGIN_PRE) + if (phase == BEGIN_PRE) { DRAMPower->doCommand(MemCommand::PRE, bank, cycle); sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::PRE)); } - else if (phase == BEGIN_PRE_ALL) + else if (phase == BEGIN_PREA) { DRAMPower->doCommand(MemCommand::PREA, bank, cycle); - sendToController(payload, END_PRE_ALL, + sendToController(payload, END_PREA, delay + memSpec->getExecutionTime(Command::PREA)); } - else if (phase == BEGIN_ACTB) - { - DRAMPower->doCommand(MemCommand::ACTB, bank, cycle); - sendToController(payload, END_ACTB, delay + memSpec->getExecutionTime(Command::ACTB)); - unsigned int row = DramExtension::getExtension(payload).getRow().ID(); - if (StoreMode == StorageMode::ErrorModel) - ememory[bank]->activate(row); - } else if (phase == BEGIN_ACT) { DRAMPower->doCommand(MemCommand::ACT, bank, cycle); @@ -301,14 +288,6 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle); } - else if (phase == BEGIN_PDNAB) - { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } - else if (phase == END_PDNAB) - { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } else if (phase == BEGIN_PDNP) { DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle); @@ -317,14 +296,6 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle); } - else if (phase == BEGIN_PDNPB) - { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } - else if (phase == END_PDNPB) - { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } else if (phase == BEGIN_SREF) { DRAMPower->doCommand(MemCommand::SREN, bank, cycle); @@ -333,14 +304,6 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { DRAMPower->doCommand(MemCommand::SREX, bank, cycle); } - else if (phase == BEGIN_SREFB) - { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } - else if (phase == END_SREFB) - { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } else { SC_REPORT_FATAL("DRAM", "DRAM PEQ was called with unknown phase");