derek/DRAMSys
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Included ControllerRecordable for disabling of trace recording.

Browse Source
This commit is contained in:
Lukas Steiner (2)
2019-07-29 16:44:14 +02:00
parent 91755962a2
commit 4fa59c2410
6 changed files with 135 additions and 62 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
DRAMSys/library/library.pro
View File

@@ -155,7 +155,8 @@ SOURCES += \
src/controller/scheduler/SchedulerFifo.cpp \
src/controller/scheduler/SchedulerFrFcfs.cpp \
src/controller/cmdmux/CmdMuxStrict.cpp \
src/controller/cmdmux/CmdMuxOldest.cpp
src/controller/cmdmux/CmdMuxOldest.cpp \
src/controller/ControllerRecordable.cpp
HEADERS += \
src/common/third_party/tinyxml2/tinyxml2.h \
@@ -246,7 +247,8 @@ HEADERS += \
src/controller/scheduler/SchedulerFrFcfs.h \
src/controller/cmdmux/CmdMuxIF.h \
src/controller/cmdmux/CmdMuxStrict.h \
src/controller/cmdmux/CmdMuxOldest.h
src/controller/cmdmux/CmdMuxOldest.h \
src/controller/ControllerRecordable.h
#src/common/third_party/json/include/nlohmann/json.hpp \
thermalsim = $$(THERMALSIM)

51
DRAMSys/library/src/controller/ControllerNew.cpp
View File

@@ -8,8 +8,8 @@
#include "../common/protocol.h"
#include "core/scheduling/ScheduledCommand.h"
ControllerNew::ControllerNew(sc_module_name name, TlmRecorder *tlmRecorder) :
sc_module(name), tlmRecorder(tlmRecorder), debugManager(&DebugManager::getInstance())
ControllerNew::ControllerNew(sc_module_name name) :
sc_module(name), debugManager(&DebugManager::getInstance())
{
SC_METHOD(controllerMethod);
sensitive << triggerEvent << triggerEventQueue;
@@ -43,7 +43,6 @@ ControllerNew::~ControllerNew()
tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans,
tlm_phase &phase, sc_time &delay)
{
recordPhase(trans, phase, delay);
sc_time notificationDelay = delay;
if (phase == BEGIN_REQ)
@@ -70,7 +69,6 @@ tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans,
tlm_sync_enum ControllerNew::nb_transport_bw(tlm_generic_payload &trans,
tlm_phase &phase, sc_time &delay)
{
recordPhase(trans, phase, delay);
printDebugMessage("[bw] " + phaseNameToString(phase) + " notification in " +
delay.to_string());
Bank bank = DramExtension::getExtension(trans).getBank();
@@ -90,26 +88,6 @@ void ControllerNew::printDebugMessage(string message)
debugManager->printDebugMessage(name(), message);
}
void ControllerNew::recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay)
{
sc_time recTime = delay + sc_time_stamp();
unsigned int thr = DramExtension::getExtension(trans).getThread().ID();
unsigned int ch = DramExtension::getExtension(trans).getChannel().ID();
unsigned int bg = DramExtension::getExtension(trans).getBankGroup().ID();
unsigned int bank = DramExtension::getExtension(trans).getBank().ID();
unsigned int row = DramExtension::getExtension(trans).getRow().ID();
unsigned int col = DramExtension::getExtension(trans).getColumn().ID();
unsigned int id = DramExtension::getExtension(trans).getPayloadID();
printDebugMessage("Recording " + phaseNameToString(phase) + " thread " +
to_string(thr) + " channel " + to_string(ch) + " bank group " + to_string(
bg) + " bank " + to_string(bank) + " row " + to_string(row) + " column " +
to_string(col) + " id " + to_string(id) + " at " + recTime.to_string());
tlmRecorder->recordPhase(trans, phase, recTime);
}
void ControllerNew::triggerEventAfterDelay(sc_time delay)
{
if (delay != SC_ZERO_TIME)
@@ -155,7 +133,10 @@ void ControllerNew::controllerMethod()
// (4) Send result to arbiter
if (payloadToRelease == nullptr && !responseQueue.empty())
sendToFrontend();
{
payloadToRelease = responseQueue.front();
sendToFrontend(payloadToRelease, BEGIN_RESP);
}
// (5) Start bank machines to issue new requests for current time
for (auto it : bankMachines)
@@ -207,21 +188,15 @@ void ControllerNew::acquirePayload()
numberOfPayloads++;
payloadToAcquire->set_response_status(TLM_OK_RESPONSE);
tlm_phase tPhase = END_REQ;
sc_time tDelay = SC_ZERO_TIME;
recordPhase(*payloadToAcquire, tPhase, tDelay);
tSocket->nb_transport_bw(*payloadToAcquire, tPhase, tDelay);
sendToFrontend(payloadToAcquire, END_REQ);
payloadToAcquire = nullptr;
}
void ControllerNew::sendToFrontend()
void ControllerNew::sendToFrontend(tlm_generic_payload *payload, tlm_phase phase)
{
payloadToRelease = responseQueue.front();
tlm_phase tPhase = BEGIN_RESP;
sc_time tDelay = SC_ZERO_TIME;
recordPhase(*payloadToRelease, tPhase, tDelay);
tSocket->nb_transport_bw(*payloadToRelease, tPhase, tDelay);
sc_time delay = SC_ZERO_TIME;
tSocket->nb_transport_bw(*payload, phase, delay);
}
void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload)
@@ -242,16 +217,10 @@ void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload)
else if (command == Command::RD)
{
phase = BEGIN_RD;
ScheduledCommand scheduledCommand = state->getLastCommandOnBank(command, bank);
TimeInterval dataStrobe = scheduledCommand.getIntervalOnDataStrobe();
tlmRecorder->updateDataStrobe(dataStrobe.start, dataStrobe.end, *payload);
}
else if (command == Command::WR)
{
phase = BEGIN_WR;
ScheduledCommand scheduledCommand = state->getLastCommandOnBank(command, bank);
TimeInterval dataStrobe = scheduledCommand.getIntervalOnDataStrobe();
tlmRecorder->updateDataStrobe(dataStrobe.start, dataStrobe.end, *payload);
}
else
SC_REPORT_FATAL("ControllerNew", "Unknown phase");

21
DRAMSys/library/src/controller/ControllerNew.h
View File

@@ -12,7 +12,6 @@
#include "BankMachine.h"
#include "cmdmux/CmdMuxIF.h"
#include "scheduler/SchedulerIF.h"
#include "../common/TlmRecorder.h"
#include "../common/DebugManager.h"
#include "core/scheduling/checker/CheckerDDR3New.h"
#include "ControllerState.h"
@@ -25,23 +24,26 @@ class SchedulerIF;
class ControllerNew : public sc_module
{
public:
ControllerNew(sc_module_name, TlmRecorder *);
ControllerNew(sc_module_name);
SC_HAS_PROCESS(ControllerNew);
~ControllerNew();
virtual ~ControllerNew();
tlm_utils::simple_target_socket<ControllerNew> tSocket;
tlm_utils::simple_initiator_socket<ControllerNew> iSocket;
private:
tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans,
protected:
virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans,
tlm_phase &phase, sc_time &delay);
tlm_sync_enum nb_transport_bw(tlm_generic_payload &trans,
virtual tlm_sync_enum nb_transport_bw(tlm_generic_payload &trans,
tlm_phase &phase, sc_time &delay);
unsigned int transport_dbg(tlm_generic_payload &);
virtual unsigned int transport_dbg(tlm_generic_payload &);
virtual void sendToFrontend(tlm_generic_payload *, tlm_phase);
virtual void sendToDram(Command, tlm_generic_payload *);
void printDebugMessage(string message);
void recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay);
//private:
unsigned numberOfPayloads = 0;
tlm_generic_payload *payloadToAcquire = nullptr;
sc_time timeToAcquire = SC_ZERO_TIME;
@@ -49,7 +51,6 @@ private:
sc_time timeToRelease = SC_ZERO_TIME;
std::queue<tlm_generic_payload *> responseQueue;
TlmRecorder *tlmRecorder;
DebugManager *debugManager;
ControllerState *state;
@@ -60,8 +61,6 @@ private:
void releasePayload();
void acquirePayload();
void sendToFrontend();
void sendToDram(Command, tlm_generic_payload *);
void controllerMethod();
sc_event triggerEvent;

78
DRAMSys/library/src/controller/ControllerRecordable.cpp Normal file
View File

@@ -0,0 +1,78 @@
#include "ControllerRecordable.h"
#include "../common/protocol.h"
tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload &trans,
tlm_phase &phase, sc_time &delay)
{
recordPhase(trans, phase, delay);
return ControllerNew::nb_transport_fw(trans, phase, delay);
}
tlm_sync_enum ControllerRecordable::nb_transport_bw(tlm_generic_payload &trans,
tlm_phase &phase, sc_time &delay)
{
recordPhase(trans, phase, delay);
return ControllerNew::nb_transport_bw(trans, phase, delay);
}
void ControllerRecordable::sendToFrontend(tlm_generic_payload *payload, tlm_phase phase)
{
sc_time delay = SC_ZERO_TIME;
recordPhase(*payload, phase, delay);
tSocket->nb_transport_bw(*payload, phase, delay);
}
// TODO: call ControllerNew::sendToDram
void ControllerRecordable::sendToDram(Command command, tlm_generic_payload *payload)
{
sc_time execTime = Configuration::getInstance().memSpec->getExecutionTime(command, *payload);
ScheduledCommand scheduledCommand(command, sc_time_stamp(), execTime, *payload);
state->cleanUp(sc_time_stamp());
state->change(scheduledCommand);
Bank bank = scheduledCommand.getBank();
bankMachines[bank]->updateState(command);
sc_time delay = SC_ZERO_TIME;
tlm_phase phase;
if (command == Command::ACT)
phase = BEGIN_ACT;
else if (command == Command::PRE)
phase = BEGIN_PRE;
else if (command == Command::RD)
{
phase = BEGIN_RD;
ScheduledCommand scheduledCommand = state->getLastCommandOnBank(command, bank);
TimeInterval dataStrobe = scheduledCommand.getIntervalOnDataStrobe();
tlmRecorder->updateDataStrobe(dataStrobe.start, dataStrobe.end, *payload);
}
else if (command == Command::WR)
{
phase = BEGIN_WR;
ScheduledCommand scheduledCommand = state->getLastCommandOnBank(command, bank);
TimeInterval dataStrobe = scheduledCommand.getIntervalOnDataStrobe();
tlmRecorder->updateDataStrobe(dataStrobe.start, dataStrobe.end, *payload);
}
else
SC_REPORT_FATAL("ControllerNew", "Unknown phase");
iSocket->nb_transport_fw(*payload, phase, delay);
}
void ControllerRecordable::recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay)
{
sc_time recTime = delay + sc_time_stamp();
unsigned int thr = DramExtension::getExtension(trans).getThread().ID();
unsigned int ch = DramExtension::getExtension(trans).getChannel().ID();
unsigned int bg = DramExtension::getExtension(trans).getBankGroup().ID();
unsigned int bank = DramExtension::getExtension(trans).getBank().ID();
unsigned int row = DramExtension::getExtension(trans).getRow().ID();
unsigned int col = DramExtension::getExtension(trans).getColumn().ID();
unsigned int id = DramExtension::getExtension(trans).getPayloadID();
printDebugMessage("Recording " + phaseNameToString(phase) + " thread " +
to_string(thr) + " channel " + to_string(ch) + " bank group " + to_string(
bg) + " bank " + to_string(bank) + " row " + to_string(row) + " column " +
to_string(col) + " id " + to_string(id) + " at " + recTime.to_string());
tlmRecorder->recordPhase(trans, phase, recTime);
}

27
DRAMSys/library/src/controller/ControllerRecordable.h Normal file
View File

@@ -0,0 +1,27 @@
#ifndef CONTROLLERRECORDABLE_H
#define CONTROLLERRECORDABLE_H
#include "ControllerNew.h"
#include "../common/TlmRecorder.h"
class ControllerRecordable final : public ControllerNew
{
public:
ControllerRecordable(sc_module_name name, TlmRecorder *tlmRecorder) :
ControllerNew(name), tlmRecorder(tlmRecorder) {}
private:
tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans,
tlm_phase &phase, sc_time &delay) override;
tlm_sync_enum nb_transport_bw(tlm_generic_payload &trans,
tlm_phase &phase, sc_time &delay) override;
void sendToFrontend(tlm_generic_payload *, tlm_phase) override;
void sendToDram(Command, tlm_generic_payload *) override;
void recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay);
TlmRecorder *tlmRecorder;
};
#endif // CONTROLLERRECORDABLE_H

14
DRAMSys/library/src/simulation/DRAMSys.cpp
View File

@@ -59,6 +59,7 @@
#include "DramDDR4.h"
#include "DramWideIO.h"
#include "../controller/ControllerNew.h"
#include "../controller/ControllerRecordable.h"
using namespace std;
@@ -252,14 +253,11 @@ void DRAMSys::instantiateModules(const string &traceName,
{
std::string str = "controller" + std::to_string(i);
// GenericController *controller;
// if (recordingEnabled)
// controller = new RecordableController(str.c_str(), tlmRecorders[i]);
// else
// controller = new Controller(str.c_str());
// controllers.push_back(controller);
ControllerNew *controller = new ControllerNew(str.c_str(), tlmRecorders[i]);
ControllerNew *controller;
if (recordingEnabled)
controller = new ControllerRecordable(str.c_str(), tlmRecorders[i]);
else
controller = new ControllerNew(str.c_str());
newControllers.push_back(controller);
str = "dram" + std::to_string(i);