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Included MemSpecWideIO2, some adaptions for all memspecs.

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This commit is contained in:
Lukas Steiner (2)
2019-10-08 14:14:42 +02:00
parent 932027112e
commit 65db413a20
17 changed files with 386 additions and 228 deletions
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11
DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.xml Normal file
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@@ -0,0 +1,11 @@
<!-- Row Bank Column -->
<addressmapping>
<channel from="28" to="29" />
<bank from="25" to="27" />
<row from="12" to="24" />
<column from="3" to="11" />
<bytes from="0" to="2" />
</addressmapping>
<!-- Bank Row Column -->

8
DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.xml
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@@ -2,10 +2,10 @@
<addressmapping>
<channel from="28" to="29" />
<row from="15" to="27" />
<bank from="12" to="14" />
<column from="3" to="11" />
<bytes from="0" to="2" />
<row from="15" to="27" />
<bank from="12" to="14" />
<column from="3" to="11" />
<bytes from="0" to="2" />
</addressmapping>
<!-- Bank Row Column -->

3
DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.xml
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@@ -21,7 +21,8 @@
<parameter id="RFC" type="uint" value="18" />
<parameter id="RAS" type="uint" value="9" />
<parameter id="WL" type="uint" value="1" />
<parameter id="DQSCK" type="uint" value="1" />
<parameter id="DQSCK" type="uint" value="1" />
<parameter id="AC" type="uint" value="1" />
<parameter id="WR" type="uint" value="3" />
<parameter id="XP" type="uint" value="2" />
<parameter id="XS" type="uint" value="20" />

3
DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.xml
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@@ -21,7 +21,8 @@
<parameter id="RFC" type="uint" value="24" />
<parameter id="RAS" type="uint" value="12" />
<parameter id="WL" type="uint" value="1" />
<parameter id="DQSCK" type="uint" value="1" />
<parameter id="DQSCK" type="uint" value="1" />
<parameter id="AC" type="uint" value="1" />
<parameter id="WR" type="uint" value="4" />
<parameter id="XP" type="uint" value="3" />
<parameter id="XS" type="uint" value="27" />

71
DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.xml
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@@ -13,54 +13,31 @@
<parameter id="burstLength" type="uint" value="4" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="400" />
<parameter id="RCD" type="uint" value="8" />
<parameter id="RPPB" type="uint" value="8" />
<parameter id="RPAB" type="uint" value="9" />
<parameter id="RAS" type="uint" value="17" />
<parameter id="RCPB" type="uint" value="24" />
<parameter id="RCAB" type="uint" value="26" />
<parameter id="WTR" type="uint" value="4" />
<parameter id="RRD" type="uint" value="4" />
<parameter id="FAW" type="uint" value="24" />
<parameter id="CKE" type="uint" value="3" />
<parameter id="REFM" type="uint" value="1" />
<parameter id="REFI" type="uint" value="1560" />
<parameter id="RFCAB" type="uint" value="72" />
<parameter id="RFCPB" type="uint" value="36" />
<parameter id="CKESR" type="uint" value="6" />
<parameter id="XS" type="uint" value="76" />
<parameter id="XP" type="uint" value="3" />
<parameter id="RL" type="uint" value="7" />
<parameter id="WL" type="uint" value="5" />
<parameter id="WR" type="uint" value="8" />
<parameter id="RTP" type="uint" value="3" />
<parameter id="CCD" type="uint" value="2" />
<parameter id="clkMhz" type="double" value="400" />
<parameter id="RCD" type="uint" value="8" />
<parameter id="RPPB" type="uint" value="8" />
<parameter id="RPAB" type="uint" value="9" />
<parameter id="RAS" type="uint" value="17" />
<parameter id="RCPB" type="uint" value="24" />
<parameter id="RCAB" type="uint" value="26" />
<parameter id="WTR" type="uint" value="4" />
<parameter id="RRD" type="uint" value="4" />
<parameter id="FAW" type="uint" value="24" />
<parameter id="CKE" type="uint" value="3" />
<parameter id="REFM" type="uint" value="1" />
<parameter id="REFI" type="uint" value="1560" />
<parameter id="RFCAB" type="uint" value="72" />
<parameter id="RFCPB" type="uint" value="36" />
<parameter id="CKESR" type="uint" value="6" />
<parameter id="XS" type="uint" value="76" />
<parameter id="XP" type="uint" value="3" />
<parameter id="RL" type="uint" value="7" />
<parameter id="WL" type="uint" value="5" />
<parameter id="WR" type="uint" value="8" />
<parameter id="RTP" type="uint" value="3" />
<parameter id="CCD" type="uint" value="2" />
</memtimingspec>
<mempowerspec>
<parameter id="idd0" type="double" value="5.88" />
<parameter id="idd02" type="double" value="21.18" />
<parameter id="idd2p0" type="double" value="0.05" />
<parameter id="idd2p02" type="double" value="0.17" />
<parameter id="idd2p1" type="double" value="0.05" />
<parameter id="idd2p12" type="double" value="0.17" />
<parameter id="idd2n" type="double" value="0.13" />
<parameter id="idd2n2" type="double" value="4.04" />
<parameter id="idd3p0" type="double" value="0.25" />
<parameter id="idd3p02" type="double" value="1.49" />
<parameter id="idd3p1" type="double" value="0.25" />
<parameter id="idd3p12" type="double" value="1.49" />
<parameter id="idd3n" type="double" value="0.52" />
<parameter id="idd3n2" type="double" value="6.55" />
<parameter id="idd4r" type="double" value="1.41" />
<parameter id="idd4r2" type="double" value="85.73" />
<parameter id="idd4w" type="double" value="1.42" />
<parameter id="idd4w2" type="double" value="60.79" />
<parameter id="idd5" type="double" value="14.43" />
<parameter id="idd52" type="double" value="48.17" />
<parameter id="idd6" type="double" value="0.07" />
<parameter id="idd62" type="double" value="0.27" />
<parameter id="vdd" type="double" value="1.8" />
<parameter id="vdd2" type="double" value="1.2" />
<!-- to be completed -->
</mempowerspec>
</memspec>

71
DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.xml
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@@ -13,54 +13,31 @@
<parameter id="burstLength" type="uint" value="4" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="533" />
<parameter id="RCD" type="uint" value="10" />
<parameter id="RPPB" type="uint" value="10" />
<parameter id="RPAB" type="uint" value="12" />
<parameter id="RAS" type="uint" value="23" />
<parameter id="RCPB" type="uint" value="32" />
<parameter id="RCAB" type="uint" value="34" />
<parameter id="WTR" type="uint" value="6" />
<parameter id="RRD" type="uint" value="6" />
<parameter id="FAW" type="uint" value="32" />
<parameter id="CKE" type="uint" value="3" />
<parameter id="REFM" type="uint" value="1" />
<parameter id="REFI" type="uint" value="2078" />
<parameter id="RFCAB" type="uint" value="96" />
<parameter id="RFCPB" type="uint" value="48" />
<parameter id="CKESR" type="uint" value="8" />
<parameter id="XS" type="uint" value="102" />
<parameter id="XP" type="uint" value="4" />
<parameter id="RL" type="uint" value="9" />
<parameter id="WL" type="uint" value="7" />
<parameter id="WR" type="uint" value="11" />
<parameter id="RTP" type="uint" value="4" />
<parameter id="CCD" type="uint" value="2" />
<parameter id="clkMhz" type="double" value="533" />
<parameter id="RCD" type="uint" value="10" />
<parameter id="RPPB" type="uint" value="10" />
<parameter id="RPAB" type="uint" value="12" />
<parameter id="RAS" type="uint" value="23" />
<parameter id="RCPB" type="uint" value="32" />
<parameter id="RCAB" type="uint" value="34" />
<parameter id="WTR" type="uint" value="6" />
<parameter id="RRD" type="uint" value="6" />
<parameter id="FAW" type="uint" value="32" />
<parameter id="CKE" type="uint" value="3" />
<parameter id="REFM" type="uint" value="1" />
<parameter id="REFI" type="uint" value="2078" />
<parameter id="RFCAB" type="uint" value="96" />
<parameter id="RFCPB" type="uint" value="48" />
<parameter id="CKESR" type="uint" value="8" />
<parameter id="XS" type="uint" value="102" />
<parameter id="XP" type="uint" value="4" />
<parameter id="RL" type="uint" value="9" />
<parameter id="WL" type="uint" value="7" />
<parameter id="WR" type="uint" value="11" />
<parameter id="RTP" type="uint" value="4" />
<parameter id="CCD" type="uint" value="2" />
</memtimingspec>
<mempowerspec>
<parameter id="idd0" type="double" value="5.88" />
<parameter id="idd02" type="double" value="21.18" />
<parameter id="idd2p0" type="double" value="0.05" />
<parameter id="idd2p02" type="double" value="0.17" />
<parameter id="idd2p1" type="double" value="0.05" />
<parameter id="idd2p12" type="double" value="0.17" />
<parameter id="idd2n" type="double" value="0.13" />
<parameter id="idd2n2" type="double" value="4.04" />
<parameter id="idd3p0" type="double" value="0.25" />
<parameter id="idd3p02" type="double" value="1.49" />
<parameter id="idd3p1" type="double" value="0.25" />
<parameter id="idd3p12" type="double" value="1.49" />
<parameter id="idd3n" type="double" value="0.52" />
<parameter id="idd3n2" type="double" value="6.55" />
<parameter id="idd4r" type="double" value="1.41" />
<parameter id="idd4r2" type="double" value="85.73" />
<parameter id="idd4w" type="double" value="1.42" />
<parameter id="idd4w2" type="double" value="60.79" />
<parameter id="idd5" type="double" value="14.43" />
<parameter id="idd52" type="double" value="48.17" />
<parameter id="idd6" type="double" value="0.07" />
<parameter id="idd62" type="double" value="0.27" />
<parameter id="vdd" type="double" value="1.8" />
<parameter id="vdd2" type="double" value="1.2" />
<!-- to be completed -->
</mempowerspec>
</memspec>

112
DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.xml
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@@ -13,88 +13,38 @@
<parameter id="burstLength" type="uint" value="16" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="1600" />
<parameter id="REFI" type="uint" value="6246" />
<parameter id="REFIPB" type="uint" value="780" />
<parameter id="RFCAB" type="uint" value="448" />
<parameter id="RFCPB" type="uint" value="224" />
<parameter id="RPAB" type="uint" value="34" />
<parameter id="RPPB" type="uint" value="29" />
<parameter id="PPD" type="uint" value="4" />
<parameter id="RAS" type="uint" value="68" />
<parameter id="RCD" type="uint" value="29" />
<parameter id="FAW" type="uint" value="64" />
<parameter id="RRD" type="uint" value="16" />
<parameter id="CCD" type="uint" value="8" />
<parameter id="RL" type="uint" value="28" />
<parameter id="RPST" type="uint" value="0" />
<parameter id="DQSCK" type="uint" value="6" />
<parameter id="RTP" type="uint" value="12" />
<parameter id="WL" type="uint" value="14" />
<parameter id="DQSS" type="uint" value="1" />
<parameter id="DQS2DQ" type="uint" value="2" />
<!--parameter id="nWR" type="uint" value="30" /-->
<parameter id="WR" type="uint" value="29" />
<parameter id="WPRE" type="uint" value="2" />
<parameter id="WTR" type="uint" value="16" />
<parameter id="XP" type="uint" value="12" />
<parameter id="SR" type="uint" value="24" />
<parameter id="XSR" type="uint" value="460" />
<parameter id="ESCKE" type="uint" value="3" />
<parameter id="CKE" type="uint" value="12" />
<parameter id="CMDCKE" type="uint" value="3" />
<parameter id="clkMhz" type="double" value="1600" />
<parameter id="REFI" type="uint" value="6246" />
<parameter id="REFIPB" type="uint" value="780" />
<parameter id="RFCAB" type="uint" value="448" />
<parameter id="RFCPB" type="uint" value="224" />
<parameter id="RPAB" type="uint" value="34" />
<parameter id="RPPB" type="uint" value="29" />
<parameter id="PPD" type="uint" value="4" />
<parameter id="RAS" type="uint" value="68" />
<parameter id="RCD" type="uint" value="29" />
<parameter id="FAW" type="uint" value="64" />
<parameter id="RRD" type="uint" value="16" />
<parameter id="CCD" type="uint" value="8" />
<parameter id="RL" type="uint" value="28" />
<parameter id="RPST" type="uint" value="0" />
<parameter id="DQSCK" type="uint" value="6" />
<parameter id="RTP" type="uint" value="12" />
<parameter id="WL" type="uint" value="14" />
<parameter id="DQSS" type="uint" value="1" />
<parameter id="DQS2DQ" type="uint" value="2" />
<!--parameter id="nWR" type="uint" value="30" /-->
<parameter id="WR" type="uint" value="29" />
<parameter id="WPRE" type="uint" value="2" />
<parameter id="WTR" type="uint" value="16" />
<parameter id="XP" type="uint" value="12" />
<parameter id="SR" type="uint" value="24" />
<parameter id="XSR" type="uint" value="460" />
<parameter id="ESCKE" type="uint" value="3" />
<parameter id="CKE" type="uint" value="12" />
<parameter id="CMDCKE" type="uint" value="3" />
</memtimingspec>
<mempowerspec>
<parameter id="idd0" type="double" value="3.5" />
<parameter id="idd02" type="double" value="45.0" />
<parameter id="idd0ql" type="double" value="0.75" />
<parameter id="idd2p" type="double" value="1.2" />
<parameter id="idd2p2" type="double" value="3.0" />
<parameter id="idd2pQ" type="double" value="0.75" />
<parameter id="idd2ps" type="double" value="1.2" />
<parameter id="idd2ps2" type="double" value="3.0" />
<parameter id="idd2psq" type="double" value="0.75" />
<parameter id="idd2n" type="double" value="2.0" />
<parameter id="idd2n2" type="double" value="27.0" />
<parameter id="idd2nQ" type="double" value="0.75" />
<parameter id="idd2ns" type="double" value="2.0" />
<parameter id="idd2ns2" type="double" value="23.0" />
<parameter id="idd2nsq" type="double" value="0.75" />
<parameter id="idd3p" type="double" value="1.2" />
<parameter id="idd3p2" type="double" value="9.0" />
<parameter id="idd3pQ" type="double" value="0.75" />
<parameter id="idd3ps" type="double" value="1.2" />
<parameter id="idd3ps2" type="double" value="9.0" />
<parameter id="idd3psq" type="double" value="0.75" />
<parameter id="idd3n" type="double" value="2.25" />
<parameter id="idd3n2" type="double" value="30.0" />
<parameter id="idd3nQ" type="double" value="0.75" />
<parameter id="idd3ns" type="double" value="2.25" />
<parameter id="idd3ns2" type="double" value="30.0" />
<parameter id="idd3nsq" type="double" value="0.75" />
<parameter id="idd4r" type="double" value="2.25" />
<parameter id="idd4r2" type="double" value="275.0" />
<parameter id="idd4rq" type="double" value="150.0" />
<parameter id="idd4w" type="double" value="2.25.0" />
<parameter id="idd4w2" type="double" value="210.0" />
<parameter id="idd4wq" type="double" value="55.0" />
<!-- refresh after every trfc -->
<parameter id="idd5" type="double" value="10.0" />
<parameter id="idd52" type="double" value="90.0" />
<parameter id="idd5q" type="double" value="0.75" />
<!-- ref once in every trefi -->
<parameter id="idd5ab" type="double" value="2.5" />
<parameter id="idd5ab2" type="double" value="30.0" />
<parameter id="idd5abq" type="double" value="0.75" />
<!-- perbank ref, ref once in every trefi/8 -->
<parameter id="idd5b" type="double" value="2.5" />
<parameter id="idd5b2" type="double" value="30.0" />
<parameter id="idd5bq" type="double" value="0.75" />
<parameter id="idd6" type="double" value="0.3" />
<parameter id="idd62" type="double" value="0.5" />
<parameter id="idd6q" type="double" value="0.1" />
<parameter id="vdd" type="double" value="1.8" />
<parameter id="vdd2" type="double" value="1.1" />
<parameter id="vddq" type="double" value="1.1" />
<!-- to be completed -->
</mempowerspec>
</memspec>

110
DRAMSys/library/src/configuration/ConfigurationLoader.cpp
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@@ -41,6 +41,7 @@
#include "memspec/MemSpecDDR4.h"
#include "memspec/MemSpecWideIO.h"
#include "memspec/MemSpecLPDDR4.h"
#include "memspec/MemSpecWideIO2.h"
#include "../common/timingCalculations.h"
using namespace tinyxml2;
@@ -168,6 +169,12 @@ void ConfigurationLoader::loadMemSpec(Configuration &config,
loadCommons(config, memspec);
loadWideIO(config, memspec);
}
else if (memoryType == "WIDEIO2")
{
Configuration::getInstance().memSpec = new MemSpecWideIO2();
loadCommons(config, memspec);
loadWideIO2(config, memspec);
}
else
reportFatal("ConfigurationLoader", "Unsupported DRAM type");
}
@@ -191,17 +198,6 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz");
memSpec->clk = FrequencyToClk(memSpec->clkMHz);
// Currents and voltages
XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec");
memSpec->iDD0 = queryDoubleParameter(powers, "idd0");
memSpec->iDD2N = queryDoubleParameter(powers, "idd2n");
memSpec->iDD3N = queryDoubleParameter(powers, "idd3n");
memSpec->iDD4R = queryDoubleParameter(powers, "idd4r");
memSpec->iDD4W = queryDoubleParameter(powers, "idd4w");
memSpec->iDD5 = queryDoubleParameter(powers, "idd5");
memSpec->iDD6 = queryDoubleParameter(powers, "idd6");
memSpec->vDD = queryDoubleParameter(powers, "vdd");
}
void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec)
@@ -245,8 +241,16 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec)
memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL");
memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL");
// Currents and Volatages: TODO Check if this is correct.
// Currents and voltages
XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec");
memSpec->iDD0 = queryDoubleParameter(powers, "idd0");
memSpec->iDD2N = queryDoubleParameter(powers, "idd2n");
memSpec->iDD3N = queryDoubleParameter(powers, "idd3n");
memSpec->iDD4R = queryDoubleParameter(powers, "idd4r");
memSpec->iDD4W = queryDoubleParameter(powers, "idd4w");
memSpec->iDD5 = queryDoubleParameter(powers, "idd5");
memSpec->iDD6 = queryDoubleParameter(powers, "idd6");
memSpec->vDD = queryDoubleParameter(powers, "vdd");
memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0");
memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1");
memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0");
@@ -313,8 +317,16 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec)
memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL");
memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL");
// Currents and Volatages:
// Currents and voltages
XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec");
memSpec->iDD0 = queryDoubleParameter(powers, "idd0");
memSpec->iDD2N = queryDoubleParameter(powers, "idd2n");
memSpec->iDD3N = queryDoubleParameter(powers, "idd3n");
memSpec->iDD4R = queryDoubleParameter(powers, "idd4r");
memSpec->iDD4W = queryDoubleParameter(powers, "idd4w");
memSpec->iDD5 = queryDoubleParameter(powers, "idd5");
memSpec->iDD6 = queryDoubleParameter(powers, "idd6");
memSpec->vDD = queryDoubleParameter(powers, "vdd");
memSpec->iDD02 = queryDoubleParameter(powers, "idd02");
memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0");
memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1");
@@ -324,7 +336,6 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec)
memSpec->vDD2 = queryDoubleParameter(powers, "vdd2");
}
// TODO: change timings for LPDDR4
void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec)
{
MemSpecLPDDR4 *memSpec = dynamic_cast<MemSpecLPDDR4 *>(config.memSpec);
@@ -372,15 +383,8 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec)
memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
memSpec->tCMDCKE = clk * queryUIntParameter(timings, "CMDCKE");
// Currents and Volatages:
XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec");
memSpec->iDD02 = queryDoubleParameter(powers, "idd02");
memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p");
memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p2");
memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p");
memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p2");
memSpec->iDD62 = queryDoubleParameter(powers, "idd62");
memSpec->vDD2 = queryDoubleParameter(powers, "vdd2");
// Currents and voltages
// TODO: to be completed
}
void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *xmlSpec)
@@ -403,7 +407,8 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *xmlSpec)
sc_time clk = memSpec->clk;
memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
//memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
memSpec->tAC = clk * queryUIntParameter(timings, "AC");
memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
memSpec->tRC = clk * queryUIntParameter(timings, "RC");
memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
@@ -421,8 +426,16 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *xmlSpec)
memSpec->tTAW = clk * queryUIntParameter(timings, "TAW");
memSpec->tWTR = clk * queryUIntParameter(timings, "WTR");
// Currents and Volatages:
// Currents and voltages
XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec");
memSpec->iDD0 = queryDoubleParameter(powers, "idd0");
memSpec->iDD2N = queryDoubleParameter(powers, "idd2n");
memSpec->iDD3N = queryDoubleParameter(powers, "idd3n");
memSpec->iDD4R = queryDoubleParameter(powers, "idd4r");
memSpec->iDD4W = queryDoubleParameter(powers, "idd4w");
memSpec->iDD5 = queryDoubleParameter(powers, "idd5");
memSpec->iDD6 = queryDoubleParameter(powers, "idd6");
memSpec->vDD = queryDoubleParameter(powers, "vdd");
memSpec->iDD02 = queryDoubleParameter(powers, "idd02");
memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0");
memSpec->iDD2P02 = queryDoubleParameter(powers, "idd2p02");
@@ -440,3 +453,50 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *xmlSpec)
memSpec->iDD62 = queryDoubleParameter(powers, "idd62");
memSpec->vDD2 = queryDoubleParameter(powers, "vdd2");
}
void ConfigurationLoader::loadWideIO2(Configuration &config, XMLElement *xmlSpec)
{
MemSpecWideIO2 *memSpec = dynamic_cast<MemSpecWideIO2 *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
// MemArchitecture
XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks");
memSpec->GroupsPerRank = 1;
memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank;
memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks;
memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks;
// MemTimings specific for WideIO
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
sc_time clk = memSpec->clk;
memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
memSpec->tDQSS = clk * queryUIntParameter(timings, "DQSS");
memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
memSpec->tRL = clk * queryUIntParameter(timings, "RL");
memSpec->tWL = clk * queryUIntParameter(timings, "WL");
memSpec->tRCpb = clk * queryUIntParameter(timings, "RCPB");
memSpec->tRCab = clk * queryUIntParameter(timings, "RCAB");
memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
memSpec->tXSR = clk * queryUIntParameter(timings, "XSR");
memSpec->tXP = clk * queryUIntParameter(timings, "XP");
memSpec->tCCD = clk * queryUIntParameter(timings, "CCD");
memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
memSpec->tRPpb = clk * queryUIntParameter(timings, "RPPB");
memSpec->tRPab = clk * queryUIntParameter(timings, "RPAB");
memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
memSpec->tWR = clk * queryUIntParameter(timings, "WR");
memSpec->tWTR = clk * queryUIntParameter(timings, "WTR");
memSpec->tRRD = clk * queryUIntParameter(timings, "RRD");
memSpec->tFAW = clk * queryUIntParameter(timings, "FAW");
memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
memSpec->tREFIpb = clk * queryUIntParameter(timings, "REFIPB");
memSpec->tRFCab = clk * queryUIntParameter(timings, "RFCAB");
memSpec->tRFCpb = clk * queryUIntParameter(timings, "RFCPB");
// Currents and voltages
// TODO: to be completed
}

1
DRAMSys/library/src/configuration/ConfigurationLoader.h
View File

@@ -73,6 +73,7 @@ private:
static void loadDDR4(Configuration &config, tinyxml2::XMLElement *memspec);
static void loadLPDDR4(Configuration &config, tinyxml2::XMLElement *memspec);
static void loadWideIO(Configuration &config, tinyxml2::XMLElement *memspec);
static void loadWideIO2(Configuration &config, tinyxml2::XMLElement *memspec);
};

10
DRAMSys/library/src/configuration/memspec/MemSpec.h
View File

@@ -87,16 +87,6 @@ struct MemSpec
double clkMHz;
sc_time clk;
// Currents and Voltages:
double iDD0;
double iDD2N;
double iDD3N;
double iDD4R;
double iDD4W;
double iDD5;
double iDD6;
double vDD;
// Command lengths on bus, standardly one clock cycle
std::vector<unsigned> commandLength;
};

9
DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h
View File

@@ -64,6 +64,15 @@ struct MemSpecDDR3 : public MemSpec
sc_time tXSDLL;
sc_time tAL;
// Currents and Voltages:
double iDD0;
double iDD2N;
double iDD3N;
double iDD4R;
double iDD4W;
double iDD5;
double iDD6;
double vDD;
double iDD2P0;
double iDD2P1;
double iDD3P0;

9
DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h
View File

@@ -67,6 +67,15 @@ struct MemSpecDDR4 : public MemSpec
sc_time tXPDLL;
sc_time tXSDLL;
// Currents and Voltages:
double iDD0;
double iDD2N;
double iDD3N;
double iDD4R;
double iDD4W;
double iDD5;
double iDD6;
double vDD;
double iDD02;
double iDD2P0;
double iDD2P1;

13
DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h
View File

@@ -40,6 +40,8 @@
struct MemSpecLPDDR4 : public MemSpec
{
MemSpecLPDDR4();
// Memspec Variables:
sc_time tREFI;
sc_time tREFIpb;
@@ -70,15 +72,8 @@ struct MemSpecLPDDR4 : public MemSpec
sc_time tCKE;
sc_time tCMDCKE;
double iDD02;
double iDD2P0;
double iDD2P1;
double iDD3P0;
double iDD3P1;
double iDD62;
double vDD2;
MemSpecLPDDR4();
// Currents and Voltages:
// TODO: to be completed
sc_time getRefreshIntervalPB() const override;
sc_time getRefreshIntervalAB() const override;

8
DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp
View File

@@ -49,9 +49,11 @@ sc_time MemSpecWideIO::getRefreshIntervalPB() const
TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime());
return TimeInterval(sc_time_stamp() + tRL + tAC,
sc_time_stamp() + tRL + tAC + getReadAccessTime());
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + getWriteAccessTime());
return TimeInterval(sc_time_stamp() + tWL,
sc_time_stamp() + tWL + getWriteAccessTime());
else
{
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
@@ -67,7 +69,7 @@ sc_time MemSpecWideIO::getExecutionTime(Command command) const
else if (command == Command::ACT)
return tRCD;
else if (command == Command::RD || command == Command::RDA)
return tRL + getReadAccessTime();
return tRL + tAC + getReadAccessTime();
// else if (command == Command::RDA)
// // this time is wrong (controller internally waits for tRAS)
// return tRTP + tRP;

10
DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h
View File

@@ -55,12 +55,22 @@ struct MemSpecWideIO : public MemSpec
sc_time tRFC;
sc_time tRP;
sc_time tDQSCK;
sc_time tAC;
sc_time tCCD_R;
sc_time tCCD_W;
sc_time tRRD;
sc_time tTAW;
sc_time tWTR;
// Currents and Voltages:
double iDD0;
double iDD2N;
double iDD3N;
double iDD4R;
double iDD4W;
double iDD5;
double iDD6;
double vDD;
double iDD02;
double iDD2P0;
double iDD2P02;

86
DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp Normal file
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@@ -0,0 +1,86 @@
/*
* Copyright (c) 2019, University of Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#include "MemSpecWideIO2.h"
sc_time MemSpecWideIO2::getRefreshIntervalAB() const
{
return tREFI;
}
sc_time MemSpecWideIO2::getRefreshIntervalPB() const
{
return tREFIpb;
}
TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(sc_time_stamp() + tRL + tDQSCK,
sc_time_stamp() + tRL + tDQSCK + getReadAccessTime());
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(sc_time_stamp() + tWL + tDQSS,
sc_time_stamp() + tWL + tDQSS + getWriteAccessTime());
else
{
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
return TimeInterval();
}
}
// Returns the execution time for commands that have a fixed execution time
sc_time MemSpecWideIO2::getExecutionTime(Command command) const
{
if (command == Command::PRE)
return tRPpb;
else if (command == Command::PREA)
return tRPab;
else if (command == Command::ACT)
return tRCD;
else if (command == Command::RD || command == Command::RDA)
return tRL + tDQSCK + getReadAccessTime();
else if (command == Command::WR || command == Command::WRA)
return tWL + tDQSS + getWriteAccessTime();
else if (command == Command::REFA)
return tRFCab;
else if (command == Command::REFB)
return tRFCpb;
else
{
SC_REPORT_FATAL("MemSpecWideIO2::getExecutionTime",
"command not known or command doesn't have a fixed execution time");
return SC_ZERO_TIME;
}
}

79
DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h Normal file
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@@ -0,0 +1,79 @@
/*
* Copyright (c) 2019, University of Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#ifndef MEMSPECWIDEIO2_H
#define MEMSPECWIDEIO2_H
#include "MemSpec.h"
struct MemSpecWideIO2 : public MemSpec
{
// Memspec Variables:
sc_time tDQSCK;
sc_time tDQSS;
sc_time tCKE;
sc_time tRL;
sc_time tWL;
sc_time tRCpb;
sc_time tRCab;
sc_time tCKESR;
sc_time tXSR;
sc_time tXP;
sc_time tCCD;
sc_time tRTP;
sc_time tRCD;
sc_time tRPpb;
sc_time tRPab;
sc_time tRAS;
sc_time tWR;
sc_time tWTR;
sc_time tRRD;
sc_time tFAW;
sc_time tREFI;
sc_time tREFIpb;
sc_time tRFCab;
sc_time tRFCpb;
// Currents and Voltages:
// TODO: to be completed
sc_time getRefreshIntervalPB() const override;
sc_time getRefreshIntervalAB() const override;
sc_time getExecutionTime(Command) const override;
TimeInterval getIntervalOnDataStrobe(Command) const override;
};
#endif // MEMSPECWIDEIO2_H