diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.xml new file mode 100644 index 00000000..cada45b2 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.xml index 94ac21ae..fc952eba 100644 --- a/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.xml +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.xml @@ -2,10 +2,10 @@ - - - - + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.xml index 838ee7f7..99fc35e7 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.xml +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.xml @@ -21,7 +21,8 @@ - + + diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.xml index 39da583f..62abc699 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.xml +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.xml @@ -21,7 +21,8 @@ - + + diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.xml index 1d4023c3..d2c14626 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.xml +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.xml @@ -13,54 +13,31 @@ - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - + diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.xml index 598303ad..901e0b21 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.xml +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.xml @@ -13,54 +13,31 @@ - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - + diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.xml index 75a2cf67..562e1e07 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.xml +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.xml @@ -13,88 +13,38 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + diff --git a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp index 42bf68cf..eaacaf3e 100644 --- a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp @@ -41,6 +41,7 @@ #include "memspec/MemSpecDDR4.h" #include "memspec/MemSpecWideIO.h" #include "memspec/MemSpecLPDDR4.h" +#include "memspec/MemSpecWideIO2.h" #include "../common/timingCalculations.h" using namespace tinyxml2; @@ -168,6 +169,12 @@ void ConfigurationLoader::loadMemSpec(Configuration &config, loadCommons(config, memspec); loadWideIO(config, memspec); } + else if (memoryType == "WIDEIO2") + { + Configuration::getInstance().memSpec = new MemSpecWideIO2(); + loadCommons(config, memspec); + loadWideIO2(config, memspec); + } else reportFatal("ConfigurationLoader", "Unsupported DRAM type"); } @@ -191,17 +198,6 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz"); memSpec->clk = FrequencyToClk(memSpec->clkMHz); - - // Currents and voltages - XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); - memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); - memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); - memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); - memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); - memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); - memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); - memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); - memSpec->vDD = queryDoubleParameter(powers, "vdd"); } void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) @@ -245,8 +241,16 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL"); - // Currents and Volatages: TODO Check if this is correct. + // Currents and voltages XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); + memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); + memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); + memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); + memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); + memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); + memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); + memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); + memSpec->vDD = queryDoubleParameter(powers, "vdd"); memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0"); memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1"); memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0"); @@ -313,8 +317,16 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL"); - // Currents and Volatages: + // Currents and voltages XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); + memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); + memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); + memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); + memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); + memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); + memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); + memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); + memSpec->vDD = queryDoubleParameter(powers, "vdd"); memSpec->iDD02 = queryDoubleParameter(powers, "idd02"); memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0"); memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1"); @@ -324,7 +336,6 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) memSpec->vDD2 = queryDoubleParameter(powers, "vdd2"); } -// TODO: change timings for LPDDR4 void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec) { MemSpecLPDDR4 *memSpec = dynamic_cast(config.memSpec); @@ -372,15 +383,8 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec) memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); memSpec->tCMDCKE = clk * queryUIntParameter(timings, "CMDCKE"); - // Currents and Volatages: - XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); - memSpec->iDD02 = queryDoubleParameter(powers, "idd02"); - memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p"); - memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p2"); - memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p"); - memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p2"); - memSpec->iDD62 = queryDoubleParameter(powers, "idd62"); - memSpec->vDD2 = queryDoubleParameter(powers, "vdd2"); + // Currents and voltages + // TODO: to be completed } void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *xmlSpec) @@ -403,7 +407,8 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *xmlSpec) sc_time clk = memSpec->clk; memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); - //memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); + memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); + memSpec->tAC = clk * queryUIntParameter(timings, "AC"); memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); memSpec->tRC = clk * queryUIntParameter(timings, "RC"); memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); @@ -421,8 +426,16 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *xmlSpec) memSpec->tTAW = clk * queryUIntParameter(timings, "TAW"); memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); - // Currents and Volatages: + // Currents and voltages XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); + memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); + memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); + memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); + memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); + memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); + memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); + memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); + memSpec->vDD = queryDoubleParameter(powers, "vdd"); memSpec->iDD02 = queryDoubleParameter(powers, "idd02"); memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0"); memSpec->iDD2P02 = queryDoubleParameter(powers, "idd2p02"); @@ -440,3 +453,50 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *xmlSpec) memSpec->iDD62 = queryDoubleParameter(powers, "idd62"); memSpec->vDD2 = queryDoubleParameter(powers, "vdd2"); } + +void ConfigurationLoader::loadWideIO2(Configuration &config, XMLElement *xmlSpec) +{ + MemSpecWideIO2 *memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); + + // MemArchitecture + XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->GroupsPerRank = 1; + memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; + memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; + memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; + + // MemTimings specific for WideIO + XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); + sc_time clk = memSpec->clk; + memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); + memSpec->tDQSS = clk * queryUIntParameter(timings, "DQSS"); + memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); + memSpec->tRL = clk * queryUIntParameter(timings, "RL"); + memSpec->tWL = clk * queryUIntParameter(timings, "WL"); + memSpec->tRCpb = clk * queryUIntParameter(timings, "RCPB"); + memSpec->tRCab = clk * queryUIntParameter(timings, "RCAB"); + memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); + memSpec->tXSR = clk * queryUIntParameter(timings, "XSR"); + memSpec->tXP = clk * queryUIntParameter(timings, "XP"); + memSpec->tCCD = clk * queryUIntParameter(timings, "CCD"); + memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); + memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); + memSpec->tRPpb = clk * queryUIntParameter(timings, "RPPB"); + memSpec->tRPab = clk * queryUIntParameter(timings, "RPAB"); + memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); + memSpec->tWR = clk * queryUIntParameter(timings, "WR"); + memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); + memSpec->tRRD = clk * queryUIntParameter(timings, "RRD"); + memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); + memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); + memSpec->tREFIpb = clk * queryUIntParameter(timings, "REFIPB"); + memSpec->tRFCab = clk * queryUIntParameter(timings, "RFCAB"); + memSpec->tRFCpb = clk * queryUIntParameter(timings, "RFCPB"); + + // Currents and voltages + // TODO: to be completed +} diff --git a/DRAMSys/library/src/configuration/ConfigurationLoader.h b/DRAMSys/library/src/configuration/ConfigurationLoader.h index 142a6918..9bcf77e4 100644 --- a/DRAMSys/library/src/configuration/ConfigurationLoader.h +++ b/DRAMSys/library/src/configuration/ConfigurationLoader.h @@ -73,6 +73,7 @@ private: static void loadDDR4(Configuration &config, tinyxml2::XMLElement *memspec); static void loadLPDDR4(Configuration &config, tinyxml2::XMLElement *memspec); static void loadWideIO(Configuration &config, tinyxml2::XMLElement *memspec); + static void loadWideIO2(Configuration &config, tinyxml2::XMLElement *memspec); }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index 98094d8b..dbb28264 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -87,16 +87,6 @@ struct MemSpec double clkMHz; sc_time clk; - // Currents and Voltages: - double iDD0; - double iDD2N; - double iDD3N; - double iDD4R; - double iDD4W; - double iDD5; - double iDD6; - double vDD; - // Command lengths on bus, standardly one clock cycle std::vector commandLength; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h index d2345098..44c972c0 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h @@ -64,6 +64,15 @@ struct MemSpecDDR3 : public MemSpec sc_time tXSDLL; sc_time tAL; + // Currents and Voltages: + double iDD0; + double iDD2N; + double iDD3N; + double iDD4R; + double iDD4W; + double iDD5; + double iDD6; + double vDD; double iDD2P0; double iDD2P1; double iDD3P0; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h index 592b864a..ece11a56 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h @@ -67,6 +67,15 @@ struct MemSpecDDR4 : public MemSpec sc_time tXPDLL; sc_time tXSDLL; + // Currents and Voltages: + double iDD0; + double iDD2N; + double iDD3N; + double iDD4R; + double iDD4W; + double iDD5; + double iDD6; + double vDD; double iDD02; double iDD2P0; double iDD2P1; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h index 2cc80bfe..ed87d516 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h @@ -40,6 +40,8 @@ struct MemSpecLPDDR4 : public MemSpec { + MemSpecLPDDR4(); + // Memspec Variables: sc_time tREFI; sc_time tREFIpb; @@ -70,15 +72,8 @@ struct MemSpecLPDDR4 : public MemSpec sc_time tCKE; sc_time tCMDCKE; - double iDD02; - double iDD2P0; - double iDD2P1; - double iDD3P0; - double iDD3P1; - double iDD62; - double vDD2; - - MemSpecLPDDR4(); + // Currents and Voltages: + // TODO: to be completed sc_time getRefreshIntervalPB() const override; sc_time getRefreshIntervalAB() const override; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp index 5ea73ad9..b5e9a90f 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp @@ -49,9 +49,11 @@ sc_time MemSpecWideIO::getRefreshIntervalPB() const TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime()); + return TimeInterval(sc_time_stamp() + tRL + tAC, + sc_time_stamp() + tRL + tAC + getReadAccessTime()); else if (command == Command::WR || command == Command::WRA) - return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + getWriteAccessTime()); + return TimeInterval(sc_time_stamp() + tWL, + sc_time_stamp() + tWL + getWriteAccessTime()); else { SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); @@ -67,7 +69,7 @@ sc_time MemSpecWideIO::getExecutionTime(Command command) const else if (command == Command::ACT) return tRCD; else if (command == Command::RD || command == Command::RDA) - return tRL + getReadAccessTime(); + return tRL + tAC + getReadAccessTime(); // else if (command == Command::RDA) // // this time is wrong (controller internally waits for tRAS) // return tRTP + tRP; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h index 7185b25a..1f3ce38f 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h @@ -55,12 +55,22 @@ struct MemSpecWideIO : public MemSpec sc_time tRFC; sc_time tRP; sc_time tDQSCK; + sc_time tAC; sc_time tCCD_R; sc_time tCCD_W; sc_time tRRD; sc_time tTAW; sc_time tWTR; + // Currents and Voltages: + double iDD0; + double iDD2N; + double iDD3N; + double iDD4R; + double iDD4W; + double iDD5; + double iDD6; + double vDD; double iDD02; double iDD2P0; double iDD2P02; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp new file mode 100644 index 00000000..a163acf4 --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#include "MemSpecWideIO2.h" + +sc_time MemSpecWideIO2::getRefreshIntervalAB() const +{ + return tREFI; +} + +sc_time MemSpecWideIO2::getRefreshIntervalPB() const +{ + return tREFIpb; +} + +TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command) const +{ + if (command == Command::RD || command == Command::RDA) + return TimeInterval(sc_time_stamp() + tRL + tDQSCK, + sc_time_stamp() + tRL + tDQSCK + getReadAccessTime()); + else if (command == Command::WR || command == Command::WRA) + return TimeInterval(sc_time_stamp() + tWL + tDQSS, + sc_time_stamp() + tWL + tDQSS + getWriteAccessTime()); + else + { + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + return TimeInterval(); + } +} + +// Returns the execution time for commands that have a fixed execution time +sc_time MemSpecWideIO2::getExecutionTime(Command command) const +{ + if (command == Command::PRE) + return tRPpb; + else if (command == Command::PREA) + return tRPab; + else if (command == Command::ACT) + return tRCD; + else if (command == Command::RD || command == Command::RDA) + return tRL + tDQSCK + getReadAccessTime(); + else if (command == Command::WR || command == Command::WRA) + return tWL + tDQSS + getWriteAccessTime(); + else if (command == Command::REFA) + return tRFCab; + else if (command == Command::REFB) + return tRFCpb; + else + { + SC_REPORT_FATAL("MemSpecWideIO2::getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + return SC_ZERO_TIME; + } +} diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h new file mode 100644 index 00000000..d3000da4 --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#ifndef MEMSPECWIDEIO2_H +#define MEMSPECWIDEIO2_H + +#include "MemSpec.h" + +struct MemSpecWideIO2 : public MemSpec +{ + // Memspec Variables: + sc_time tDQSCK; + sc_time tDQSS; + sc_time tCKE; + sc_time tRL; + sc_time tWL; + sc_time tRCpb; + sc_time tRCab; + sc_time tCKESR; + sc_time tXSR; + sc_time tXP; + sc_time tCCD; + sc_time tRTP; + sc_time tRCD; + sc_time tRPpb; + sc_time tRPab; + sc_time tRAS; + sc_time tWR; + sc_time tWTR; + sc_time tRRD; + sc_time tFAW; + sc_time tREFI; + sc_time tREFIpb; + sc_time tRFCab; + sc_time tRFCpb; + + // Currents and Voltages: + // TODO: to be completed + + sc_time getRefreshIntervalPB() const override; + sc_time getRefreshIntervalAB() const override; + + sc_time getExecutionTime(Command) const override; + TimeInterval getIntervalOnDataStrobe(Command) const override; +}; + +#endif // MEMSPECWIDEIO2_H