Included missing memory allocation in Dram.

DRAMSys/library/src/controller/core/configuration/Configuration.cpp

@@ -335,6 +335,8 @@ void Configuration::setParameters(std::map<std::string, std::string>
 std::uint64_t Configuration::getSimMemSizeInBytes()
 {
     // 1. Get number of banks, rows, columns and data width in bits for one die (or chip)
+    std::uint64_t ranks = memSpec->NumberOfRanks;
+    std::uint64_t bankgroups = memSpec->NumberOfBankGroups;
     std::uint64_t banks = memSpec->NumberOfBanks;
     std::uint64_t rows = memSpec->NumberOfRows;
     std::uint64_t columns = memSpec->NumberOfColumns;
@@ -348,6 +350,8 @@ std::uint64_t Configuration::getSimMemSizeInBytes()
 
     std::cout << headline << std::endl << std::endl;
     std::cout << std::setw(24) << "Memory size in bytes : " << memorySize            << std::endl;
+    std::cout << std::setw(24) << "Number of ranks      : " << ranks                 << std::endl;
+    std::cout << std::setw(24) << "Number of bankgroups : " << bankgroups            << std::endl;
     std::cout << std::setw(24) << "Number of banks      : " << banks                 << std::endl;
     std::cout << std::setw(24) << "Number of rows       : " << rows                  << std::endl;
     std::cout << std::setw(24) << "Number of columns    : " << columns               << std::endl;

DRAMSys/library/src/simulation/Dram.cpp

@@ -62,8 +62,25 @@ using namespace Data;
 Dram::Dram(sc_module_name name) : sc_module(name), tSocket("socket")
 {
     // Adjust number of bytes per burst dynamically to the selected ecc controller
+    // TODO: ECC only used for WideIO?
     bytesPerBurst = Configuration::getInstance().adjustNumBytesAfterECC(bytesPerBurst);
 
+    uint64_t memorySize = Configuration::getInstance().getSimMemSizeInBytes();
+    if (StoreMode == StorageMode::Store)
+    {
+        if (Configuration::getInstance().UseMalloc)
+        {
+            memory = (unsigned char *)malloc(memorySize);
+            if (!memory)
+                SC_REPORT_FATAL(this->name(), "Memory allocation failed");
+        }
+        else
+        {
+            // allocate and model storage of one DRAM channel using memory map
+            memory = (unsigned char *)mmap(NULL, memorySize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0);
+        }
+    }
+
     tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw);
     tSocket.register_transport_dbg(this, &Dram::transport_dbg);
 }

DRAMSys/library/src/simulation/Dram.h

@@ -57,9 +57,6 @@ class Dram : public sc_module
 private:
     unsigned int bytesPerBurst = Configuration::getInstance().getBytesPerBurst();
 
-    // Power Model related
-    bool powerAnalysis = Configuration::getInstance().PowerAnalysis;
-
 protected:
     Dram(sc_module_name);
     SC_HAS_PROCESS(Dram);

DRAMSys/library/src/simulation/DramWideIO.cpp

@@ -147,9 +147,6 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name)
         // For each bank in a channel a error Model is created:
         if (StoreMode == StorageMode::ErrorModel)
         {
-            if (Configuration::getInstance().UseMalloc)
-                free(memory);
-
             for (unsigned i = 0; i < memSpec->NumberOfBanks; i++)
             {
                 errorModel *em;