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Included GenericController for polymorphism.

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This commit is contained in:
Lukas Steiner (2)
2019-08-14 09:44:24 +02:00
parent c2022667c5
commit 0918a78648
3 changed files with 19 additions and 20 deletions
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22
DRAMSys/library/src/controller/GenericController.h
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@@ -18,17 +18,6 @@ public:
tlm_utils::simple_target_socket<GenericController> tSocket; // Arbiter side
tlm_utils::simple_initiator_socket<GenericController> iSocket; // DRAM side
protected:
// Bind sockets with virtual functions
GenericController(sc_module_name name) :
sc_module(name), tSocket("tSocket"), iSocket("iSocket")
{
tSocket.register_nb_transport_fw(this, &GenericController::nb_transport_fw);
tSocket.register_transport_dbg(this, &GenericController::transport_dbg);
iSocket.register_nb_transport_bw(this, &GenericController::nb_transport_bw);
}
SC_HAS_PROCESS(GenericController);
// Destructor
virtual ~GenericController()
{
@@ -69,6 +58,17 @@ protected:
<< std::endl;
}
protected:
// Bind sockets with virtual functions
GenericController(sc_module_name name) :
sc_module(name), tSocket("tSocket"), iSocket("iSocket")
{
tSocket.register_nb_transport_fw(this, &GenericController::nb_transport_fw);
tSocket.register_transport_dbg(this, &GenericController::transport_dbg);
iSocket.register_nb_transport_bw(this, &GenericController::nb_transport_bw);
}
SC_HAS_PROCESS(GenericController);
// Virtual transport functions
virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &, tlm_phase &, sc_time &) = 0;
virtual unsigned int transport_dbg(tlm_generic_payload &) = 0;

14
DRAMSys/library/src/simulation/DRAMSys.cpp
View File

@@ -252,12 +252,12 @@ void DRAMSys::instantiateModules(const string &traceName,
{
std::string str = "controller" + std::to_string(i);
ControllerNew *controller;
GenericController *controller;
if (recordingEnabled)
controller = new ControllerRecordable(str.c_str(), tlmRecorders[i]);
else
controller = new ControllerNew(str.c_str());
newControllers.push_back(controller);
controllers.push_back(controller);
str = "dram" + std::to_string(i);
Dram *dram;
@@ -315,15 +315,15 @@ void DRAMSys::bindSockets()
i++) {
arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket);
controllersTlmCheckers[i]->initiator_socket.bind(
newControllers[i]->tSocket);
newControllers[i]->iSocket.bind(drams[i]->tSocket);
controllers[i]->tSocket);
controllers[i]->iSocket.bind(drams[i]->tSocket);
}
} else {
for (size_t i = 0;
i < Configuration::getInstance().NumberOfMemChannels;
i++) {
arbiter->iSocket.bind(newControllers[i]->tSocket);
newControllers[i]->iSocket.bind(drams[i]->tSocket);
arbiter->iSocket.bind(controllers[i]->tSocket);
controllers[i]->iSocket.bind(drams[i]->tSocket);
}
}
}
@@ -351,7 +351,7 @@ DRAMSys::~DRAMSys()
delete tlmChecker;
}
for (auto controller : newControllers) {
for (auto controller : controllers) {
delete controller;
}
}

3
DRAMSys/library/src/simulation/DRAMSys.h
View File

@@ -52,7 +52,6 @@
#include "../common/tlm2_base_protocol_checker.h"
#include "../error/eccbaseclass.h"
#include "../controller/GenericController.h"
#include "../controller/ControllerNew.h"
class DRAMSys : public sc_module
{
@@ -88,7 +87,7 @@ private:
// All transactions pass through the same arbiter
Arbiter *arbiter;
// Each DRAM unit has a controller
std::vector<ControllerNew *> newControllers;
std::vector<GenericController *> controllers;
//std::vector<GenericController *> controllers;
// TODO: Each DRAM has a reorder buffer (check this!)