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Removed lastDataStrobeCommands in ControllerState, removed unused methods in timing checker.

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This commit is contained in:
Lukas Steiner
2019-07-28 21:50:28 +02:00
parent a05b0ed610
commit 42344ce87f
7 changed files with 22 additions and 194 deletions
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20
DRAMSys/library/src/controller/ControllerState.cpp
View File

@@ -106,18 +106,6 @@ void ControllerState::change(const ScheduledCommand &scheduledCommand)
switch (scheduledCommand.getCommand())
{
case Command::RD:
lastDataStrobeCommands.emplace_back(scheduledCommand);
break;
case Command::RDA:
lastDataStrobeCommands.emplace_back(scheduledCommand);
break;
case Command::WR:
lastDataStrobeCommands.emplace_back(scheduledCommand);
break;
case Command::WRA:
lastDataStrobeCommands.emplace_back(scheduledCommand);
break;
case Command::ACTB:
lastActivatesB.emplace(scheduledCommand.getStart(), scheduledCommand);
break;
@@ -132,13 +120,7 @@ void ControllerState::change(const ScheduledCommand &scheduledCommand)
void ControllerState::cleanUp(sc_time time)
{
bus.cleanUpSlots(time);
vector<ScheduledCommand> tmp;
for (ScheduledCommand &command : lastDataStrobeCommands) {
if (command.getEnd() >= time
|| getDistance(command.getEnd(), time) <= config->memSpec->tDataStrobeHistory())
tmp.push_back(command);
}
lastDataStrobeCommands = tmp;
if (time >= config->memSpec->tActHistory())
lastActivates.erase(lastActivates.begin(),
lastActivates.lower_bound(time - config->memSpec->tActHistory()));

4
DRAMSys/library/src/controller/ControllerState.h
View File

@@ -60,15 +60,13 @@ public:
void cleanUp(sc_time time);
//used by the various checkers
std::map<Command, std::map<Bank, ScheduledCommand> >
lastScheduledByCommandAndBank;
std::map<Command, std::map<Bank, ScheduledCommand>> lastScheduledByCommandAndBank;
// TODO: remove
//std::map<Command, ScheduledCommand> lastScheduledByCommand;
//std::map<Bank, ScheduledCommand> lastScheduledByBank;
//ScheduledCommand lastScheduled;
Slots bus;
std::vector<ScheduledCommand> lastDataStrobeCommands;
std::map<sc_time, ScheduledCommand> lastActivates;
std::map<sc_time, ScheduledCommand> lastActivatesB;

20
DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp
View File

@@ -441,11 +441,11 @@ bool CheckerDDR3::satisfies_nActivateWindow(ScheduledCommand &command) const
bool CheckerDDR3::collidesOnDataStrobe_RD(ScheduledCommand &read) const
{
for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands)
{
if (collidesWithStrobeCommand_RD(read, strobeCommand))
return true;
}
// for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands)
// {
// if (collidesWithStrobeCommand_RD(read, strobeCommand))
// return true;
// }
return false;
}
@@ -515,11 +515,11 @@ sc_time CheckerDDR3::CasToCas(ScheduledCommand &firstCAS, ScheduledCommand &seco
bool CheckerDDR3::collidesOnDataStrobe_WR(ScheduledCommand &write) const
{
for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands)
{
if (collidesWithStrobeCommand_WR(write, strobeCommand))
return true;
}
// for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands)
// {
// if (collidesWithStrobeCommand_WR(write, strobeCommand))
// return true;
// }
return false;
}

132
DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp
View File

@@ -165,22 +165,6 @@ sc_time CheckerDDR3New::delayToSatisfyConstraints(Command command, Bank bank)
return (minTimeToWait - sc_time_stamp());
}
/*
* ActivateChecker
*/
bool CheckerDDR3New::satsfiesACTtoACTdifferentBank(ScheduledCommand &command) const
{
for (auto act : state.lastActivates)
{
sc_time time = act.first;
if ((time < command.getStart() && command.getStart() - time < memSpec->tRRD)
|| (command.getStart() <= time && time - command.getStart() < memSpec->tRRD))
return false;
}
return true;
}
bool CheckerDDR3New::satisfiesNActivateWindow(ScheduledCommand &command) const
{
/*
@@ -206,119 +190,3 @@ bool CheckerDDR3New::satisfiesNActivateWindow(ScheduledCommand &command) const
}
return true;
}
/*
* Read-Checker
*/
bool CheckerDDR3New::collidesOnDataStrobe_RD(ScheduledCommand &read) const
{
for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands)
{
if (collidesWithStrobeCommand_RD(read, strobeCommand))
return true;
}
return false;
}
bool CheckerDDR3New::collidesWithStrobeCommand_RD(ScheduledCommand &read,
ScheduledCommand &strobeCommand) const
{
if (strobeCommand.getCommand() == Command::RD || strobeCommand.getCommand() == Command::RDA)
{
return getDistance(read.getStart(),
strobeCommand.getStart()) < CasToCas(strobeCommand, read);
}
else if (strobeCommand.getCommand() == Command::WR || strobeCommand.getCommand() == Command::WRA)
{
if (strobeCommand.getStart() >= read.getStart())
return getDistance(read.getStart(),
strobeCommand.getStart()) < readToWrite(read, strobeCommand);
else
return getDistance(strobeCommand.getStart(),
read.getStart()) < writeToRead(strobeCommand, read);
} else {
reportFatal("CheckerDDR3New",
"Invalid strobeCommand in data strobe commands " + commandToString(
strobeCommand.getCommand()));
return true;
}
return false;
}
sc_time CheckerDDR3New::writeToRead(ScheduledCommand &write, ScheduledCommand &read) const
{
sc_assert(read.getCommand() == Command::RD || read.getCommand() == Command::RDA);
sc_assert(write.getCommand() == Command::WR || write.getCommand() == Command::WRA);
return memSpec->tWL + memSpec->getWriteAccessTime() + memSpec->tWTR;
}
/* CAS-CAS */
sc_time CheckerDDR3New::CasToCas(ScheduledCommand &firstCAS, ScheduledCommand &secondCAS) const
{
if (firstCAS.getCommand() == Command::RD || firstCAS.getCommand() == Command::RDA)
{
if (secondCAS.getCommand() == Command::RD || secondCAS.getCommand() == Command::RDA)
return std::max(memSpec->tCCD, memSpec->getReadAccessTime());
}
else if (firstCAS.getCommand() == Command::WR || firstCAS.getCommand() == Command::WRA)
{
if (secondCAS.getCommand() == Command::WR || secondCAS.getCommand() == Command::WRA)
return std::max(memSpec->tCCD, memSpec->getWriteAccessTime());
}
SC_REPORT_FATAL("CasToCas", "Exception reached");
return SC_ZERO_TIME;
}
/*
* Write-Checker
*/
bool CheckerDDR3New::collidesOnDataStrobe_WR(ScheduledCommand &write) const
{
for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands)
{
if (collidesWithStrobeCommand_WR(write, strobeCommand))
return true;
}
return false;
}
bool CheckerDDR3New::collidesWithStrobeCommand_WR(ScheduledCommand &write,
ScheduledCommand &strobeCommand) const
{
if (strobeCommand.getCommand() == Command::WR || strobeCommand.getCommand() == Command::WRA)
{
return getDistance(write.getStart(),
strobeCommand.getStart()) < CasToCas(strobeCommand, write);
}
else if (strobeCommand.getCommand() == Command::RD || strobeCommand.getCommand() == Command::RDA)
{
if (strobeCommand.getStart() >= write.getStart())
return getDistance(write.getStart(),
strobeCommand.getStart()) < writeToRead(write, strobeCommand);
else
return getDistance(strobeCommand.getStart(),
write.getStart()) < readToWrite(strobeCommand, write);
}
else
{
reportFatal("CheckerDDR3New", "Invalid strobeCommand in data strobe commands "
+ commandToString(strobeCommand.getCommand()));
return true;
}
}
sc_time CheckerDDR3New::readToWrite(ScheduledCommand &read, ScheduledCommand &write) const
{
sc_assert(read.getCommand() == Command::RD
|| read.getCommand() == Command::RDA);
sc_assert(write.getCommand() == Command::WR
|| write.getCommand() == Command::WRA);
return memSpec->tRL + memSpec->getReadAccessTime() - memSpec->tWL + memSpec->clk * 2;
}

24
DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h
View File

@@ -24,30 +24,10 @@ private:
MemSpecDDR3 *memSpec;
//Activate
bool satsfiesACTtoACTdifferentBank(ScheduledCommand &command) const;
bool satisfiesNActivateWindow(ScheduledCommand &command) const;
//PowerDown
sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const;
//used for Read
bool collidesOnDataStrobe_RD(ScheduledCommand &read) const;
bool collidesWithStrobeCommand_RD(ScheduledCommand &read,
ScheduledCommand &strobeCommand) const;
//Write
bool collidesOnDataStrobe_WR(ScheduledCommand &write) const;
bool collidesWithStrobeCommand_WR(ScheduledCommand &write,
ScheduledCommand &strobeCommand) const;
//handles WR->RD
sc_time writeToRead(ScheduledCommand &write, ScheduledCommand &read) const;
//RD->WR
sc_time readToWrite(ScheduledCommand &read, ScheduledCommand &write) const;
//CasToCas Commands (WR->WR)(RD->RD)
sc_time CasToCas(ScheduledCommand &firstCAS, ScheduledCommand &secondCAS) const;
//PowerDown TODO: Implement this method?
//sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const;
const Configuration &config;
ControllerState &state;//TODO make const

8
DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp
View File

@@ -75,10 +75,10 @@ void ReadChecker::delayToSatisfyConstraints(ScheduledCommand &command) const
bool ReadChecker::collidesOnDataStrobe(ScheduledCommand &read) const
{
for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) {
if (collidesWithStrobeCommand(read, strobeCommand))
return true;
}
// for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) {
// if (collidesWithStrobeCommand(read, strobeCommand))
// return true;
// }
return false;
}

8
DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp
View File

@@ -75,10 +75,10 @@ void WriteChecker::delayToSatisfyConstraints(ScheduledCommand &command) const
bool WriteChecker::collidesOnDataStrobe(ScheduledCommand &write) const
{
for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) {
if (collidesWithStrobeCommand(write, strobeCommand))
return true;
}
// for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) {
// if (collidesWithStrobeCommand(write, strobeCommand))
// return true;
// }
return false;
}