diff --git a/DRAMSys/library/src/controller/ControllerState.cpp b/DRAMSys/library/src/controller/ControllerState.cpp index 8c299037..fb0f7af6 100644 --- a/DRAMSys/library/src/controller/ControllerState.cpp +++ b/DRAMSys/library/src/controller/ControllerState.cpp @@ -106,18 +106,6 @@ void ControllerState::change(const ScheduledCommand &scheduledCommand) switch (scheduledCommand.getCommand()) { - case Command::RD: - lastDataStrobeCommands.emplace_back(scheduledCommand); - break; - case Command::RDA: - lastDataStrobeCommands.emplace_back(scheduledCommand); - break; - case Command::WR: - lastDataStrobeCommands.emplace_back(scheduledCommand); - break; - case Command::WRA: - lastDataStrobeCommands.emplace_back(scheduledCommand); - break; case Command::ACTB: lastActivatesB.emplace(scheduledCommand.getStart(), scheduledCommand); break; @@ -132,13 +120,7 @@ void ControllerState::change(const ScheduledCommand &scheduledCommand) void ControllerState::cleanUp(sc_time time) { bus.cleanUpSlots(time); - vector tmp; - for (ScheduledCommand &command : lastDataStrobeCommands) { - if (command.getEnd() >= time - || getDistance(command.getEnd(), time) <= config->memSpec->tDataStrobeHistory()) - tmp.push_back(command); - } - lastDataStrobeCommands = tmp; + if (time >= config->memSpec->tActHistory()) lastActivates.erase(lastActivates.begin(), lastActivates.lower_bound(time - config->memSpec->tActHistory())); diff --git a/DRAMSys/library/src/controller/ControllerState.h b/DRAMSys/library/src/controller/ControllerState.h index ea7c0e22..5406386f 100644 --- a/DRAMSys/library/src/controller/ControllerState.h +++ b/DRAMSys/library/src/controller/ControllerState.h @@ -60,15 +60,13 @@ public: void cleanUp(sc_time time); //used by the various checkers - std::map > - lastScheduledByCommandAndBank; + std::map> lastScheduledByCommandAndBank; // TODO: remove //std::map lastScheduledByCommand; //std::map lastScheduledByBank; //ScheduledCommand lastScheduled; Slots bus; - std::vector lastDataStrobeCommands; std::map lastActivates; std::map lastActivatesB; diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp index 58cc1437..8f1722fc 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp @@ -441,11 +441,11 @@ bool CheckerDDR3::satisfies_nActivateWindow(ScheduledCommand &command) const bool CheckerDDR3::collidesOnDataStrobe_RD(ScheduledCommand &read) const { - for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) - { - if (collidesWithStrobeCommand_RD(read, strobeCommand)) - return true; - } +// for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) +// { +// if (collidesWithStrobeCommand_RD(read, strobeCommand)) +// return true; +// } return false; } @@ -515,11 +515,11 @@ sc_time CheckerDDR3::CasToCas(ScheduledCommand &firstCAS, ScheduledCommand &seco bool CheckerDDR3::collidesOnDataStrobe_WR(ScheduledCommand &write) const { - for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) - { - if (collidesWithStrobeCommand_WR(write, strobeCommand)) - return true; - } +// for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) +// { +// if (collidesWithStrobeCommand_WR(write, strobeCommand)) +// return true; +// } return false; } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp index 42988069..6f4c62f3 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp @@ -165,22 +165,6 @@ sc_time CheckerDDR3New::delayToSatisfyConstraints(Command command, Bank bank) return (minTimeToWait - sc_time_stamp()); } -/* -* ActivateChecker -*/ -bool CheckerDDR3New::satsfiesACTtoACTdifferentBank(ScheduledCommand &command) const -{ - for (auto act : state.lastActivates) - { - sc_time time = act.first; - if ((time < command.getStart() && command.getStart() - time < memSpec->tRRD) - || (command.getStart() <= time && time - command.getStart() < memSpec->tRRD)) - return false; - } - return true; - -} - bool CheckerDDR3New::satisfiesNActivateWindow(ScheduledCommand &command) const { /* @@ -206,119 +190,3 @@ bool CheckerDDR3New::satisfiesNActivateWindow(ScheduledCommand &command) const } return true; } - - -/* - * Read-Checker -*/ - -bool CheckerDDR3New::collidesOnDataStrobe_RD(ScheduledCommand &read) const -{ - for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) - { - if (collidesWithStrobeCommand_RD(read, strobeCommand)) - return true; - } - return false; -} - -bool CheckerDDR3New::collidesWithStrobeCommand_RD(ScheduledCommand &read, - ScheduledCommand &strobeCommand) const -{ - if (strobeCommand.getCommand() == Command::RD || strobeCommand.getCommand() == Command::RDA) - { - return getDistance(read.getStart(), - strobeCommand.getStart()) < CasToCas(strobeCommand, read); - } - else if (strobeCommand.getCommand() == Command::WR || strobeCommand.getCommand() == Command::WRA) - { - if (strobeCommand.getStart() >= read.getStart()) - return getDistance(read.getStart(), - strobeCommand.getStart()) < readToWrite(read, strobeCommand); - else - return getDistance(strobeCommand.getStart(), - read.getStart()) < writeToRead(strobeCommand, read); - } else { - reportFatal("CheckerDDR3New", - "Invalid strobeCommand in data strobe commands " + commandToString( - strobeCommand.getCommand())); - return true; - } - return false; -} - -sc_time CheckerDDR3New::writeToRead(ScheduledCommand &write, ScheduledCommand &read) const -{ - sc_assert(read.getCommand() == Command::RD || read.getCommand() == Command::RDA); - sc_assert(write.getCommand() == Command::WR || write.getCommand() == Command::WRA); - - return memSpec->tWL + memSpec->getWriteAccessTime() + memSpec->tWTR; -} - -/* CAS-CAS */ - -sc_time CheckerDDR3New::CasToCas(ScheduledCommand &firstCAS, ScheduledCommand &secondCAS) const -{ - if (firstCAS.getCommand() == Command::RD || firstCAS.getCommand() == Command::RDA) - { - if (secondCAS.getCommand() == Command::RD || secondCAS.getCommand() == Command::RDA) - return std::max(memSpec->tCCD, memSpec->getReadAccessTime()); - } - else if (firstCAS.getCommand() == Command::WR || firstCAS.getCommand() == Command::WRA) - { - if (secondCAS.getCommand() == Command::WR || secondCAS.getCommand() == Command::WRA) - return std::max(memSpec->tCCD, memSpec->getWriteAccessTime()); - } - SC_REPORT_FATAL("CasToCas", "Exception reached"); - return SC_ZERO_TIME; -} - -/* -* Write-Checker -*/ - -bool CheckerDDR3New::collidesOnDataStrobe_WR(ScheduledCommand &write) const -{ - for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) - { - if (collidesWithStrobeCommand_WR(write, strobeCommand)) - return true; - } - return false; -} - -bool CheckerDDR3New::collidesWithStrobeCommand_WR(ScheduledCommand &write, - ScheduledCommand &strobeCommand) const -{ - if (strobeCommand.getCommand() == Command::WR || strobeCommand.getCommand() == Command::WRA) - { - return getDistance(write.getStart(), - strobeCommand.getStart()) < CasToCas(strobeCommand, write); - } - else if (strobeCommand.getCommand() == Command::RD || strobeCommand.getCommand() == Command::RDA) - { - if (strobeCommand.getStart() >= write.getStart()) - return getDistance(write.getStart(), - strobeCommand.getStart()) < writeToRead(write, strobeCommand); - else - return getDistance(strobeCommand.getStart(), - write.getStart()) < readToWrite(strobeCommand, write); - } - else - { - reportFatal("CheckerDDR3New", "Invalid strobeCommand in data strobe commands " - + commandToString(strobeCommand.getCommand())); - return true; - } -} - - -sc_time CheckerDDR3New::readToWrite(ScheduledCommand &read, ScheduledCommand &write) const -{ - sc_assert(read.getCommand() == Command::RD - || read.getCommand() == Command::RDA); - sc_assert(write.getCommand() == Command::WR - || write.getCommand() == Command::WRA); - - return memSpec->tRL + memSpec->getReadAccessTime() - memSpec->tWL + memSpec->clk * 2; -} diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h index 349b250d..a658da60 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h @@ -24,30 +24,10 @@ private: MemSpecDDR3 *memSpec; //Activate - bool satsfiesACTtoACTdifferentBank(ScheduledCommand &command) const; bool satisfiesNActivateWindow(ScheduledCommand &command) const; - //PowerDown - sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; - - //used for Read - bool collidesOnDataStrobe_RD(ScheduledCommand &read) const; - bool collidesWithStrobeCommand_RD(ScheduledCommand &read, - ScheduledCommand &strobeCommand) const; - - //Write - bool collidesOnDataStrobe_WR(ScheduledCommand &write) const; - bool collidesWithStrobeCommand_WR(ScheduledCommand &write, - ScheduledCommand &strobeCommand) const; - - //handles WR->RD - sc_time writeToRead(ScheduledCommand &write, ScheduledCommand &read) const; - - //RD->WR - sc_time readToWrite(ScheduledCommand &read, ScheduledCommand &write) const; - - //CasToCas Commands (WR->WR)(RD->RD) - sc_time CasToCas(ScheduledCommand &firstCAS, ScheduledCommand &secondCAS) const; + //PowerDown TODO: Implement this method? + //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; const Configuration &config; ControllerState &state;//TODO make const diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp index 769624cc..d47dee54 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp @@ -75,10 +75,10 @@ void ReadChecker::delayToSatisfyConstraints(ScheduledCommand &command) const bool ReadChecker::collidesOnDataStrobe(ScheduledCommand &read) const { - for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) { - if (collidesWithStrobeCommand(read, strobeCommand)) - return true; - } +// for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) { +// if (collidesWithStrobeCommand(read, strobeCommand)) +// return true; +// } return false; } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp index e9136ef7..df8fc8ed 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp @@ -75,10 +75,10 @@ void WriteChecker::delayToSatisfyConstraints(ScheduledCommand &command) const bool WriteChecker::collidesOnDataStrobe(ScheduledCommand &write) const { - for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) { - if (collidesWithStrobeCommand(write, strobeCommand)) - return true; - } +// for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) { +// if (collidesWithStrobeCommand(write, strobeCommand)) +// return true; +// } return false; }