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a05b0ed610
Removed RowBufferState in ControllerState.
2019-07-28 20:57:48 +02:00
e0743b71d6
Small improvement in ControllerNew (redundant event triggers), renaming in ControllerState.
2019-07-28 20:45:03 +02:00
733525e787
Included command mux which selects the oldest payload and a command mux interface.
2019-07-27 21:12:22 +02:00
215790a931
Created different schedulers (Fifo and FrFcfs) and a scheduler interface.
2019-07-27 19:24:09 +02:00
c4c2640594
Moved event trigger out of BankMachine.
2019-07-26 16:28:22 +02:00
3f913b5c16
Arbiter now assigns each payload an ID for transaction order decision in CommandMux.
2019-07-26 15:48:58 +02:00
f2ab2fe3ee
Included first test for CommandMux.
2019-07-25 16:40:03 +02:00
38a21088a0
Merge branch 'master' into DRAMSys4.0_ctrl
2019-07-25 13:47:57 +02:00
7304055a22
Merge branch 'googletest_merge2' into 'master'
2019-07-25 12:02:33 +02:00
a303f242e6
Included googletest and subproject for unit tests.
2019-07-25 11:49:18 +02:00
7bd0950e1e
Some minor changes.
2019-07-23 21:30:29 +02:00
e1e53b5c2e
Moved parts of logic from CommandMux::selectCommand to controlMethod, moved commandFinishedTime from BMs to Controller.
2019-07-23 16:20:38 +02:00
1e8b8e37ea
Moved if statements from inner methods to controllerMethod().
2019-07-23 15:10:19 +02:00
e7552f6916
Code cleanup.
2019-07-23 14:30:01 +02:00
0d0c7415b2
Fixed clk cycle waiting for fifo strict transaction order.
2019-07-23 14:13:51 +02:00
6aa2533edd
New controller is working.
2019-07-22 20:31:17 +02:00
f69771e7be
Simulation is running to the end, results may still be wrong.
2019-07-22 17:59:51 +02:00
1ce8996ece
Some bugs are fixed, still not running.
2019-07-22 01:53:18 +02:00
ef011ad52c
Ready for debugging.
2019-07-22 00:23:12 +02:00
9204a88a28
Included some functionality, included scheduler.
2019-07-20 23:32:37 +02:00
cd5b5cb423
Included new controller classes.
2019-07-20 15:53:30 +02:00
41e2db0b5a
Removed refresh and power down.
2019-07-19 10:29:14 +02:00
f43ea71e95
Minor changes in new timing checker.
2019-07-16 15:52:02 +02:00
be83ad01cb
Included remaining commands.
2019-07-11 15:22:09 +02:00
9be64edaa9
Added commands ACT, PRE, PREA, RD, RDA, WR, WRA, PDEA, PDEP to new timing checker.
2019-07-10 15:55:45 +02:00
3e4e8e9408
Included new timing checker for DDR3.
2019-07-09 15:52:09 +02:00
cb393b8abf
Renaming of commands, TODOs in timing checkers.
2019-07-05 16:17:52 +02:00
37b2dc9e4d
Renaming of commands according to DRAMml.
2019-07-04 10:13:19 +02:00
34626448bb
RefMode (tRFC) is now only configurable during initialization.
2019-07-02 16:25:43 +02:00
41cc447d86
Included timing parameters for RGR.
2019-07-02 14:25:53 +02:00
ffdc67945a
Removed specific DRAMPower configuration in DRAMs.
2019-07-01 15:00:01 +02:00
50f90176a0
Included specific timing parameters for different DRAMs.
2019-07-01 11:16:36 +02:00
3b509a7c17
Marked old timing parameters with "_old" for inclusion of new ones without conflicts.
2019-07-01 10:23:30 +02:00
9b8729c58b
Bugfix: nbrOfRanks is only part of some memspecs for WideIO.
2019-06-28 17:53:52 +02:00
409e49f044
Bugfix: call loadCommons() only after creating a memSpec object.
2019-06-28 17:36:51 +02:00
21adf2ac70
Moved some timings to loadCommons().
2019-06-28 16:26:46 +02:00
a5fb1327a1
Renaming of timings.
2019-06-28 15:14:47 +02:00
7da2aacfa3
Separate constructors for each DRAM type.
2019-06-28 14:40:07 +02:00
72152bca8b
Included GenericController for later verilator inclusion.
2019-06-28 14:10:09 +02:00
ac4e4c7783
Moved specific timing calculation functions to MemSpecs.
2019-06-27 16:02:24 +02:00
e462287d7c
Split up timings.
2019-06-25 22:40:18 +02:00
2d08d48f81
Bugfix: Wrong header included. Removed redundant main function.
2019-06-25 19:49:03 +02:00
51e6ebfed0
CheckerDDR3 works, timings may still be wrong.
2019-06-25 15:56:22 +02:00
c0d6231e26
Adapted timings for CheckerDDR3.
2019-06-25 14:24:39 +02:00
4c4119803e
Included CheckerDDR3.
2019-06-25 13:37:49 +02:00
70b9ec8517
Merge branch 'DRAMSys4.0_dev' into 'master'
2019-06-24 16:10:33 +02:00
188c552d5f
Merge remote-tracking branch 'origin/DRAMSys4.0_merge' into DRAMSys4.0_dev
2019-06-24 14:13:05 +02:00
d07a775697
Annotations for different MemSpecs.
2019-06-24 13:59:57 +02:00
45b05c5cf0
Created DramWideIO, removed powerAnalysis switch.
2019-06-24 11:59:59 +02:00
21c243b9d3
Replaced "BaseDram::" with "this->" to access members of the base class.
2019-06-23 21:20:21 +02:00
f8baef57c6
Adapting current DRAM to new structure.
2019-06-23 20:53:08 +02:00
cb7b5b585a
NOT RUNNING! Adapting current DRAM to new structure.
2019-06-23 19:10:28 +02:00
cff2455be2
Bugfix for failing tests: missing renaming.
2019-06-22 22:08:00 +02:00
c3da6912a9
Further renaming of schedulers.
2019-06-22 21:49:18 +02:00
882a0eaa90
Revert "Included templates for new DRAMs."
2019-06-22 20:50:07 +02:00
27fed22003
Revert "Templating for DRAMs is working."
2019-06-22 20:49:57 +02:00
d69cb555ac
Templating for DRAMs is working.
2019-06-19 13:59:01 +02:00
8f0e59c85e
Included templates for new DRAMs.
2019-06-19 11:16:38 +02:00
388a2623af
Preparation for merge with master.
2019-06-18 10:52:04 +02:00
b901c32f2a
Merge branch 'master' into DRAMSys4.0_dev
2019-06-18 10:15:54 +02:00
7540388cfe
Preparation for specific memspecs (member memSpec is now dynamic).
2019-06-17 19:31:21 +02:00
a97a20b148
Added specific MemSpecs, commit not running!
2019-06-17 17:41:46 +02:00
9f253267d3
Merge branch 'bw_calculation_move' into 'master'
2019-06-17 10:54:12 +02:00
bf1a9dc47d
Moved bandwidth calculation from Dram to Controller.
2019-06-16 21:12:33 +02:00
24a8f7f483
Code refactoring.
2019-06-13 23:41:22 +02:00
abcd2a910b
Renaming files (Commit 2 of 2)
2019-06-12 20:25:38 +02:00
cd67d638d4
Renaming files (Commit 1 of 2)
2019-06-12 19:28:31 +02:00
761bd8946f
Renaming files (Commit 2 of 2)
2019-06-12 16:22:45 +02:00
20797f61f5
Renaming files (Commit 1 of 2)
2019-06-12 16:21:00 +02:00
cea3b26bd0
Bugfix (incomplete renaming).
2019-06-12 01:49:27 +02:00
6bc5f6ead3
Removed unused files in folder scheduler.
2019-06-12 00:54:55 +02:00
193893c23b
Renaming of schedulers.
2019-06-12 00:54:02 +02:00
5ac2701d2c
Fix commit for renaming issue.
2019-06-12 00:52:28 +02:00
62c5ec720f
Code refactoring.
2019-06-11 23:14:07 +02:00
e7704a74e6
Code refactoring.
2019-06-11 23:11:39 +02:00
02803de97c
Code refactoring.
2019-06-11 23:10:45 +02:00
4454b82363
No changes, some TODOs for future work.
2019-06-10 00:52:26 +02:00
84bd62a781
No changes, some TODOs for future work.
2019-06-05 16:21:26 +02:00
b90784f54c
Created cpp file for arbiter. Removed redundant routing table in arbiter.
2019-06-04 15:51:35 +02:00
fb781882f7
Included doxygen config.
2019-06-03 15:42:50 +02:00
b96121b4f8
improve
2019-05-31 16:44:19 +02:00
5b46cbebe0
improvement
2019-05-28 14:04:48 +02:00
963d65aecb
improvement
2019-05-28 13:47:42 +02:00
de8a546584
improvement
2019-05-28 12:22:30 +02:00
6ee31fb9d6
improvement
2019-05-28 12:05:33 +02:00
15890f96d3
improvement
2019-05-28 09:36:59 +02:00
503f974037
improvement
2019-05-22 10:06:31 +02:00
e955c86269
improvement
2019-05-22 10:02:30 +02:00
9b7d14b353
improvement
2019-05-10 07:38:38 +02:00
b37bdf3734
doc updated
2019-04-30 08:58:21 +02:00
861478e2b6
improvement
2019-04-29 17:55:56 +02:00
7a5ee0e52e
doc updated
2019-04-29 14:27:22 +02:00
205736173e
doc updated
2019-04-15 08:27:47 +02:00
81e81a8604
doc update
2019-04-15 08:14:08 +02:00
d21088a18f
Improvement
2019-04-12 15:00:32 +02:00
f45a168c48
Merge branch '226-generate-and-combine-the-coverage-data-of-the-tests-correctly' into 'master'
2019-03-01 10:37:41 +01:00
9a666b198f
Merge branch '215-begin_resp-exclusion-rule-violation-when-using-closepagepolicy' into 'master'
2019-03-01 10:32:53 +01:00
e4b1884c05
Resolve "BEGIN_RESP Exclusion Rule violation when using ClosePagePolicy"
2019-03-01 10:32:53 +01:00
58fb41fef7
Redefine directory for .gcda files and adjust path to source code files
2019-02-28 17:34:17 +01:00
6bd1029d9e
script updated
2019-02-26 16:00:41 +01:00
Lukas Steiner