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Annotations for different MemSpecs.

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This commit is contained in:
Lukas Steiner (2)
2019-06-24 13:59:57 +02:00
parent 45b05c5cf0
commit d07a775697
3 changed files with 69 additions and 68 deletions
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134
DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp
View File

@@ -177,17 +177,17 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *memspec)
XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec");
config.memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks");
config.memSpec->NumberOfBankGroups = 1;
config.memSpec->NumberOfBankGroups = 1;
config.memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
config.memSpec->BurstLength = queryUIntParameter(architecture, "burstLength");
config.memSpec->nActivate = 4;
config.memSpec->nActivate = 4;
config.memSpec->DataRate = queryUIntParameter(architecture, "dataRate");
config.memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
config.memSpec->NumberOfColumns = queryUIntParameter(architecture,
"nbrOfColumns");
config.memSpec->bitWidth = queryUIntParameter(architecture, "width");
config.memSpec->DLL = true;
config.memSpec->termination = true;
config.memSpec->DLL = true;
config.memSpec->termination = true;
//MemTimings
XMLElement *timings = memspec->FirstChildElement("memtimingspec");
@@ -198,29 +198,29 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *memspec)
config.memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
config.memSpec->tRC = clk * queryUIntParameter(timings, "RC");
config.memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD");
config.memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD");
config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD");
config.memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD");
config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD");
config.memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD");
config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD");
config.memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD");
config.memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
config.memSpec->tNAW = clk * queryUIntParameter(timings, "FAW");
config.memSpec->tNAW = clk * queryUIntParameter(timings, "FAW");
config.memSpec->tRL = clk * queryUIntParameter(timings, "RL");
config.memSpec->tWL = clk * queryUIntParameter(timings, "WL");
config.memSpec->tWR = clk * queryUIntParameter(timings, "WR");
config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR");
config.memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR");
config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR");
config.memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR");
config.memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
config.memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
config.memSpec->tXP = clk * queryUIntParameter(timings, "XP");
config.memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL");
config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS");
config.memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XSDLL");
config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS");
config.memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XSDLL");
config.memSpec->tAL = clk * queryUIntParameter(timings, "AL");
config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
config.memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
config.memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
config.memSpec->refreshTimings.clear();
config.memSpec->refreshTimings.clear();
for (unsigned int i = 0; i < config.memSpec->NumberOfBanks; ++i) {
config.memSpec->refreshTimings[Bank(i)] = RefreshTiming(config.memSpec->tRFC,
config.memSpec->tREFI);
@@ -229,7 +229,7 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *memspec)
// Currents and Volatages: TODO Check if this is correct.
XMLElement *powers = memspec->FirstChildElement("mempowerspec");
config.memSpec->iDD0 = queryDoubleParameter(powers, "idd0");
config.memSpec->iDD02 = 0;
config.memSpec->iDD02 = 0;
config.memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0");
config.memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1");
config.memSpec->iDD2N = queryDoubleParameter(powers, "idd2n");
@@ -240,9 +240,9 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *memspec)
config.memSpec->iDD4W = queryDoubleParameter(powers, "idd4w");
config.memSpec->iDD5 = queryDoubleParameter(powers, "idd5");
config.memSpec->iDD6 = queryDoubleParameter(powers, "idd6");
config.memSpec->iDD62 = 0;
config.memSpec->iDD62 = 0;
config.memSpec->vDD = queryDoubleParameter(powers, "vdd");
config.memSpec->vDD2 = 0;
config.memSpec->vDD2 = 0;
}
void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *memspec)
@@ -255,14 +255,14 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *memspec)
"nbrOfBankGroups");
config.memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
config.memSpec->BurstLength = queryUIntParameter(architecture, "burstLength");
config.memSpec->nActivate = 4;
config.memSpec->nActivate = 4;
config.memSpec->DataRate = queryUIntParameter(architecture, "dataRate");
config.memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
config.memSpec->NumberOfColumns = queryUIntParameter(architecture,
"nbrOfColumns");
config.memSpec->bitWidth = queryUIntParameter(architecture, "width");
config.memSpec->DLL = true;
config.memSpec->termination = true;
config.memSpec->DLL = true;
config.memSpec->termination = true;
//MemTimings
XMLElement *timings = memspec->FirstChildElement("memtimingspec");
@@ -278,7 +278,7 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *memspec)
config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD_S");
config.memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD_L");
config.memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
config.memSpec->tNAW = clk * queryUIntParameter(timings, "FAW");
config.memSpec->tNAW = clk * queryUIntParameter(timings, "FAW");
config.memSpec->tRL = clk * queryUIntParameter(timings, "RL");
config.memSpec->tWL = clk * queryUIntParameter(timings, "WL");
config.memSpec->tWR = clk * queryUIntParameter(timings, "WR");
@@ -288,8 +288,8 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *memspec)
config.memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
config.memSpec->tXP = clk * queryUIntParameter(timings, "XP");
config.memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL");
config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS");
config.memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XSDLL");
config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS");
config.memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XSDLL");
config.memSpec->tAL = clk * queryUIntParameter(timings, "AL");
config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
config.memSpec->tRFC2 = clk * queryUIntParameter(timings, "RFC2");
@@ -324,60 +324,60 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *memspec)
config.memSpec->vDD2 = queryDoubleParameter(powers, "vdd2");
}
// TODO: fix this for LPDDR4
// TODO: change timings for LPDDR4
void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *memspec)
{
//MemArchitecture:
XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec");
config.memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks");
config.memSpec->NumberOfBankGroups = 1;
config.memSpec->NumberOfBankGroups = 1;
config.memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
config.memSpec->BurstLength = queryUIntParameter(architecture, "burstLength");
config.memSpec->nActivate = 4;
config.memSpec->nActivate = 4;
config.memSpec->DataRate = queryUIntParameter(architecture, "dataRate");
config.memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
config.memSpec->NumberOfColumns = queryUIntParameter(architecture,
"nbrOfColumns");
config.memSpec->bitWidth = queryUIntParameter(architecture, "width");
config.memSpec->DLL = false; // TODO: Correct?
config.memSpec->termination = true; // TODO: Correct?
config.memSpec->DLL = false; // TODO: Correct?
config.memSpec->termination = true; // TODO: Correct?
//MemTimings
XMLElement *timings = memspec->FirstChildElement("memtimingspec");
config.memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz");
config.memSpec->clk = FrequencyToClk(config.memSpec->clkMHz);
sc_time clk = config.memSpec->clk;
config.memSpec->tRP = clk * queryUIntParameter(timings, "RPPB");
config.memSpec->tRP = clk * queryUIntParameter(timings, "RPPB");
config.memSpec->tRPAB = clk * queryUIntParameter(timings, "RPAB");
config.memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
config.memSpec->tRC = clk * queryUIntParameter(timings, "RC");
config.memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD");
config.memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD");
config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD");
config.memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD");
config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD");
config.memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD");
config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD");
config.memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD");
config.memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
config.memSpec->tNAW = clk * queryUIntParameter(timings, "FAW");
config.memSpec->tNAW = clk * queryUIntParameter(timings, "FAW");
config.memSpec->tRL = clk * queryUIntParameter(timings, "RL");
config.memSpec->tWL = clk * queryUIntParameter(timings, "WL");
config.memSpec->tWR = clk * queryUIntParameter(timings, "WR");
config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR");
config.memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR");
config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR");
config.memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR");
config.memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
config.memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
config.memSpec->tXP = clk * queryUIntParameter(timings, "XP");
config.memSpec->tXPDLL = clk * queryUIntParameter(timings, "XP");
config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS");
config.memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XS");
config.memSpec->tXPDLL = clk * queryUIntParameter(timings, "XP");
config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS");
config.memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XS");
config.memSpec->tAL = clk * queryUIntParameter(timings, "AL");
config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFCAB");
// TODO: config.memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB");
config.memSpec->tREFI = clk * queryUIntParameter(timings, "REFIAB");
// TODO: config.memSpec->tREFIPB = clk * queryUIntParameter(timings, "RFCPB");
config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFCAB");
// TODO: config.memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB");
config.memSpec->tREFI = clk * queryUIntParameter(timings, "REFIAB");
// TODO: config.memSpec->tREFIPB = clk * queryUIntParameter(timings, "RFCPB");
config.memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
config.memSpec->refreshTimings.clear();
config.memSpec->refreshTimings.clear();
for (unsigned int i = 0; i < config.memSpec->NumberOfBanks; ++i) {
config.memSpec->refreshTimings[Bank(i)] = RefreshTiming(config.memSpec->tRFC,
config.memSpec->tREFI);
@@ -387,11 +387,11 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *memspec)
XMLElement *powers = memspec->FirstChildElement("mempowerspec");
config.memSpec->iDD0 = queryDoubleParameter(powers, "idd0");
config.memSpec->iDD02 = queryDoubleParameter(powers, "idd02");
config.memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p");
config.memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p2");
config.memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p");
config.memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p2");
config.memSpec->iDD2N = queryDoubleParameter(powers, "idd2n");
config.memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p");
config.memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p2");
config.memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p");
config.memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p2");
config.memSpec->iDD3N = queryDoubleParameter(powers, "idd3n");
config.memSpec->iDD4R = queryDoubleParameter(powers, "idd4r");
config.memSpec->iDD4W = queryDoubleParameter(powers, "idd4w");
@@ -408,17 +408,17 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec)
XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec");
config.memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks");
config.memSpec->NumberOfBankGroups = 1;
config.memSpec->NumberOfRanks = 1;
config.memSpec->NumberOfBankGroups = 1;
config.memSpec->NumberOfRanks = 1;
config.memSpec->BurstLength = queryUIntParameter(architecture, "burstLength");
config.memSpec->nActivate = 2;
config.memSpec->nActivate = 2;
config.memSpec->DataRate = queryUIntParameter(architecture, "dataRate");
config.memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
config.memSpec->NumberOfColumns = queryUIntParameter(architecture,
"nbrOfColumns");
config.memSpec->bitWidth = queryUIntParameter(architecture, "width");
config.memSpec->DLL = false;
config.memSpec->termination = false;
config.memSpec->DLL = false;
config.memSpec->termination = false;
//MemTimings
XMLElement *timings = memspec->FirstChildElement("memtimingspec");
@@ -428,29 +428,29 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec)
config.memSpec->tRP = clk * queryUIntParameter(timings, "RP");
config.memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
config.memSpec->tRC = clk * queryUIntParameter(timings, "RC");
config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD");
config.memSpec->tRRD_L = config.memSpec->tRRD_S;
config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD");
config.memSpec->tCCD_L = config.memSpec->tCCD_S;
config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD");
config.memSpec->tRRD_L = config.memSpec->tRRD_S;
config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD");
config.memSpec->tCCD_L = config.memSpec->tCCD_S;
config.memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
config.memSpec->tNAW = clk * queryUIntParameter(timings, "TAW");
config.memSpec->tNAW = clk * queryUIntParameter(timings, "TAW");
config.memSpec->tRL = clk * queryUIntParameter(timings, "RL");
config.memSpec->tWL = clk * queryUIntParameter(timings, "WL");
config.memSpec->tWR = clk * queryUIntParameter(timings, "WR");
config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR");
config.memSpec->tWTR_L = config.memSpec->tWTR_S;
config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR");
config.memSpec->tWTR_L = config.memSpec->tWTR_S;
config.memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
config.memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
config.memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
config.memSpec->tXP = clk * queryUIntParameter(timings, "XP");
config.memSpec->tXPDLL = config.memSpec->tXP;
config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS");
config.memSpec->tXSRDLL = config.memSpec->tXSR;
config.memSpec->tAL = clk * queryUIntParameter(timings, "AL");
config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
config.memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
config.memSpec->tXPDLL = config.memSpec->tXP;
config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS");
config.memSpec->tXSRDLL = config.memSpec->tXSR;
config.memSpec->tAL = clk * queryUIntParameter(timings, "AL");
config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
config.memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
config.memSpec->refreshTimings.clear();
config.memSpec->refreshTimings.clear();
for (unsigned int i = 0; i < config.memSpec->NumberOfBanks; ++i) {
config.memSpec->refreshTimings[Bank(i)] = RefreshTiming(config.memSpec->tRFC,
config.memSpec->tREFI);

1
DRAMSys/library/src/simulation/Dram.cpp
View File

@@ -56,7 +56,6 @@
#include "../common/protocol.h"
#include "../common/utils.h"
#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../error/errormodel.h"
using namespace std;
using namespace tlm;

2
DRAMSys/library/src/simulation/DramWideIO.cpp
View File

@@ -38,6 +38,8 @@
#include <systemc>
#include <tlm>
#include "Dram.h"
#include "../controller/core/configuration/Configuration.h"
#include "../error/errormodel.h"
using namespace tlm;