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Code refactoring.

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This commit is contained in:
Lukas Steiner
2019-06-11 23:10:45 +02:00
parent 4454b82363
commit 02803de97c
7 changed files with 56 additions and 33 deletions
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52
DRAMSys/library/src/controller/Controller.cpp
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@@ -451,47 +451,59 @@ void Controller::dramPEQCallback(tlm_generic_payload &payload,
printDebugMessage("Received " + phaseNameToString(phase) + " on bank " +
to_string(bank.ID()) + " from DRAM");
if (phase == END_RD || phase == END_WR) {
if(responseQueue.empty()) {
if (phase == END_RD || phase == END_WR)
{
if(responseQueue.empty())
sendToFrontend(payload, BEGIN_RESP, SC_ZERO_TIME);
}
responseQueue.push(&payload);
} else if (phase == END_RDA || phase == END_WRA) {
if(responseQueue.empty()) {
}
else if (phase == END_RDA || phase == END_WRA)
{
if(responseQueue.empty())
sendToFrontend(payload, BEGIN_RESP, SC_ZERO_TIME);
}
responseQueue.push(&payload);
scheduleNextFromScheduler(bank);
} else if (phase == END_REFA) {
}
else if (phase == END_REFA)
{
printDebugMessage("Finished auto refresh on all banks ");
bool sleepy = true;
for (Bank bank : controllerCore->getBanks()) {
if (numberOfPayloadsInSystem[bank] != 0) {
for (Bank bank : controllerCore->getBanks())
{
if (numberOfPayloadsInSystem[bank] != 0)
{
sleepy = false;
scheduleNextFromScheduler(bank);
}
}
if (sleepy == true) {
if (sleepy == true)
controllerCore->powerDownManager->sleep(0, sc_time_stamp());
}
} else if (phase == END_REFB) {
}
else if (phase == END_REFB)
{
printDebugMessage("Finished auto refresh on bank " + to_string(bank.ID()));
if (numberOfPayloadsInSystem[bank] == 0) {
if (numberOfPayloadsInSystem[bank] == 0)
controllerCore->powerDownManager->sleep(bank, sc_time_stamp());
} else {
else
scheduleNextFromScheduler(bank);
}
scheduleNextFromScheduler(bank);
} else if (containsPhase(phase, {END_PREB, END_PRE, END_ACTB, END_ACT})) {
scheduleNextFromScheduler(bank);
}
else if (phase == END_PRE_ALL) {
else if (containsPhase(phase, {END_PREB, END_PRE, END_ACTB, END_ACT}))
{
scheduleNextFromScheduler(bank);
}
else if (phase == END_PRE_ALL)
{
// No need to trigger anything for a END_PRE_ALL. It is followed by a AUTO_REFRESH anyway (in our current
// scheduler implementation)
} else {
}
else
{
string str =
string("DRAM PEQ in controller wrapper was triggered with unsupported phase ")
+ phaseNameToString(phase);

4
DRAMSys/library/src/controller/Controller.h
View File

@@ -145,9 +145,9 @@ protected:
//Scheduler* scheduler;
IScheduler *scheduler;
std::map<Bank, int> numberOfPayloadsInSystem;
std::vector<gp * > refreshCollisionRequets;
std::vector<gp *> refreshCollisionRequets;
tlm::tlm_generic_payload *backpressure = NULL;
std::queue<gp * > responseQueue;
std::queue<gp *> responseQueue;
tlm_utils::peq_with_cb_and_phase<Controller> frontendPEQ;
tlm_utils::peq_with_cb_and_phase<Controller> dramPEQ;

2
DRAMSys/library/src/controller/core/ControllerCore.cpp
View File

@@ -169,7 +169,7 @@ bool ControllerCore::scheduleRequest(Command command,
sc_time start = clkAlign(sc_time_stamp());
state->cleanUp(start);
ScheduledCommand scheduledCommand = schedule(command, start, payload);
if (config.ControllerCoreRefDisable == true) {
if (config.ControllerCoreRefDisable) {
state->change(scheduledCommand);
controller.send(scheduledCommand, payload);
return true;

3
DRAMSys/library/src/controller/core/configuration/Configuration.h
View File

@@ -54,7 +54,8 @@ enum class EPowerDownMode {NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF};
enum class ECCControllerMode {Disabled, Hamming};
struct Configuration {
struct Configuration
{
static std::string memspecUri;
static std::string mcconfigUri;
std::string pathToResources;

2
DRAMSys/library/src/controller/scheduler/Fifo.cpp
View File

@@ -57,7 +57,9 @@ std::pair<Command, tlm::tlm_generic_payload *> Fifo::getNextRequest(Bank bank)
return std::pair<Command, tlm::tlm_generic_payload *>(command, payload);
}
else
{
return std::pair<Command, tlm::tlm_generic_payload *>(Command::NOP, NULL);
}
}
gp *Fifo::getPendingRequest(Bank /*bank*/)

4
DRAMSys/library/src/controller/scheduler/Fifo.h
View File

@@ -52,8 +52,8 @@ public:
virtual ~Fifo() {}
void storeRequest(gp *payload) override;
std::pair<Command, tlm::tlm_generic_payload *> getNextRequest(
Bank bank) override;
std::pair<Command, tlm::tlm_generic_payload *>
getNextRequest(Bank bank) override;
virtual gp *getPendingRequest(Bank bank) override;
private:

22
DRAMSys/library/src/controller/scheduler/IScheduler.cpp
View File

@@ -50,13 +50,18 @@ void IScheduler::printDebugMessage(std::string message)
Command IScheduler::getNextCommand(gp &payload)
{
Bank bank = DramExtension::getBank(payload);
if (!controllerCore.getRowBufferStates().rowBufferIsOpen(bank)) {
if (!controllerCore.getRowBufferStates().rowBufferIsOpen(bank))
{
return Command::Activate;
} else if (controllerCore.getRowBufferStates().rowBufferIsOpen(bank) &&
}
else if (controllerCore.getRowBufferStates().rowBufferIsOpen(bank) &&
controllerCore.getRowBufferStates().getRowInRowBuffer(bank) !=
DramExtension::getRow(payload)) {
DramExtension::getRow(payload))
{
return Command::Precharge;
} else {
}
else
{
return getReadWriteCommand(payload);
}
}
@@ -68,13 +73,15 @@ Command IScheduler::getNextCommand(gp *payload)
Command IScheduler::getReadWriteCommand(gp &payload)
{
if (payload.get_command() == tlm::TLM_READ_COMMAND) {
if (payload.get_command() == tlm::TLM_READ_COMMAND)
{
if (Configuration::getInstance().OpenPagePolicy)
return Command::Read;
else
return Command::ReadA;
} else {
}
else
{
if (Configuration::getInstance().OpenPagePolicy)
return Command::Write;
else
@@ -86,3 +93,4 @@ Command IScheduler::getReadWriteCommand(gp *payload)
{
return getReadWriteCommand(*payload);
}