From 02803de97cdfc3ec6c592b89b3c3dc35b93118a5 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 11 Jun 2019 23:10:45 +0200 Subject: [PATCH] Code refactoring. --- DRAMSys/library/src/controller/Controller.cpp | 52 ++++++++++++------- DRAMSys/library/src/controller/Controller.h | 4 +- .../src/controller/core/ControllerCore.cpp | 2 +- .../core/configuration/Configuration.h | 3 +- .../library/src/controller/scheduler/Fifo.cpp | 2 + .../library/src/controller/scheduler/Fifo.h | 4 +- .../src/controller/scheduler/IScheduler.cpp | 22 +++++--- 7 files changed, 56 insertions(+), 33 deletions(-) diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 844e5d09..27055763 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -451,47 +451,59 @@ void Controller::dramPEQCallback(tlm_generic_payload &payload, printDebugMessage("Received " + phaseNameToString(phase) + " on bank " + to_string(bank.ID()) + " from DRAM"); - if (phase == END_RD || phase == END_WR) { - if(responseQueue.empty()) { + if (phase == END_RD || phase == END_WR) + { + if(responseQueue.empty()) sendToFrontend(payload, BEGIN_RESP, SC_ZERO_TIME); - } + responseQueue.push(&payload); - } else if (phase == END_RDA || phase == END_WRA) { - if(responseQueue.empty()) { + } + else if (phase == END_RDA || phase == END_WRA) + { + if(responseQueue.empty()) sendToFrontend(payload, BEGIN_RESP, SC_ZERO_TIME); - } + responseQueue.push(&payload); scheduleNextFromScheduler(bank); - } else if (phase == END_REFA) { + } + else if (phase == END_REFA) + { printDebugMessage("Finished auto refresh on all banks "); bool sleepy = true; - for (Bank bank : controllerCore->getBanks()) { - if (numberOfPayloadsInSystem[bank] != 0) { + for (Bank bank : controllerCore->getBanks()) + { + if (numberOfPayloadsInSystem[bank] != 0) + { sleepy = false; scheduleNextFromScheduler(bank); } } - - if (sleepy == true) { + if (sleepy == true) controllerCore->powerDownManager->sleep(0, sc_time_stamp()); - } - } else if (phase == END_REFB) { + } + else if (phase == END_REFB) + { printDebugMessage("Finished auto refresh on bank " + to_string(bank.ID())); - if (numberOfPayloadsInSystem[bank] == 0) { + if (numberOfPayloadsInSystem[bank] == 0) controllerCore->powerDownManager->sleep(bank, sc_time_stamp()); - } else { + else scheduleNextFromScheduler(bank); - } - scheduleNextFromScheduler(bank); - } else if (containsPhase(phase, {END_PREB, END_PRE, END_ACTB, END_ACT})) { + scheduleNextFromScheduler(bank); } - else if (phase == END_PRE_ALL) { + else if (containsPhase(phase, {END_PREB, END_PRE, END_ACTB, END_ACT})) + { + scheduleNextFromScheduler(bank); + } + else if (phase == END_PRE_ALL) + { // No need to trigger anything for a END_PRE_ALL. It is followed by a AUTO_REFRESH anyway (in our current // scheduler implementation) - } else { + } + else + { string str = string("DRAM PEQ in controller wrapper was triggered with unsupported phase ") + phaseNameToString(phase); diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index 97ec9e73..8df4f8b0 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -145,9 +145,9 @@ protected: //Scheduler* scheduler; IScheduler *scheduler; std::map numberOfPayloadsInSystem; - std::vector refreshCollisionRequets; + std::vector refreshCollisionRequets; tlm::tlm_generic_payload *backpressure = NULL; - std::queue responseQueue; + std::queue responseQueue; tlm_utils::peq_with_cb_and_phase frontendPEQ; tlm_utils::peq_with_cb_and_phase dramPEQ; diff --git a/DRAMSys/library/src/controller/core/ControllerCore.cpp b/DRAMSys/library/src/controller/core/ControllerCore.cpp index 63069368..ba8d1ebe 100644 --- a/DRAMSys/library/src/controller/core/ControllerCore.cpp +++ b/DRAMSys/library/src/controller/core/ControllerCore.cpp @@ -169,7 +169,7 @@ bool ControllerCore::scheduleRequest(Command command, sc_time start = clkAlign(sc_time_stamp()); state->cleanUp(start); ScheduledCommand scheduledCommand = schedule(command, start, payload); - if (config.ControllerCoreRefDisable == true) { + if (config.ControllerCoreRefDisable) { state->change(scheduledCommand); controller.send(scheduledCommand, payload); return true; diff --git a/DRAMSys/library/src/controller/core/configuration/Configuration.h b/DRAMSys/library/src/controller/core/configuration/Configuration.h index c20e35f7..37b7f4ea 100644 --- a/DRAMSys/library/src/controller/core/configuration/Configuration.h +++ b/DRAMSys/library/src/controller/core/configuration/Configuration.h @@ -54,7 +54,8 @@ enum class EPowerDownMode {NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF}; enum class ECCControllerMode {Disabled, Hamming}; -struct Configuration { +struct Configuration +{ static std::string memspecUri; static std::string mcconfigUri; std::string pathToResources; diff --git a/DRAMSys/library/src/controller/scheduler/Fifo.cpp b/DRAMSys/library/src/controller/scheduler/Fifo.cpp index 305e2798..71e098b6 100644 --- a/DRAMSys/library/src/controller/scheduler/Fifo.cpp +++ b/DRAMSys/library/src/controller/scheduler/Fifo.cpp @@ -57,7 +57,9 @@ std::pair Fifo::getNextRequest(Bank bank) return std::pair(command, payload); } else + { return std::pair(Command::NOP, NULL); + } } gp *Fifo::getPendingRequest(Bank /*bank*/) diff --git a/DRAMSys/library/src/controller/scheduler/Fifo.h b/DRAMSys/library/src/controller/scheduler/Fifo.h index dfb5820c..14a9f34c 100644 --- a/DRAMSys/library/src/controller/scheduler/Fifo.h +++ b/DRAMSys/library/src/controller/scheduler/Fifo.h @@ -52,8 +52,8 @@ public: virtual ~Fifo() {} void storeRequest(gp *payload) override; - std::pair getNextRequest( - Bank bank) override; + std::pair + getNextRequest(Bank bank) override; virtual gp *getPendingRequest(Bank bank) override; private: diff --git a/DRAMSys/library/src/controller/scheduler/IScheduler.cpp b/DRAMSys/library/src/controller/scheduler/IScheduler.cpp index 09d53b47..2a9b6eff 100644 --- a/DRAMSys/library/src/controller/scheduler/IScheduler.cpp +++ b/DRAMSys/library/src/controller/scheduler/IScheduler.cpp @@ -50,13 +50,18 @@ void IScheduler::printDebugMessage(std::string message) Command IScheduler::getNextCommand(gp &payload) { Bank bank = DramExtension::getBank(payload); - if (!controllerCore.getRowBufferStates().rowBufferIsOpen(bank)) { + if (!controllerCore.getRowBufferStates().rowBufferIsOpen(bank)) + { return Command::Activate; - } else if (controllerCore.getRowBufferStates().rowBufferIsOpen(bank) && + } + else if (controllerCore.getRowBufferStates().rowBufferIsOpen(bank) && controllerCore.getRowBufferStates().getRowInRowBuffer(bank) != - DramExtension::getRow(payload)) { + DramExtension::getRow(payload)) + { return Command::Precharge; - } else { + } + else + { return getReadWriteCommand(payload); } } @@ -68,13 +73,15 @@ Command IScheduler::getNextCommand(gp *payload) Command IScheduler::getReadWriteCommand(gp &payload) { - - if (payload.get_command() == tlm::TLM_READ_COMMAND) { + if (payload.get_command() == tlm::TLM_READ_COMMAND) + { if (Configuration::getInstance().OpenPagePolicy) return Command::Read; else return Command::ReadA; - } else { + } + else + { if (Configuration::getInstance().OpenPagePolicy) return Command::Write; else @@ -86,3 +93,4 @@ Command IScheduler::getReadWriteCommand(gp *payload) { return getReadWriteCommand(*payload); } +