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No changes, some TODOs for future work.

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This commit is contained in:
Lukas Steiner
2019-06-10 00:52:26 +02:00
parent 84bd62a781
commit 4454b82363
6 changed files with 48 additions and 49 deletions
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47
DRAMSys/library/src/common/dramExtension.h
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@@ -45,15 +45,13 @@
class Thread
{
public:
explicit Thread(unsigned int id) :
id(id)
{
}
explicit Thread(unsigned int id) : id(id) {}
unsigned int ID() const
{
return id;
}
private:
unsigned int id;
};
@@ -61,14 +59,13 @@ private:
class Channel
{
public:
explicit Channel(unsigned int id) :
id(id)
{
}
explicit Channel(unsigned int id) : id(id) {}
unsigned int ID() const
{
return id;
}
private:
unsigned int id;
};
@@ -76,14 +73,13 @@ private:
class BankGroup
{
public:
explicit BankGroup(unsigned int id) :
id(id)
{
}
explicit BankGroup(unsigned int id) : id(id) {}
unsigned int ID() const
{
return id;
}
private:
unsigned int id;
};
@@ -91,10 +87,8 @@ private:
class Bank
{
public:
Bank(unsigned int id) :
id(id)
{
}
Bank(unsigned int id) : id(id) {}
unsigned int ID() const
{
return id;
@@ -110,7 +104,6 @@ public:
return std::to_string(id);
}
private:
unsigned int id;
};
@@ -120,14 +113,9 @@ class Row
public:
static const Row NO_ROW;
Row() :
id(0), isNoRow(true)
{
}
explicit Row(unsigned int id) :
id(id), isNoRow(false)
{
}
Row() : id(0), isNoRow(true) {}
explicit Row(unsigned int id) : id(id), isNoRow(false) {}
unsigned int ID() const
{
@@ -135,6 +123,7 @@ public:
}
const Row operator++();
private:
unsigned int id;
bool isNoRow;
@@ -145,21 +134,19 @@ private:
class Column
{
public:
explicit Column(unsigned int id) :
id(id)
{
}
explicit Column(unsigned int id) : id(id) {}
unsigned int ID() const
{
return id;
}
private:
unsigned int id;
};
class DramExtension: public tlm::tlm_extension<DramExtension>
class DramExtension : public tlm::tlm_extension<DramExtension>
{
public:
DramExtension();

23
DRAMSys/library/src/controller/Controller.cpp
View File

@@ -39,6 +39,19 @@
#include "Controller.h"
#include <iostream>
Controller::Controller(sc_module_name /*name*/) :
frontendPEQ(this, &Controller::frontendPEQCallback),
dramPEQ(this, &Controller::dramPEQCallback),
controllerCorePEQ(this, &Controller::controllerCorePEQCallback),
debugManager(DebugManager::getInstance())
{
controllerCore = new ControllerCore("core", *this, numberOfPayloadsInSystem);
buildScheduler();
iSocket.register_nb_transport_bw(this, &Controller::nb_transport_bw);
tSocket.register_nb_transport_fw(this, &Controller::nb_transport_fw);
tSocket.register_transport_dbg(this, &Controller::transport_dbg);
}
void Controller::buildScheduler()
{
string selectedScheduler = Configuration::getInstance().Scheduler;
@@ -274,6 +287,7 @@ void Controller::frontendPEQCallback(tlm_generic_payload &payload,
return;
}
payload.set_response_status(tlm::TLM_OK_RESPONSE);
// tSocket->nb_transport_bw(*backpressure, END_REQ, SC_ZERO_TIME)
sendToFrontend(payload, END_REQ, SC_ZERO_TIME);
scheduler->storeRequest(&payload);
@@ -291,6 +305,7 @@ void Controller::frontendPEQCallback(tlm_generic_payload &payload,
{
printDebugMessage("##Backpressure released");
backpressure->set_response_status(tlm::TLM_OK_RESPONSE);
// tSocket->nb_transport_bw(*backpressure, END_REQ, SC_ZERO_TIME)
sendToFrontend(*backpressure, END_REQ, SC_ZERO_TIME);
scheduler->storeRequest(backpressure);
@@ -355,6 +370,7 @@ void Controller::scheduleNextFromScheduler(Bank bank)
if (controllerCore->bankIsBusy(bank))
return;
// TODO: rescheduled always true?
bool rescheduled = true;
pair<Command, tlm::tlm_generic_payload *> nextRequest =
scheduler->getNextRequest(bank);
@@ -363,8 +379,8 @@ void Controller::scheduleNextFromScheduler(Bank bank)
}
else
{
// TODO: getPendingRequest is only used by SMS scheduler
gp *pendingRequest = scheduler->getPendingRequest(bank);
// TODO: if path (pendingRequest != NULL) is only used by SMS scheduler
if (pendingRequest != NULL)
{
rescheduled = true;
@@ -373,8 +389,10 @@ void Controller::scheduleNextFromScheduler(Bank bank)
}
}
// TODO: only used with FifoStrict scheduler
queue<Bank> blocked;
while (!blockedRequests.empty()) {
while (!blockedRequests.empty())
{
bank = blockedRequests.front();
blockedRequests.pop();
@@ -387,6 +405,7 @@ void Controller::scheduleNextFromScheduler(Bank bank)
if (pendingRequest != NULL) {
//Pending request
if (!rescheduled) {
// TODO: never reached, rescheduled is always true
rescheduled = true;
frontendPEQ.notify(*(pendingRequest), PendingRequest,
Configuration::getInstance().memSpec.clk);

16
DRAMSys/library/src/controller/Controller.h
View File

@@ -81,18 +81,7 @@ DECLARE_EXTENDED_PHASE(PendingRequest);
class Controller : public sc_module, public IController
{
public:
Controller(sc_module_name /*name*/) :
frontendPEQ(this, &Controller::frontendPEQCallback),
dramPEQ(this, &Controller::dramPEQCallback),
controllerCorePEQ(this, &Controller::controllerCorePEQCallback),
debugManager(DebugManager::getInstance())
{
controllerCore = new ControllerCore("core", *this, numberOfPayloadsInSystem);
buildScheduler();
iSocket.register_nb_transport_bw(this, &Controller::nb_transport_bw);
tSocket.register_nb_transport_fw(this, &Controller::nb_transport_fw);
tSocket.register_transport_dbg(this, &Controller::transport_dbg);
}
Controller(sc_module_name);
virtual ~Controller()
{
@@ -112,8 +101,9 @@ public:
virtual void send(Trigger trigger, sc_time time,
tlm_generic_payload &payload) override;
tlm_utils::simple_initiator_socket<Controller> iSocket;
tlm_utils::simple_target_socket<Controller> tSocket;
tlm_utils::simple_initiator_socket<Controller> iSocket;
unsigned int getTotalNumberOfPayloadsInSystem();
void scheduleNextFromScheduler(Bank bank) override;

5
DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.h
View File

@@ -33,11 +33,13 @@
*/
#ifndef ACTB_CHECKER_H_
#define ACTB_CHECKER_H_
#include <map>
#include "ICommandChecker.h"
#include "../../configuration/Configuration.h"
#include "../../../ControllerState.h"
class ActBChecker: public ICommandChecker
class ActBChecker : public ICommandChecker
{
public:
ActBChecker(const Configuration &config,
@@ -53,4 +55,5 @@ private:
bool satsfies_activateToActivate_differentBank(ScheduledCommand &command) const;
bool satisfies_nActivateWindow(ScheduledCommand &command) const;
};
#endif /* ACTB_CHECKER_H_ */

2
DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp
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@@ -34,7 +34,7 @@
#include "PreBChecker.h"
#include "../../TimingCalculation.h"
void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd)const
void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const
{
sc_assert(cmd.getCommand() == Command::PreB);
ScheduledCommand lastCmd = state.getLastScheduledCommand(cmd.getBank());

4
DRAMSys/library/src/controller/scheduler/FifoStrict.cpp
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@@ -61,14 +61,14 @@ std::pair<Command, tlm::tlm_generic_payload *> FifoStrict::getNextRequest(
// enqueued request until the appropriate sequence of commands is
// sent to the DRAM.
//
// Every time getNextRequest() it is called it calls
// Every time getNextRequest() is called it calls
// getNextCommand() that returns the suitable command to be sent
// to the DRAM.
//
// getNextCommand() returns the proper command based on the
// internal status of the DRAM.
//
// In the worst case getNextCommand() need to be called three
// In the worst case getNextCommand() needs to be called three
// times for a given element in the requests queue: first for
// precharge, second for activate and finally for read or write
// (accordingly the nature of the request). In contrast, for the