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Included new controller classes.

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This commit is contained in:
Lukas Steiner (2)
2019-07-20 15:53:30 +02:00
parent 41e2db0b5a
commit cd5b5cb423
9 changed files with 196 additions and 17 deletions
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10
DRAMSys/library/library.pro
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@@ -149,7 +149,10 @@ SOURCES += \
src/simulation/DramWideIO.cpp \
src/controller/core/scheduling/checker/CheckerDDR3.cpp \
src/controller/core/configuration/MemSpec.cpp \
src/controller/core/scheduling/checker/CheckerDDR3New.cpp
src/controller/core/scheduling/checker/CheckerDDR3New.cpp \
src/controller/BankMachine.cpp \
src/controller/CommandMux.cpp \
src/controller/ControllerNew.cpp
HEADERS += \
src/common/third_party/tinyxml2/tinyxml2.h \
@@ -232,7 +235,10 @@ HEADERS += \
src/simulation/DramWideIO.h \
src/controller/core/scheduling/checker/CheckerDDR3.h \
src/controller/GenericController.h \
src/controller/core/scheduling/checker/CheckerDDR3New.h
src/controller/core/scheduling/checker/CheckerDDR3New.h \
src/controller/BankMachine.h \
src/controller/CommandMux.h \
src/controller/ControllerNew.h
#src/common/third_party/json/include/nlohmann/json.hpp \
thermalsim = $$(THERMALSIM)

13
DRAMSys/library/src/controller/BankMachine.cpp Normal file
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@@ -0,0 +1,13 @@
#include "BankMachine.h"
#include "Command.h"
BankMachine::BankMachine(ControllerNew &controller) :
currentPayload(nullptr),
currentState(BmState::Precharged),
currentRow(Row(0)),
nextCommand(Command::NOP),
earliestTime(SC_ZERO_TIME),
controller(controller)
{
}

32
DRAMSys/library/src/controller/BankMachine.h Normal file
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@@ -0,0 +1,32 @@
#ifndef BANKMACHINE_H
#define BANKMACHINE_H
#include <systemc.h>
#include <tlm.h>
#include "../common/dramExtensions.h"
#include "Command.h"
using namespace tlm;
class ControllerNew;
enum class BmState
{
Precharged,
Activated
};
class BankMachine
{
public:
BankMachine(ControllerNew &);
private:
tlm_generic_payload *currentPayload;
BmState currentState;
Row currentRow;
Command nextCommand;
sc_time earliestTime;
ControllerNew &controller;
};
#endif // BANKMACHINE_H

22
DRAMSys/library/src/controller/CommandMux.cpp Normal file
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@@ -0,0 +1,22 @@
#include "CommandMux.h"
#include "core/configuration/Configuration.h"
CommandMux::CommandMux(sc_module_name name, ControllerNew &controller) :
sc_module(name),
controller(controller),
state("CommandMux", &Configuration::getInstance()),
checker(Configuration::getInstance(), state)
{
SC_METHOD(compute);
sensitive << triggerEvent;
}
void CommandMux::triggerAtTime(sc_time triggerTime)
{
triggerEvent.notify(triggerTime);
}
void CommandMux::compute()
{
}

27
DRAMSys/library/src/controller/CommandMux.h Normal file
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@@ -0,0 +1,27 @@
#ifndef COMMANDMUX_H
#define COMMANDMUX_H
#include <systemc.h>
#include <tlm.h>
#include "ControllerState.h"
#include "core/scheduling/checker/CheckerDDR3New.h"
using namespace tlm;
class ControllerNew;
class CommandMux : public sc_module
{
public:
CommandMux(sc_module_name, ControllerNew &);
SC_HAS_PROCESS(CommandMux);
void triggerAtTime(sc_time triggerTime);
private:
void compute();
sc_event triggerEvent;
ControllerState state;
CheckerDDR3New checker;
ControllerNew &controller;
};
#endif // COMMANDMUX_H

36
DRAMSys/library/src/controller/ControllerNew.cpp Normal file
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@@ -0,0 +1,36 @@
#include "ControllerNew.h"
#include "core/configuration/Configuration.h"
#include "scheduler/FifoStrict.h"
ControllerNew::ControllerNew(sc_module_name name) :
sc_module(name), commandMux("CommandMux", *this)
{
tSocket.register_nb_transport_fw(this, &ControllerNew::nb_transport_fw);
tSocket.register_transport_dbg(this, &ControllerNew::transport_dbg);
iSocket.register_nb_transport_bw(this, &ControllerNew::nb_transport_bw);
for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++)
bankMachines[Bank(bankID)] = std::unique_ptr<BankMachine>(new BankMachine(*this));
}
ControllerNew::~ControllerNew()
{
}
tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans,
tlm_phase &phase, sc_time &delay)
{
}
unsigned int ControllerNew::transport_dbg(__attribute__((unused)) tlm_generic_payload &trans)
{
SC_REPORT_FATAL("ControllerNew", "Debug Transport not supported");
return 0;
}
tlm_sync_enum ControllerNew::nb_transport_bw(tlm_generic_payload &trans,
tlm_phase &phase, sc_time &delay)
{
}

38
DRAMSys/library/src/controller/ControllerNew.h Normal file
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@@ -0,0 +1,38 @@
#ifndef CONTROLLERNEW_H
#define CONTROLLERNEW_H
#include <map>
#include <systemc.h>
#include <tlm.h>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include "../common/dramExtensions.h"
#include "BankMachine.h"
#include "CommandMux.h"
#include "scheduler/IScheduler.h"
using namespace tlm;
class ControllerNew : public sc_module
{
public:
ControllerNew(sc_module_name);
SC_HAS_PROCESS(ControllerNew);
~ControllerNew();
tlm_utils::simple_target_socket<ControllerNew> tSocket;
tlm_utils::simple_initiator_socket<ControllerNew> iSocket;
private:
tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans,
tlm_phase &phase, sc_time &delay);
unsigned int transport_dbg(tlm_generic_payload &trans);
tlm_sync_enum nb_transport_bw(tlm_generic_payload &trans,
tlm_phase &phase, sc_time &delay);
std::map<Bank, std::unique_ptr<BankMachine>> bankMachines;
CommandMux commandMux;
IScheduler *scheduler;
};
#endif // CONTROLLERNEW_H

31
DRAMSys/library/src/simulation/DRAMSys.cpp
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@@ -58,6 +58,7 @@
#include "DramDDR3.h"
#include "DramDDR4.h"
#include "DramWideIO.h"
#include "../controller/ControllerNew.h"
using namespace std;
@@ -247,17 +248,19 @@ void DRAMSys::instantiateModules(const string &traceName,
// Create DRAM
std::string memoryType = Configuration::getInstance().memSpec->MemoryType;
for (size_t i = 0;
i < Configuration::getInstance().NumberOfMemChannels;
i++) {
for (size_t i = 0; i < Configuration::getInstance().NumberOfMemChannels; i++)
{
std::string str = "controller" + std::to_string(i);
GenericController *controller;
if (recordingEnabled)
controller = new RecordableController(str.c_str(), tlmRecorders[i]);
else
controller = new Controller(str.c_str());
controllers.push_back(controller);
// GenericController *controller;
// if (recordingEnabled)
// controller = new RecordableController(str.c_str(), tlmRecorders[i]);
// else
// controller = new Controller(str.c_str());
// controllers.push_back(controller);
ControllerNew *controller = new ControllerNew(str.c_str());
newControllers.push_back(controller);
str = "dram" + std::to_string(i);
Dram *dram;
@@ -315,15 +318,15 @@ void DRAMSys::bindSockets()
i++) {
arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket);
controllersTlmCheckers[i]->initiator_socket.bind(
controllers[i]->tSocket);
controllers[i]->iSocket.bind(drams[i]->tSocket);
newControllers[i]->tSocket);
newControllers[i]->iSocket.bind(drams[i]->tSocket);
}
} else {
for (size_t i = 0;
i < Configuration::getInstance().NumberOfMemChannels;
i++) {
arbiter->iSocket.bind(controllers[i]->tSocket);
controllers[i]->iSocket.bind(drams[i]->tSocket);
arbiter->iSocket.bind(newControllers[i]->tSocket);
newControllers[i]->iSocket.bind(drams[i]->tSocket);
}
}
}
@@ -351,7 +354,7 @@ DRAMSys::~DRAMSys()
delete tlmChecker;
}
for (auto controller : controllers) {
for (auto controller : newControllers) {
delete controller;
}
}

4
DRAMSys/library/src/simulation/DRAMSys.h
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@@ -53,6 +53,7 @@
#include "../common/tlm2_base_protocol_checker.h"
#include "../error/eccbaseclass.h"
#include "../controller/GenericController.h"
#include "../controller/ControllerNew.h"
class DRAMSys : public sc_module
{
@@ -88,7 +89,8 @@ private:
// All transactions pass through the same arbiter
Arbiter *arbiter;
// Each DRAM unit has a controller
std::vector<GenericController *> controllers;
std::vector<ControllerNew *> newControllers;
//std::vector<GenericController *> controllers;
// TODO: Each DRAM has a reorder buffer (check this!)
ReorderBuffer *reorder;