derek/DRAMSys
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Minor changes in new timing checker.

Browse Source
This commit is contained in:
Lukas Steiner (2)
2019-07-16 15:52:02 +02:00
parent be83ad01cb
commit f43ea71e95
4 changed files with 58 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

55
DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.xml Normal file
View File

@@ -0,0 +1,55 @@
<!DOCTYPE memspec SYSTEM "memspec.dtd">
<memspec>
<parameter id="memoryId" type="string" value="MICRON_1Gb_DDR3-800_8bit_G" />
<parameter id="memoryType" type="string" value="DDR3" />
<memarchitecturespec>
<parameter id="width" type="uint" value="8" />
<parameter id="nbrOfBanks" type="uint" value="8" />
<parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfColumns" type="uint" value="1024" />
<parameter id="nbrOfRows" type="uint" value="16384" />
<parameter id="dataRate" type="uint" value="2" />
<parameter id="burstLength" type="uint" value="8" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="400" />
<parameter id="RC" type="uint" value="20" /> <!-- 50 ns -->
<parameter id="RCD" type="uint" value="5" /> <!-- 12.5 ns -->
<parameter id="RL" type="uint" value="5" /> <!-- 12.5 ns -->
<parameter id="RP" type="uint" value="5" /> <!-- 12.5 ns -->
<parameter id="RFC" type="uint" value="44" /> <!-- 110 ns for 1Gb -->
<parameter id="RAS" type="uint" value="15" /> <!-- 37.5 ns -->
<parameter id="WL" type="uint" value="5" /> <!-- jedec 5 clk cycles -->
<parameter id="AL" type="uint" value="0" />
<parameter id="DQSCK" type="uint" value="0" /> <!-- 0.4 ns -->
<parameter id="RTP" type="uint" value="4" /> <!-- 4 clk cycles -->
<parameter id="WR" type="uint" value="6" /> <!-- 15 ns -->
<parameter id="XP" type="uint" value="3" /> <!-- 3 clk cycles -->
<parameter id="XPDLL" type="uint" value="10" /> <!-- 10 clk cycles -->
<parameter id="XS" type="uint" value="48" /> <!-- 110ns + 10ns -->
<parameter id="XSDLL" type="uint" value="512" /> <!-- 512 clk cycles ns -->
<parameter id="REFI" type="uint" value="3120" /> <!-- 78 000 ns -->
<parameter id="CL" type="uint" value="5" /> <!-- jedec 5 clk cycles -->
<parameter id="FAW" type="uint" value="16" /> <!-- 40 ns -->
<parameter id="RRD" type="uint" value="4" /> <!-- 4 clk cycles -->
<parameter id="CCD" type="uint" value="4" /> <!-- 4 clk cycles -->
<parameter id="WTR" type="uint" value="4" /> <!-- 4 clk cycles -->
<parameter id="CKE" type="uint" value="3" /> <!-- 3 clk cycles -->
<parameter id="CKESR" type="uint" value="4" /> <!-- 4 clk cycles -->
</memtimingspec>
<mempowerspec>
<parameter id="idd0" type="double" value="60.0" />
<parameter id="idd2p0" type="double" value="12.0" />
<parameter id="idd2p1" type="double" value="25.0" />
<parameter id="idd2n" type="double" value="35.0" />
<parameter id="idd3p0" type="double" value="30.0" />
<parameter id="idd3p1" type="double" value="30.0" />
<parameter id="idd3n" type="double" value="40.0" />
<parameter id="idd4w" type="double" value="110.0" />
<parameter id="idd4r" type="double" value="105.0" />
<parameter id="idd5" type="double" value="160.0" />
<parameter id="idd6" type="double" value="8.0" />
<parameter id="vdd" type="double" value="1.5" />
</mempowerspec>
</memspec>

1
DRAMSys/library/src/controller/Controller.cpp
View File

@@ -305,7 +305,6 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &payload,
else if (phase == END_RESP)
{
// Bandwidth IDLE
// TODO: getTotalNumberOfPayloadsInSystem() == 1 && !idleState ??
if (getTotalNumberOfPayloadsInSystem() == 1)
startBandwidthIdleCollector();
}

12
DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp
View File

@@ -55,7 +55,9 @@ void CheckerDDR3New::delayToSatisfyConstraints(ScheduledCommand &command) const
if (lastCommand.isValidCommand())
command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXS);
delayToSatisfyACTtoACTsameBank(command);
lastCommand = state.getLastCommand(Command::ACT, command.getBank());
if (lastCommand.isValidCommand())
command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRC);
while (!(state.bus.isFree(command.getStart()) && satsfiesACTtoACTdifferentBank(command) && satisfiesNActivateWindow(command)))
command.delayStart(memSpec->clk);
@@ -373,14 +375,6 @@ void CheckerDDR3New::delayToSatisfyConstraints(ScheduledCommand &command) const
/*
* ActivateChecker
*/
void CheckerDDR3New::delayToSatisfyACTtoACTsameBank(ScheduledCommand &command) const
{
ScheduledCommand lastActivateOnBank = state.getLastCommand(Command::ACT, command.getBank());
if (lastActivateOnBank.isValidCommand())
command.establishMinDistanceFromStart(lastActivateOnBank.getStart(), memSpec->tRC);
}
bool CheckerDDR3New::satsfiesACTtoACTdifferentBank(ScheduledCommand &command) const
{
for (auto act : state.lastActivates)

1
DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h
View File

@@ -24,7 +24,6 @@ private:
MemSpecDDR3 *memSpec;
//Activate
void delayToSatisfyACTtoACTsameBank(ScheduledCommand &command) const;
bool satsfiesACTtoACTdifferentBank(ScheduledCommand &command) const;
bool satisfiesNActivateWindow(ScheduledCommand &command) const;